distrib/docxml2/text/doc/hitas_user/abstraction_guidelines.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>
   2 <chapter>
   3 <section niv='1'><title>Timing Characterization (.lib)</title>
   4
   5 <section niv='2'><title>Setup and Hold Constraints Formulas</title>
   6 <p>Interface Setup and hold constraints are computed for each latch and register. They are computed with respect to
   7 the following formulas:</p>
   8 <code>
   9 <cl>setup = data_path_max - clock_path_min</cl>
  10 <cl>hold = clock_path_max - data_path_min</cl>
  11 </code>
  12 <p>The following diagram gives an example of clock path and data path.</p>
  13 <imgsize namehtml="Intrinsic.gif" namepdf="Intrinsic.svg"/>
  14 <list>
  15 <item>Clock path: from <f>ck</f> to <f>com</f> (the command of the latch)</item>
  16 <item>Data path: from <f>data</f> to <f>mem</f> (the memory point itself).</item>
  17 </list>
  18 <p>With such definitions
  19 of data and clock paths, the above formulas give optimistic values for setup and hold times. Therefore, a corrective factor
  20 is added to those values. The corrective factor for setup is called the "intrinsic setup of the latch"; the corrective factor
  21 for hold is called "intrinsic hold of the latch". The formulas now become:</p>
  22 <code>
  23 <cl>setup = data_path_max - clock_path_min + intrinsic_setup</cl>
  24 <cl>hold = clock_path_max - data_path_min + intrinsic_hold</cl>
  25 </code>
  26
  27 <section niv='3'><title>Setup Correction</title>
  28 <p>For setup time, the calculus is as follow:</p>
  29 <list>
  30 <item><f>clock_path_min</f> delay is computed at <f>com</f> crossing Vdd/2 (time <f>t1</f>), as the transitor <f>M</f>
  31 closes at time <f>t2</f>: <f>t2 - t1</f> must be added to <f>clock_path_min</f></item>
  32 <item>Setup time must ensure that data is correctly written into the latch, i.e. that data crosses the feedback loop. This is modeled by
  33 adding <f>t_loop</f> to <f>data_path_max</f>.</item>
  34 </list>
  35 <p>The formula for setup becomes:</p>
  36 <code>setup = data_path_max + t_loop - (clock_path_min + t2 - t1)</code>
  37 <p>The corrective factor for setup is:</p>
  38 <code>intrinsic_setup = t_loop - (t2 - t1)</code>
  39 </section>
  40
  41
  42 <section niv='3'><title>Hold Correction</title>
  43 <p>For hold time, the calculus is as follow:</p>
  44 <list>
  45 <item><f>clock_path_max</f> delay is computed at <f>com</f> crossing Vdd/2 (time <f>t1</f>), as the transitor <f>M</f>
  46 closes at time <f>t2</f>: <f>t2 - t1</f> must be added to <f>clock_path_max</f></item>
  47 </list>
  48 <p>The formula for hold becomes:</p>
  49 <code>hold = clock_path_max + (t2 - t1) - data_path_min</code>
  50 <p>The corrective factor for hold is:</p>
  51 <code>intrinsic_hold = t2 - t1</code>
  52 </section>
  53 </section>
  54
  55 <section niv='2'><title>Performing the Characterization</title>
  56 <p>The purpose of timing abstraction is to create a <f>.lib</f> file - containing setup, hold and access information
  57 of the design - from an already existing timing figure. Within the <f>avt_shell</f> Tcl interface, timing abstraction
  58 is performed with the function <f>tmabs</f></p>
  59 <p><f>BehFigure</f> is a description of the functionality that can be associated with the design in the <f>.lib</f> file.
  60 For the moment it takes the <f>NULL</f> value.</p>
  61 <p><f>TimingFigure</f> is the database itself, the one the <f>.lib</f> file will be created from. Timing abstraction
  62 only uses the <f>.dtx</f> file. The database can be obtained by two ways. Through
  63 the <f>hitas</f> function, with the appropriate configuration allowing correct database construction:</p>
  64 <code>
  65 <cl>avt_config ...</cl>
  66 <cl>avt_config ...</cl>
  67 <cl> </cl>
  68 <cl>set fig [hitas my_design]</cl>
  69 </code>
  70 <p>If the timing database has already been constructed, the path view can be obtained from the <f>.dtx</f> file with the
  71 following command:</p>
  72 <code>
  73 <cl>set fig [ttv_LoadSpecifiedTimingFigure my_design]</cl>
  74 </code>
  75 <p>Timing abstraction requires additionnal information concerning clock definition (in order to construct correct
  76 setup/hold/access relationships). Clock definition and timing abstraction are then done as follow:</p>
  77 <code>
  78 <cl>inf_SetFigureName my_design</cl>
  79 <cl>create_clock -period 3000 ck</cl>
  80 <cl>set abs_fig [tmabs $fig NULL * * *]</cl>
  81 </code>
  82 <p>The <f>-period</f> value is irrelevant but is needed to respect SDC syntax. The <f>.lib</f> file is
  83 generated from the abstracted timing figure <f>abs_fig</f> as follow:</p>
  84 <code>
  85 <cl>lib_DriveFile [list $abs_fig] NULL my_design.lib max</cl>
  86 </code>
  87
  88 </section>
  89
  90 <section niv='2'><title>Advanced Configuration</title>
  91 <section niv='3'><title>Input Slope and Output Load Axis</title>
  92 <p>User-defined input slopes can be defined with the function <f>inf_DefineSlopeRange</f>. This function affects
  93 the way lookup-table axis are constructed. Be aware that <f>inf_DefineSlopeRange</f> should be applied before calling the <f>hitas</f>
  94 function:</p>
  95 <code>
  96 <cl>inf_SetFigureName my_design</cl>
  97 <cl>inf_DefineSlopeRange default {100e-12 150e-12 350e-12} custom</cl>
  98 <cl>set fig [hitas my_design]</cl>
  99 </code>
 100
 101 <p>The same remarks apply to <f>inf_DefineCapacitanceRange</f>.</p>
 102
 103 </section>
 104 <section niv='3'><title>Capacitances in the .lib file</title>
 105 <p>By default, capacitance values are given for input connectors only, as an average value. The given value is
 106 the equivalent capacitance allowing to compute the driving gate's delay at vdd/2. Capacitance ranges as well as different
 107 rise/fall capacitances can be obtained by tuning the <f>elpCapaLevel</f> variable (values <f>1</f> or <f>2</f>).</p>
 108 <p>Capacitances can also be given for output connectors (set <f>tmaDriveCapaOut</f> variable to <f>yes</f>).
 109 In such a case, the output delay is given WITHOUT taking into account the output connector's capacitance.</p>
 110 </section>
 111
 112
 113
 114 </section>
 115
 116 <section niv='2'><title>Cell Library</title>
 117
 118 <p>Here is given an example Tcl script performing the timing abstraction of a list of
 119 standard cells, into a single <f>.lib</f> file:</p>
 120
 121 <code>
 122 <cl>avt_config tasBefig yes</cl>
 123 <cl>avt_config tmaFunctionalityMode w</cl>
 124 <cl> </cl>
 125 <cl>avt_LoadFile ./bsim3_018.tech spice</cl>
 126 <cl> </cl>
 127 <cl>foreach cell { ao2o22 ff2 inv mux2 na2 } {</cl>
 128 <cl>    avt_LoadFile $cell.spi spice</cl>
 129 <cl> </cl>
 130 <cl>    set fig [hitas $cell]</cl>
 131 <cl>    set beh_fig NULL</cl>
 132 <cl>    set abs_fig [tma_abstract $fig $beh_fig]</cl>
 133 <cl> </cl>
 134 <cl>    lappend fig_list $abs_fig</cl>
 135 <cl>    lappend beh_list $beh_fig</cl>
 136 <cl>}</cl>
 137 <cl> </cl>
 138 <cl>lib_drivefile $fig_list $beh_list "stdcells.lib" max</cl>
 139 </code>
 140 </section>
 141
 142
 143 </section></chapter>