distrib/docxml2/text/doc/hitas_user/overview.xml

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   2 <chapter>
   3 <section niv='1'><title>Overview</title>
   4
   5 <section niv='2'><title>Static Timing Analysis</title>
   6 <p>The advent of semiconductor fabrication technologies now allows high performance in complex
   7 integrated circuits.</p>
   8 <p>With the increasing complexity of these circuits, static timing analysis (STA)
   9 has revealed itself as the only feasible method ensuring that expected performances are
  10 actually obtained.</p>
  11 <p>In addition, signal integrity (SI) issues due to crosstalk play a crucial role in
  12 performance and reliability of these systems, and must be taken into account during
  13 the timing analysis.</p>
  14 <p>However, performance achievement not only lies in fabrication technologies, but also
  15 in the way circuits are designed. Very high performance designs are obtained with semi or
  16 full-custom designs techniques.</p>
  17 <p>The &tool; platform provides advanced STA and SI solutions at transistor level. It has
  18 been built-up in order to allow engineers to ensure complete timing and SI coverage on their digital
  19 custom designs, as well as IP-reuse through timing abstraction. </p>
  20 <p>Furthermore, hierarchy handling through transparent timing views allows full-chip
  21 verification, with virtually no limit of capacity in design size.</p>
  22 </section>
  23
  24 <section niv='2'><title>Signal Integrity Analysis </title>
  25 <p>&tool; crosstalk engine is coupled with static timing analysis (STA) engine and is based
  26 upon a multi-switching windows refinement algorithm.</p>
  27 <p>Crosstalk effects are then fully handled in timing checks. Precise delay update is done thanks
  28 to current source models for gate, and non-linear charge transfer models for effective wire load
  29 computation.</p>
  30 <p>Detailed SI report provides:</p>
  31 <list>
  32 <item>Delta-delays in gates and interconnects</item>
  33 <item>Effective noise contribution of each aggressor</item>
  34 <item>Overshoot and undershoot peaks, together with sensitivity of the fan-out gates</item>
  35 <item>Statistical noise classification allowing Engineering Change Orders</item>
  36 </list>
  37 <p>The graphical user interface (GUI) allows easy execution of the crosstalk analysis.</p>
  38 </section>
  39
  40 <section niv='2'><title>Applications</title>
  41 <p>&tool; can be used on a wide range of ICs, such as Micro-Processors, Micro-Controllers,
  42 Memory Controllers, Custom IPs or Standard-Cell Libraries (Arithmetic Units, Data-Paths...). It
  43 provides the following benefits:</p>
  44 <p>Timing sign-off</p>
  45 <list>
  46 <item>Digital custom macros STA sign-off</item>
  47 <item>Full-chip STA sign-off</item>
  48 </list>
  49 <p>Signal Integrity sign-off</p>
  50 <list>
  51 <item>Digital custom macros crosstalk analysis</item>
  52 <item>Full-chip crosstalk analysis</item>
  53 </list>
  54 <p>Design and debug</p>
  55 <list>
  56 <item>Circuit timing analysis during design phase</item>
  57 <item>Early detection of timing bottlenecks</item>
  58 </list>
  59 <p>IP Reuse (.lib files generation)</p>
  60 <list>
  61 <item>Digital custom macros characterization</item>
  62 <item>Standard cells re-characterization</item>
  63 </list>
  64 </section>
  65
  66 <section niv='2'><title>Key Features</title>
  67 <p>&tool; provides the following features:</p>
  68 <list>
  69 <item>Vector-free fast simulation engine, accuracy within 5% of SPICE</item>
  70 <item>Current Source Modeling (CSM) of drivers, AWE modeling of interconnects</item>
  71 <item>SPICE, VHDL or VERILOG netlist support, SPICE, SPEF or DSPF parasitics support, BSIM3 and BSIM4 support</item>
  72 <item>Design-style support: latch-based, domino logic, barrel shifters, multipliers</item>
  73 <item>Advanced timing checks: cycle sharing, cycle stealing, multicycle paths</item>
  74 <item>Full-Chip analysis through transparent hierarchy</item>
  75 <item>Cross corner analysis</item>
  76 <item>STA and SI coupled analysis</item>
  77 <item>Non-linear noise models</item>
  78 <item>Statistical noise classification</item>
  79 <item>GUI and Tcl interface</item>
  80 <item>Critical path automatic spice deck</item>
  81 <item>SDC timing constraints</item>
  82 </list>
  83 </section>
  84
  85 </section>
  86 </chapter>
  87
  88