distrib/docxml2/text/doc/hitas_user/sim_guidelines.xml

   1 <?xml version="1.0" encoding="ISO-8859-1" ?>
   2 <chapter>
   3 <section niv='1'><title>Spice Deck Generation</title>
   4 <p>The &tool; platform provides the means to generate a simulatable netlist of any timing
   5 path of the timing database. This generated simulatable netlist contains all the transistors
   6 that participate to the timing path. Actually, as a timing path runs through a set of cones (partitions),
   7 the simulatable netlist contains the transistors belonging to this set of cones. Transistors that do not
   8 directly participate to the path (out-of-path transistors) can be either modeled as blocked transistors or
   9 as equivalent capacitances.</p>
  10 <p>The path transistor netlist comes with all the stimuli enabling the propagation of the signal through the
  11 path. The tool automatically generates the stimuli enabling the appropriate transitions.
  12 The path transistor netlist and the stimuli form what is called the Spice Deck.</p>
  13 <p>The &tool; platform also provides the means to link with external Spice simulators for simulating
  14 the Spice Deck, and to get back the results for pertinent comparison of &tool; results.
  15 The accuracy of most of Spice simulators is heavily dependant on their operating mode (digital/analog)
  16 and on convergence configuration. Pertinent comparison of &tool; results should be made with simulators
  17 in the mode allowing the most accurate results.</p>
  18 <p>Path simulation is not available for hierarchical timing databases.</p>
  19
  20 <section niv='2'><title>Simulator Configuration</title>
  21 <p>First a few variables need to be set to control spice deck generation. They are related to the
  22 simulator being used. Supported simulators are:</p>
  23 <list>
  24 <item>ELDO (Mentor Graphics)</item>
  25 <item>HSPICE (Synopsys)</item>
  26 <item>TITAN (Infineon)</item>
  27 <item>NGSPICE (GEDA)</item>
  28 </list>
  29 <p>The minimal required configuration is as follow (example is given for ELDO):</p>
  30 <code>
  31 <cl># Spice deck target simulator</cl>
  32 <cl>avt_config SimToolModel eldo</cl>
  33 <cl> </cl>
  34 <cl># Simulator invoking (command line)</cl>
  35 <cl>avt_config avtSpiceString "/tools/eldo $"</cl>
  36 <cl> </cl>
  37 <cl># Transistor models (.INCLUDE to be added in spice deck)</cl>
  38 <cl>avt_config SimTechnologyName bsim3_018.tech</cl>
  39 </code>
  40
  41 <p>Setting the <f>SimToolModel</f> variable to a specific simulator also controls the default
  42 value of the following variables:</p>
  43 <list>
  44 <item><f>avtSpiceOutFile</f></item>
  45 <item><f>avtSpiceStdOutFile</f></item>
  46 <item><f>simSpiceOptions</f></item>
  47 <item><f>simExtractRule</f></item>
  48 <item><f>simMeasCmd</f></item>
  49 </list>
  50 <p>Be aware that setting values for those variable overwrite their default value.</p>
  51 </section>
  52
  53 <section niv='2'><title>Spice Deck Generation</title>
  54 <p>A spice deck is related to a timing path, and spice deck generation is based upon the detail
  55 of the timing path. Therefore, one should be able to get a timing path from a
  56 timing database before generating the spice deck. The following operations must be performed:</p>
  57 <code>
  58 <cl>set fig [ttv_LoadSpecifiedTimingFigure my_design]</cl>
  59 <cl>set paths [ttv_GetPaths $fig * * ?? 1 critic path max]</cl>
  60 <cl>set path [lindex $paths 0]</cl>
  61 <cl> </cl>
  62 <cl>set detail  [ttv_GetPathDetail $path]</cl>
  63 </code>
  64 <p>The spice deck generation is then done as follow:</p>
  65 <code>
  66 <cl>ttv_DriveSpiceDeck $fig $detail "path.spicedeck"</cl>
  67 </code>
  68 <p>This method only generates the spice deck file <f>path.spicedeck</f>. It does not allow the reading of the
  69 results for comparison. Thsi operation is described in the next section.</p>
  70
  71 </section>
  72
  73 <section niv='2'><title>Spice Deck Simulation</title>
  74 <p>Spice deck generation, simulator launch and result reading can be all done together within the
  75 function <f>ttv_DisplayPathListDetail</f>, given that it has been enabled through the <f>ttv_DisplayActivateSimulation</f>
  76 function. The <f>ttv_DisplayPathListDetail</f> requires a timing path as argument, but no timing detail. It
  77 gets it automatically:</p>
  78
  79 <code>
  80 <cl>set fig [ttv_LoadSpecifiedTimingFigure my_design]</cl>
  81 <cl>set paths [ttv_GetPaths $fig * * ?? 1 critic path max]</cl>
  82 <cl>set path [lindex $paths 0]</cl>
  83 <cl> </cl>
  84 <cl>ttv_SetupReport "ps ff"</cl>
  85 <cl>ttv_DisplayActivateSimulation y</cl>
  86 <cl>ttv_DisplayPathListDetail stdout $path</cl>
  87 </code>
  88
  89 <p>This script performs the following actions:</p>
  90 <list>
  91 <item>Gets the timing path <f>$path</f></item>
  92 <item>Activates the simulation engine</item>
  93 <item>Generates the spice deck: <f>my_design_ext.spi</f> and <f>cmd_my_design_ext.spi</f></item>
  94 <item>Performs the simulation: <f>/tools/eldo cmd_my_design_ext.spi</f></item>
  95 <item>Reads the simulation result: <f>cmd_my_design_ext.chi</f></item>
  96 <item>Prints the path detail on standard output, displaying &tool; and simulator delay and slope values</item>
  97 </list>
  98 </section>
  99
 100 <section niv='2'><title>Out-of-path Transistors</title>
 101 <p>The variable <f>simOutLoad</f> controls the way out-of-path transistors are modeled.</p>
 102 <p>If <f>simOutLoad</f> is set to <f>dynamic</f>, the tool transforms out-of-path transistors
 103 into equivalent capacitances in the spicedeck. In such a case transistor models are needed for the grid and source/drain
 104 capacitances evaluations. </p>
 105 <p>If <f>simOutLoad</f> is set to <f>transistor</f>, the tool does not transform out-of-path transistors into
 106 capacitances, but just print them in the spicedeck in a blocked configuration. In such a case the transistor models
 107 are not needed. One must be careful with this configuration, as the generated spice deck may be very big, for a
 108 very little accuracy gain.</p>
 109 <p>The load of a file containing transistor models (<f>bsim3_018.tech</f>) at the beginning of the script is necessary when
 110 <f>simOutLoad</f> is set to <f>dynamic</f>.</p>
 111 </section>
 112
 113 </section>
 114
 115 </chapter>