distrib/share/etc/ReleaseNotes3.3

   1 ###############################################################################
   2 # AvtTools version 3.3p25 Release Notes
   3 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
   4 # Mar 16th, 2009
   5 #
   6 ###############################################################################
   7
   8 # 1 - New functionalities
   9   - More intelligent choice of current path determining maximum delay in case
  10     where most resistive path is effectivly redundant.
  11   - New option to set default nominal temperature using either spicedeck or
  12     "simNominalTemperature" variable.
  13   - Proper parsing and handling of resistance temperature coefficients.
  14   - New option in GNS behavioural API to force driving of sequential blocks
  15     in Verilog regardles of the driver configuration settings.
  16   - Added API fflush.
  17   - New verilog driver setting "avtVerilogDriveConflict" to control drive
  18     of conflict condition.
  19   - Explicit instance connector orientation now also works when the model
  20     is not a transistor level.
  21   - Bleeders with series resistances are now detected automatically.
  22
  23 # 2 - Bug fixes
  24   - Corrected BSIM4 calculation issues which could lead to overflow for some
  25     parameter values.
  26   - Default nominal temperature now properly set by "simToolModel", i.e.
  27     25C for hspice, else 27C.
  28   - Verification of undeclared signals in the behavioural model.
  29   - Empty timing groups can no longer be driven in .LIB files.
  30   - Issue in gnsTraceFile.
  31   - Corrected some inconsistencies in bleeder and level-hold markings which
  32     could lead to non-detection or loss of stuck flag.
  33
  34 ###############################################################################
  35 # AvtTools version 3.3p24 Release Notes
  36 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
  37 # Feb 12th, 2009
  38 #
  39 ###############################################################################
  40
  41 # 1 - Bug fixes
  42   - Corrected bug in new glitcher detection setting.
  43   - Corrected bug causing user-defined bleeder marking to disappear in case
  44     of transfer-gate like structure.
  45
  46 ###############################################################################
  47 # AvtTools version 3.3p23 Release Notes
  48 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
  49 # Feb 11th, 2009
  50 #
  51 ###############################################################################
  52
  53 # 1 - New functionalities
  54   - New GNS pragma search option "stop_at_power_supplies" which can optimise
  55     search times of certain models when the instance connectors are power
  56     supplies.
  57   - The "yagDetectGlitchers" setting (default yes) now detects glitched current
  58     paths in CMOS dual gates, set to "nondual" to disable this.
  59   - New configuration "yagLoopOrientRatio" to control the relative size
  60     difference to allow orientation of double inverter loops.
  61   - Separate rise and fall wire delays in timed behavioural models.
  62
  63 # 2 - Bug fixes
  64   - Corrected bug in redundant current path detection.
  65   - Fixed some cases where non-latch inverter loops were not considered to be
  66     level-holds.
  67
  68 ###############################################################################
  69 # AvtTools version 3.3p22 Release Notes
  70 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
  71 # Feb 8th, 2009
  72 #
  73 ###############################################################################
  74
  75 # 1 - New functionalities
  76   - New configuration variable "avtSpiIgnoreCrypt" so that the .PROTECT and
  77     .UNPROTECT are ignored by the spice parser, otherwise they are considered
  78     to encapsulate encrypted data.
  79   - New configuration variable "yagPullupRatio" to specify how much more
  80     resistive a current path has to be in order to be considered as a
  81     pull-up or pull-down rather than stuck.
  82   - Logging of slope values for "delay_calc" log.
  83
  84 # 2 - Bug fixes
  85   - Correction for some missing signal correspondences for behavioural code
  86     generated by GNS.
  87
  88 ###############################################################################
  89 # AvtTools version 3.3p21 Release Notes
  90 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
  91 # Feb 3rd, 2009
  92 #
  93 ###############################################################################
  94
  95 # 1 - Bug fixes
  96   - Issue of missing delays in verilog when the new bus style (default) is
  97     used and the delays obtained by simulation.
  98
  99 ###############################################################################
 100 # AvtTools version 3.3p20 Release Notes
 101 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 102 # Jan 23rd, 2009
 103 #
 104 ###############################################################################
 105
 106 # 1 - New functionalities
 107   - Proper driving of power-rail definitions in .LIB files.
 108   - Proper handling of user-defined signal swing on input pins.
 109
 110 # 2 - Bug fixes
 111   - Coherent handling by TMA of pin names starting with digits.
 112   - Instance parameter "sca" no longer ignored.
 113   - Minor BSIM4 bug involving "toxe" and "epsrox" parameters.
 114   - Minor bug configuring between .print and .measure in generated spicedecks.
 115   - Correction for axes incoherency when redriving a parsed .LIB file.
 116   - Correction for schematic generation bug introduced by expression evaluator
 117     optimisation.
 118   - Behavioural model generation bug when memory nodes are on the interface.
 119   - Correction for resistive level-hold detection.
 120   - Possible fatal error in asynchronous command detection.
 121
 122 # 3 - Configuration changes
 123   - Configuration variable "tmaLibCellSyntax" removed since cell and macro
 124     .LIB files are now identical.
 125
 126 ###############################################################################
 127 # AvtTools version 3.3p19 Release Notes
 128 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 129 # Nov 18th, 2008
 130 #
 131 ###############################################################################
 132
 133 # 1 - New functionalities
 134   - New API "ttv_PlotPathDetail" to generate HiTAS waveform plots for all nodes
 135     on a timing path.
 136   - New option to API ttv_SimulatePath to generate waveforms plots from
 137     simulation results.
 138   - New setting "yagLevelHoldAnalysis" to generate bus style behavioural models
 139     for level-hold nodes.
 140   - New Verilog behavioural driver option "avtVerilogOldStyleBus" to model
 141     bussed signals using conditional continuous assignments.
 142   - New Verilog behavioural driver option "avtVerilogTristateIsMemory" to add
 143     a memorizing process to all bussed signals.
 144   - New Verilog behavioural driver option "avtVerilogInertialMemory" to model
 145     latches using conditional continuous assignments and a memorizing process.
 146   - Verilog behaviour modeling improvements.
 147   - New option "yagSingleDelayRatio" to use identical timing for drivers in
 148     a process which similar timing. This avoids race problems.
 149   - New option "yagDriveConflictCondition" to drive the real conflict condition
 150     after latch or bus analysis.
 151   - Bus anlysis no longer abandons when conflict conditions exist but has no
 152     effect if no explicit data inputs can be identified.
 153
 154 # 2 - Bug fixes
 155   - BSIM4 current calculation bug in some cases of very small current
 156     contributions.
 157   - Correction in the timing calculation in the case of parallel transistors
 158     with very different lengths.
 159   - Corrected bug in timing figure cleaning in some cases of black box
 160     connectors.
 161   - Proper behavioural expression generation for latches which have a real
 162     high impedance condition.
 163
 164 # 3 - Configuration changes
 165   - Glitcher detection is now on by default.
 166
 167 ###############################################################################
 168 # AvtTools version 3.3p18 Release Notes
 169 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 170 # Oct 14th, 2008
 171 #
 172 ###############################################################################
 173
 174 # 1 - New functionalities
 175   - Bus processes are now always in the form IF-ELSEIF-...-ELSEIF-ELSE HZ to
 176     avoid non active IF to set the BUS in HZ state.
 177
 178 # 3 - Configuration changes
 179   - yagSplitTimingRatio is now set to 0 by default.
 180
 181 ###############################################################################
 182 # AvtTools version 3.3p17 Release Notes
 183 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 184 # Oct 11th, 2008
 185 #
 186 ###############################################################################
 187
 188 # 1 - New functionalities
 189   - Support for native rising and falling delay specification in verilog
 190     assignments.
 191
 192 ###############################################################################
 193 # AvtTools version 3.3p16 Release Notes
 194 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 195 # Oct 11th, 2008
 196 #
 197 ###############################################################################
 198
 199 # 1 - New functionalities
 200   - Explicit RC delays in Yagle generated behavioural models.
 201     This mode is enabled by tasMergeRCAndGateDelays=no. It's the default.
 202   - More tolerant glitcher detection with new configuration variable
 203     "yagMaxGlitcherLinks", an integer value which specifies the maximum
 204     number of links beyond which no glitcher detection is done (default is 3)
 205
 206 # 2 - Bug fixes
 207   - Possible crash in GNS with blackboxes with RC on their pins when executing
 208     actions involving simulations.
 209   - Issue which prevented latch detection when the feedback loop was
 210     conflictual.
 211   - Issue preventing RS detection when one of the gates had additional
 212     conflictual drivers.
 213   - Issue which prevented marking of redundancy when bleeders or level-holds
 214     were present.
 215
 216 ###############################################################################
 217 # AvtTools version 3.3p15 Release Notes
 218 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 219 # Oct 9th, 2008
 220 #
 221 ###############################################################################
 222
 223 # 1 - New functionalities
 224   - Yagle sensitive timing support for verilog models.
 225   - Double inverter loops which are not latches are considered level-holds.
 226
 227 # 2 - Bug fixes
 228   - Stuck loops are no longer reported as unknown loops.
 229   - Fixed possible fatal error in RC delay calculation for hierarchical Yagle.
 230
 231 ###############################################################################
 232 # AvtTools version 3.3p14 Release Notes
 233 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 234 # Oct 8th, 2008
 235 #
 236 ###############################################################################
 237
 238 # 1 - New functionalities
 239   - A level-hold is now modeled as memorizing by Yagle generated models
 240
 241 # 2 - Bug fixes
 242   - Fixed possible fatal error in hierarchical Yagle when building final
 243     model after multiples runs building manual behavioral models for
 244     recognised blocks.
 245   - Fixed possible latch recognition failure.
 246
 247 ###############################################################################
 248 # AvtTools version 3.3p13 Release Notes
 249 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 250 # Sep 30th, 2008
 251 #
 252 ###############################################################################
 253
 254 # 1 - New functionalities
 255   - Default configuration settings displayed in avtman.
 256   - New TCL command "cpe_DefineCorrelation" to specify external constraints
 257     required for correct stimulus generation in extracted spicedecks.
 258   - Proper spicedeck generation for buffer structures made from multiple
 259     logic paths.
 260   - New option "yagDetectDelayedRS" to activate automatic detection and
 261     handling of RS type non-overlapping clock generators.
 262   - Verilog netlist driver can now output transistors.
 263   - New option "yagHierarchyGroupTransistors" for yagle hierarchical mode
 264     when handling a netlist for which all instances have generated models
 265     but there are some transistors. Setting this option to "yes" results
 266     in the transistors being grouped in a separate module which is then
 267     abstracted.
 268   - Modified false path marking algorithm which can sometimes improve
 269     performance for large numbers of false path settings.
 270
 271 # 2 - Bug fixes
 272   - Fixed technology file issue for new tempmod=2 setting available since
 273     BSIM 4.5.
 274   - Fixed issue in netlist flattening which could sometimes cause power
 275     supply markings to be lost.
 276   - Fixed issue which could sometimes result in incorrent detection of
 277     static conflicts in latch feedback loops.
 278   - Fixed path search bug due to latch nodes directly in the interface
 279     or directly driving latch commands.
 280   - Fixed issue in generation of bussed output expressions in behavioural
 281     verilog driver.
 282
 283 # 3 - Configuration changes
 284   - Removal of "yagVectorize" and associated options so that vector
 285     policy for abstraction is determined by "avtVectorize". But added
 286     option "yagReorderInterfaceVectors" to reorder interface pins for
 287     behavioural models if desired.
 288   - Replacement of "avtVerilogNamePolicy" by "avtVerilogKeepNames" which
 289     keeps names which are not legal Verilog by using the backslash
 290     convention. By default the names are modified.
 291
 292 ###############################################################################
 293 # AvtTools version 3.3p12 Release Notes
 294 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 295 # Sep 9th, 2008
 296 #
 297 ###############################################################################
 298
 299 # 1 - New functionalities
 300   - Falsepath handling speed up
 301   - Slack object list display speed up
 302   - New option "apiUseCorrespondenceTable" to revert GNS generated hierarchical
 303     names to original circuit names when they are not vectors.
 304   - More value computation error checks in spice parser.
 305   - Handling of correlated skew for paths which are not access paths.
 306
 307 ###############################################################################
 308 # AvtTools version 3.3p11 Release Notes
 309 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 310 # Sep 1st, 2008
 311 #
 312 ###############################################################################
 313
 314 # 1 - New functionalities
 315   - Possibility to specify the transition of the test clock when specifying
 316     false slacks using the "inf_DefineFalseSlack" command.
 317   - New options "tasStrictPathCapacitance" and "tasMaxPathCapacitanceFanout"
 318     to control the handling of out of path capacitances.
 319
 320 # 2 - Bug fixes
 321   - Possible case sensitive issue in FCL markings.
 322   - Error in handling of some cases of transmission gate latches directly
 323     on interface.
 324
 325 ###############################################################################
 326 # AvtTools version 3.3p10 Release Notes
 327 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 328 # Aug 29th, 2008
 329 #
 330 ###############################################################################
 331
 332 # 1 - New functionalities
 333   - Possibility to disable use of threads in tmabs by setting "simAllowThreads"
 334     to "no".
 335   - Select alternative means of calling external simulator by setting
 336     "simUseSystemCommand" to "yes".
 337
 338 ###############################################################################
 339 # AvtTools version 3.3p9 Release Notes
 340 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 341 # Aug 22nd, 2008
 342 #
 343 ###############################################################################
 344
 345 # 1 - Bug fixes
 346   - Fixed possible internal error due to inconsistent dependancy graph
 347
 348 ###############################################################################
 349 # AvtTools version 3.3p8 Release Notes
 350 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 351 # Aug 21st, 2008
 352 #
 353 ###############################################################################
 354
 355 # 1 - New functionalities
 356   - Configuration option "simTransistorAsInstance" can be set to "smart" to handle
 357     mix of transistor instances and transistors.
 358   - units supports for simulation API
 359
 360 ###############################################################################
 361 # AvtTools version 3.3p7 Release Notes
 362 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 363 # Jul 30th, 2008
 364 #
 365 ###############################################################################
 366
 367 # 1 - Bug fixes
 368   - Fixed wrong hold value computation when using false access path information.
 369
 370 ###############################################################################
 371 # AvtTools version 3.3p6 Release Notes
 372 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 373 # Jul 30th, 2008
 374 #
 375 ###############################################################################
 376
 377 # 1 - New functionalities
 378   - avt_shell is now based on Tcl 8.5.3
 379   - Improved false path check when using STB if the false paths are defined
 380     by 3 nodes: {clock latch outputnode}.
 381   - "set_multi_cycle_path" defined with an origin (-from) now impacts the LAGs
 382     in the circuit statility.
 383
 384 # 2 - Bug fixes
 385   - Fixed filter-directive errors in slack details.
 386   - Fixed wrong DATA REQUIRED value with check-directive.
 387
 388 ###############################################################################
 389 # AvtTools version 3.3p5 Release Notes
 390 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 391 # Jul 30th, 2008
 392 #
 393 ###############################################################################
 394
 395 # 1 - New functionalities
 396   - New configuration option "stbSuppressLag" to disable data lag calculation
 397     for latches, precharges or both.
 398   - Automatic handling of RS structure of greater than two inputs.
 399   - Configuration option "yagDetectClockGating" has been enhanced to allow
 400     detection of just timing checks or just filters.
 401   - Removal of clock relative columns in slack report summary.
 402   - Display of data lag in slack report summary.
 403   - Display of total and group counts in in slack wrap-up reports.
 404   - In spice extracted netlists any *|NET directive now influences names
 405     for floating nodes.
 406   - Generated clocks are now supported in .lib files.
 407
 408 # 2 - Bug fixes
 409   - False slack through transparent precharge directly to clock ignoring lag.
 410
 411 ###############################################################################
 412 # AvtTools version 3.3p4 Release Notes
 413 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 414 # Jul 21st, 2008
 415 #
 416 ###############################################################################
 417
 418 # 1 - Bug fixes
 419   - Fixed fatal error in level-hold detection on node connected to a GNS
 420     recognised instance.
 421
 422 ###############################################################################
 423 # AvtTools version 3.3p2 Release Notes
 424 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 425 # Jul 17th, 2008
 426 #
 427 ###############################################################################
 428
 429 # 1 - Bug fixes
 430   - GNS recognition correctly uses power supplies in circuit to set Vcards in
 431     extracted spicedeck for simulation.
 432   - Correct default verilog file suffix for structural driver.
 433
 434 ###############################################################################
 435 # AvtTools version 3.3p1 Release Notes
 436 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 437 # Jul 16th, 2008
 438 #
 439 ###############################################################################
 440
 441 # 1 - New functionalities
 442   - Possibility to refer to an external signal name in a BEG behaviour
 443     generation rule for GNS.
 444   - Option "yagStuckAnalysis" to disable detailed analysis of stuck nets.
 445   - Improved logging of set_case_analysis constraining.
 446
 447 # 2 - Bug fixes
 448   - Eliminated possible unnecessary fatal error in transistor VTI calculation.
 449
 450 ###############################################################################
 451 # AvtTools version 3.3 Release Notes
 452 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 453 # Jul 10th, 2008
 454 #
 455 ###############################################################################
 456
 457 # 1 - New functionalities
 458   - "Hitas SSTA" based on MonteCarlo analysis (ssta slack report, ssta path report).
 459   - New TCL actions for GNS.
 460   - Internal pins and "max_capacitance" are now supported in "tmabs" and .lib files.
 461   - Environnement variable supported in .include and .lib spice files.
 462   - New configuration variable "avtSpiReplaceVoltageInExpressions" to support
 463     voltage between 2 nodes in expression in technology files.
 464   - "clock uncertainty" and "is_hz" added for slack properties.
 465
 466 # 2 - Bug fixes
 467   - Support of ".connect" at top level netlist is now fixed.
 468   - Default comment '!' when using simToolModel ELDO.
 469   - Standalone parasitics added in false path detection.
 470   - Standalone parasitics are now supported in CPE.
 471   - ACM bug for some hspice BSIM3 models.
 472   - Detection of RS bistable directly on output pins.
 473   - Undriven cones correctly modeled in behaviour.
 474
 475
 476 ###############################################################################
 477 # AvtTools version 3.2p13 Release Notes
 478 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 479 # Jun 20th, 2008
 480 #
 481 ###############################################################################
 482
 483 # 1 - New functionalities
 484   - False access path settings fully taken into account during slack analysis.
 485   - New TCL command "stb_DisplayCoverage" which dumps a report with statistics
 486     of how many timing nodes have been checked and details of those which have
 487     not been checked.
 488   - Support of SDC command "set_clock_uncertainty".
 489   - Support of SDC commands "set_max_delay" and ""set_min_delay" as additional
 490     timing checks.
 491   - Support of CDL syntax .PININFO to orient subckt pins.
 492   - Support for orientation of signals mapped to pins of cells recognised
 493     using GNS.
 494   - Reporting of probable badly identified gates in .REP file.
 495   - Option to attempt to guess any necessary MUTEX settings, activated by
 496     "yagMutexHelp" configuration variable.
 497
 498 # 2 - Bug fixes
 499   - Selective handling of parasitics on current paths.
 500   - Issue in parasitic delay recalculation on signals without drivers.
 501
 502
 503 ###############################################################################
 504 # AvtTools version 3.2p12 Release Notes
 505 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 506 # Jun 13th, 2008
 507 #
 508 ###############################################################################
 509
 510 # 1 - New functionalities
 511   - Generation of avt_env.sh during the installation.
 512
 513 # 2 - Bug fixes
 514   - Fixed an error if "bus_naming_style" is missing in .lib files.
 515   - Fixed an error if "pulling_resistance_unit" is missing in .lib files.
 516
 517 ###############################################################################
 518 # AvtTools version 3.2p11 Release Notes
 519 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 520 # Jun 4th, 2008
 521 #
 522 ###############################################################################
 523
 524 # 1 - New functionalities
 525   - Recognition of Level-Hold structures containing resistive transistors.
 526   - Experimental faster transistor characterisation to accelerate
 527     statistical analysis.
 528
 529 # 2 - Bug fixes
 530   - Fixed a fatal error handling transistor M factors in certain cases.
 531
 532 ###############################################################################
 533 # AvtTools version 3.2p10 Release Notes
 534 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 535 # May 21st, 2008
 536 #
 537 ###############################################################################
 538
 539 # 1 - New functionalities
 540   - Possibilty to use an external dynamically linked library for transistor
 541     characterisation.
 542
 543 ###############################################################################
 544 # AvtTools version 3.2p9 Release Notes
 545 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 546 # May 16th, 2008
 547 #
 548 ###############################################################################
 549
 550 # 1 - Bug fixes
 551   - Fixed an issue of slow database generation in some schematic netlists.
 552   - Fixed an issue where clock was incorrectly identified in precharges
 553     when data inputs were filtered by other clocks.
 554
 555 ###############################################################################
 556 # AvtTools version 3.2p8 Release Notes
 557 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 558 # May 15th, 2008
 559 #
 560 ###############################################################################
 561
 562 # 1 - New functionalities
 563   - More precise delay calculation for pass-transistors when gate is voltage
 564     boosted.
 565
 566 # 2 - Bug fixes
 567   - Fixed a spicedeck generation issue of blocked transistors being
 568     incorrectly polarised.
 569
 570 ###############################################################################
 571 # AvtTools version 3.2p7 Release Notes
 572 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 573 # May 2nd, 2008
 574 #
 575 ###############################################################################
 576
 577 # 1 - New functionalities
 578   - Technology and netlist encryption using new TCL command "avt_EncryptSpice",
 579     encrypted files are decrypted automatically.
 580   - Support for SDC command "set_clock_uncertainty".
 581
 582 # 2 - Bug fixes
 583   - Fixed a stability issue when latches were missing clock definition.
 584   - Wildcards now work for specifying clock pins.
 585
 586 ###############################################################################
 587 # AvtTools version 3.2p6 Release Notes
 588 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 589 # Apr 21st, 2008
 590 #
 591 ###############################################################################
 592
 593 # 1 - Bug fixes
 594   - Fixed a syntax ambiguity in the spice parser between models bounded by
 595     brackets and functions which are space separated from their arguments.
 596
 597 ###############################################################################
 598 # AvtTools version 3.2p5 Release Notes
 599 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 600 # Apr 17th, 2008
 601 #
 602 ###############################################################################
 603
 604 # 1 - New functionalities
 605   - Enhancement in "tmabs" for handling blackbox constraints at the interface.
 606   - Spice units enhancement.
 607   - Disabling of transistor diode detection.
 608
 609 # 2 - Bug fixes
 610   - Fixed a special case in BSIM4 parameter handling.
 611   - TCL_LIBRARY setting when using SDC commands.
 612   - Fixed an issue of handling capacitances through transfer gates.
 613   - Better handling of BYPASS in "tma_abstract".
 614   - Better handling of LIB parser functionnality.
 615
 616 ###############################################################################
 617 # AvtTools version 3.2p4 Release Notes
 618 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 619 # Mar 31st, 2008
 620 #
 621 ###############################################################################
 622
 623 # 1 - New functionalities
 624   - avt_shell is now based on Tcl 8.5.1
 625   - New setting "avtSpiUseUnits" which allows the use of units in driven spicedeck.
 626   - Some API's are now with variable arguments: "stb_GetSlacks", "ttv_ProbeDelay",
 627     "ttv_GetPaths" and "ttv_DisplaySlackReport".
 628   - New API "hitas_pvt_count" which returns the number of PVT errors encountered in
 629     the last Hitas run.
 630   - New API "stb_ComputeSlacks" computing slacks directly from list of paths.
 631   - Better handling of breakpoints in STA.
 632   - Non-driven cones are set as breakpoints and paths from them are created.
 633   - Enhancement of latch and memsym detection/configuration.
 634
 635 # 2 - Bug fixes
 636   - Corrected an issue when diodes and transistors have same model name.
 637   - Fixed clock edge synchronization for multiple clock domains in STA.
 638   - Fixed an issue in computing intrinsic setup/hold values.
 639   - Enhancement of blocked transitors driven in spicedeck.
 640
 641 # 3 - Configuration changes
 642   - Added setting "include" in "avtSpiParseFirstLine".
 643   - The setting of "avtErrorPolicy" is "strict" by default.
 644   - The setting of "tasGenerateConeFile" is defaulted to "yes".
 645
 646 ###############################################################################
 647 # AvtTools version 3.2p3 Release Notes
 648 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 649 # Mar 18th, 2008
 650 #
 651 ###############################################################################
 652
 653 # 1 - Bug fixes
 654   - Fixed an issue in configuration of environment variables.
 655
 656 ###############################################################################
 657 # AvtTools version 3.2p2 Release Notes
 658 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 659 # Mar 7th, 2008
 660 #
 661 ###############################################################################
 662
 663 # 1 - New functionalities
 664   - New tutorial.
 665
 666 # 2 - Bug fixes
 667   - TMA correctly handles output load dependence when parasitics are present.
 668
 669 ###############################################################################
 670 # AvtTools version 3.2p1 Release Notes
 671 # Copyright (c) 1998-2008, AVERTEC All Rights Reserved
 672 # Feb 20th, 2008
 673 #
 674 ###############################################################################
 675
 676 # 1 - New functionalities
 677   - slew_derate_from_library in LIB can be tuned with the variable "tmaLibSlewDerate".
 678   - CPE is now compatible with Mspice.
 679   - .lib inside .subckt is now supported in spice.
 680   - Enhancement of error messages for computed expressions.
 681
 682 # 2 - Bug fixes
 683   - False slacks computed in STB.
 684
 685 ###############################################################################
 686 # AvtTools version 3.2 Release Notes
 687 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
 688 # Dec 3rd, 2007
 689 #
 690 ###############################################################################
 691
 692 # 1 - New functionalities
 693   - On-line help in avt_shell, type "help help" in avt_shell for details.
 694   - New API "tmabs", replacement for "tma_abstract" API. This new function
 695     provides the following advantages:
 696     + identical configuration for characterization using the HiTAS timing
 697       engine or characterization using an external Spice simulator.
 698     + A common base with the standard path report functions such as
 699       ConnectorToLatchMargin and Access Paths which guarantees results
 700       consistency and allows easy user configuration and results check.
 701     + Support for partial characterization, i.e. the user can specify which
 702       pins to characterize.
 703     + Clock-gating checks are reported in the LIB.
 704     + Setup/Hold constraints relative to generated clocks are handled.
 705   - New TCL Constraint Objects. Compound object, representing a setup/hold
 706     timing constraint, made up of the relevant data and clock path components
 707     together with intrinsic setup/hold. This object is used internally by
 708     the new "tmabs" and by "ConnectorToLatchMargin". The object also handles
 709     generated clocks correctly.
 710   - New properties for timing path object:
 711      "TYPE", "IS_HZ", "PATH_MARGIN_FACTOR", "PATH_MARGIN_DELTA"
 712   - New property "IS_ASYNCHRONOUS" for timing signal object.
 713   - CPE is now capable of calculating simulation patterns for RS loops
 714     and symmetric memory cells.
 715   - CPE is now capable of generating simulation measures for HZ paths.
 716   - Slack reports for user-defined timing checks show details of all slacks
 717     separated by THRU latch and command and not just the worst case.
 718     This is the same behaviour as for a normal timing check.
 719   - Better handling of "counter" style clocking schemes since nodes with
 720     a generated clock directive are now verified and can be sources of data.
 721   - M-factor now handled by Spice parser for Instances, Resistors and
 722     Capacitors as well as Transistors.
 723   - The automatic false path detection algorithm can now handle access paths.
 724   - New setting "avtEnableMultipleConnectorsOnNet", which, when set to "yes",
 725     handles multiple pin connections on a single logical net. This can be
 726     useful to avoid disappearance of external pins for a generated LIB file.
 727     However, this option should not be used unless strictly necessary.
 728   - New setting "tmaLibDriveTableIndex", which, when set to "yes" means that
 729     any LIB files are generated with axes specified individually for each
 730     look-up table instead of being only in the template.
 731
 732 # 2 - Bug fixes
 733   - Corrected ordering issue in delay recalculation (e.g. ttv_RecomputeDelays)
 734     which meant some timings were not recalculated.
 735   - Corrected "set_false_path" matching issue in rare cases where the path
 736     contained parasitics.
 737   - Fixed an issue which led to breakpoints being eliminated if there was
 738     no timing path reaching the breakpoint.
 739
 740 # 3 - Configuration changes
 741   - Property "FIGNAME" for object TimingFigure is obsolete, use "NAME"
 742
 743 # 4 - Feature changes
 744   - The effect of a multicycle path directive is now reported in the
 745     DATA REQUIRED component of a slack.
 746
 747 ###############################################################################
 748 # AvtTools version 3.1p6 Release Notes
 749 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
 750 # Sep 3rd, 2007
 751 #
 752 ###############################################################################
 753 # 2 - Bug fixes
 754   - Bug concerning the usage "tasUseFinalCapacitance" introduced in 3.1p5 fixed.
 755
 756 ###############################################################################
 757 # AvtTools version 3.1p5 Release Notes
 758 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
 759 # Aug 24th, 2007
 760 #
 761 ###############################################################################
 762
 763 # 1 - New functionalities
 764   - Standard header information automatically added at start of all reports.
 765   - User can specify a .avt_shellrc file in home directory which is run
 766     automatically at the start of an avt_shell script.
 767   - New setting "tasPathCapacitanceDepth" which, is set to a non-zero values
 768     controls across how many transistor the out of path capacitance should
 769     be counted.
 770   - Spicedeck generation can now handle certain types of timing loop.
 771   - New setting "cpePrechargedMemsym" which tells HiTAS that symmetric memory
 772     nodes should be considered to have been precharged for the generation of
 773     Spicedeck stimuli for memory read.
 774   - File compression can now be selectively disabled using the setting
 775     "avtDisableCompression" which is a space separated list of filenames.
 776   - Spicedeck generation can now identify the conditions for writing to
 777     a symmetric memory.
 778
 779 # 2 - Bug fixes
 780   - Fixed discrepancy with Spice where HiTAS used GEOMOD to calculate diffusion
 781     size when these parameters are set to zero in a netlist.
 782   - Fixed discrepancy with Spice where HiTAS could use a model inside a subckt
 783     to characterize a transistor even if the transistor was not described as an
 784     instance.
 785   - Device names containing only Spice device card are now accepted by HiTAS.
 786   - Fixed potential fatal error during crosstalk analysis of circuits without
 787     any clock.
 788   - Fixed potential undefined behaviour when calculating the slope for a very
 789     large resistance.
 790
 791 ###############################################################################
 792 # AvtTools version 3.1p4 Release Notes
 793 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
 794 # Aug 2nd, 2007
 795 #
 796 ###############################################################################
 797
 798 # 1 - New functionalities
 799   - New TCL function "inf_DefineStrictSetup" to specify a strict verification
 800     mode for a given latch. Setup is check with respect to the opening clock
 801     edge and hold with respect to the closing edge.
 802   - New TCL function "sim_ReadMeasure" which allows extraction of a delay
 803     or slope measurement from the results file of a spice simulation.
 804   - The setting "yagSetResetDetection" has a new option "remove" which will
 805     disable all set/reset inputs for all latches except RS bistables.
 806   - New TCL function inf_DefineMemsym which sets a pair of signals to be a
 807     symmetric memory so long as there is a loop between the two signals.
 808   - Enhanced modeling of overshoot discharge in conflictual current paths.
 809   - Enhanced modeling of gate delay and slope when driving huge RC networks.
 810
 811 # 2 - Bug fixes
 812   - Fixed fatal error in CPE when extracting Spicedeck of unusual symmetric
 813     memory configurations.
 814   - V cards on internal connectors of a hierarchical netlist now handled
 815     in HiTAS hierarchical mode.
 816   - intelligent handling of XOR structures at a circuit interface.
 817
 818 # 3 - Configuration Changes
 819   - New configuration variable "yagMemsymHeuristic", defaults to no. When set
 820     to yes, always eliminates current paths connecting two symmetric memories,
 821     which was previous behavior.
 822   - The setting "yagMemsymLatch" has been removed, behavior is as if this was
 823     set to yes.
 824   - The TCL function "ttv_SimulatePathDetail" is deprecated and is replaced by
 825     the new function "ttv_SimulatePath" which takes a timing path.
 826   - New configuration variable "yagStuckLatch". When set to "yes" (the default)
 827     latches are considered to be stuck if all data inputs are stuck even if
 828     the clock inputs are not stuck.
 829
 830 ###############################################################################
 831 # AvtTools version 3.1p3 Release Notes
 832 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
 833 # Jul 25th, 2007
 834 #
 835 ###############################################################################
 836
 837 # 1 - New functionalities
 838   - New TCL function "inf_DefineTransparent" which allows user to specify that a
 839     latch can be transparent so that paths crossing the latch are reported.
 840   - The "set_false_path" command can now be used for access paths.
 841   - Slack report for clock gating checks now display all data origins instead
 842     of just the worst.
 843   - Optional precision warning message, activated by "stmPrecisionWarning",
 844     during delay calculation when an input slope is more than a given multiple
 845     of the gate delay. Multiple given by "stmPrecisionThreshold" (default 10).
 846   - The "ttv_ProbeDelay" function now supports use of wildcards
 847   - Possibility to generate a mini crosstalk report after each iteration in
 848     crosstalk analysis. Enabled by setting "stbCtkMaxReportedSignals" greater
 849     than zero, this value sets the number of slacks/delays/scores to report.
 850   - New TCL function "inf_DefineSwitchingProbability" to define a switching
 851     probability for a signal used during crosstalk analysis to filter
 852     improbable aggression.
 853   - Possibility to use explicit time/capacitance units in TCL functions.
 854
 855 # 2 - Bug fixes
 856   - Clock latency is now displayed in slack report when user specified by
 857     "set_clock_latency".
 858   - INF or SDC directives affecting database generation can now use any of
 859     the possible names when referring to a node in a hierarchical netlist.
 860   - Filter directives could sometimes eliminate valid paths.
 861   - CPE can now correctly handle looped structures such as RS and clock
 862     generators.
 863   - CPE can now handle a write to a symmetric memory.
 864   - The setting "avtParasiticCacheSize = 0" now works from a TCL script.
 865   - The observable mode of crosstalk analysis now filters correctly.
 866   - Fixed bug preventing timing checks for directives between two data
 867     signals.
 868   - Configuration "avtSpiTp/TnModelName" now works from a TCL script.
 869
 870 # 3 - Configuration Changes
 871   - Crosstalk analysis is set to observable mode by default.
 872
 873
 874 ###############################################################################
 875 # AvtTools version 3.1p2 Release Notes
 876 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
 877 # Jun 21st, 2007
 878 #
 879 ###############################################################################
 880
 881 # 1 - New functionalities
 882   - Clock gating checks are performed between the inputs of the gate at which
 883     the convergence occurs.
 884   - Any of the possible hierarchical names can be set for "set_case_analysis"
 885     constraints in a hierarchical netlist.
 886   - Display both HZ and non-HZ slacks for a precharge node instead of just the
 887     worst.
 888   - Possibility to specify HZ transition in path or slack report request by
 889     suffixing the character 'Z' or '/' to the direction specification.
 890   - Path search can now take into account that latches or precharges of
 891     identical phase are transparent.
 892   - New option to allow propagation of a slack error on a precharge to the
 893     latch at the end of a domino precharge chain in order to obtain slack
 894     error margin at this latch. Set "avtTransparentPrecharge" to "unfiltered".
 895   - Possibility to specify the "through latch" in a slack report request.
 896   - Marking a latch using FCL no longer automatically blocks current paths
 897     through the latch unless the "BLOCKER" directive is added.
 898
 899 # 2 - Bug fixes
 900   - Possibility of wrong evaluation of expressions in the flattening process.
 901   - Critical path search through precharge nodes ("avtTransparentPrecharge")
 902     could return incorrect path.
 903   - Missing "through" node in slack corresponding to unclocked precharge
 904     evaluation.
 905
 906 ###############################################################################
 907 # AvtTools version 3.1p1 Release Notes
 908 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
 909 # Jun 11th, 2007
 910 #
 911 ###############################################################################
 912
 913 # 1 - New functionalities
 914   - inf_DefinePathDelayMargin now affects .lib values.
 915   - New option "pathcomp" for ttv_ConnectorToLatchReport.
 916   - Handling of '\' and '\\' in spice parser.
 917
 918 # 2 - Bug fixes
 919   - Better handling of stuck inputs in CPE.
 920   - ttv_ProbeDelay now can take net names.
 921   - Handling of mixed BSIM levels.
 922   - Wrong equivalent capacitance value computed when loading timing database in CPE.
 923
 924 ###############################################################################
 925 # AvtTools version 3.1 Release Notes
 926 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
 927 # May 30th, 2007
 928 #
 929 ###############################################################################
 930
 931 # 1 - New functionalities
 932   - Handling of .FUNC in spice parser.
 933   - New functions added in spice parser:
 934       sgn(a)
 935       sign(a,b)
 936       pow(a,b)
 937       pwr(a,b)
 938       e(a,b)
 939       limit(a,b)
 940       agauss(a,b,c)
 941       symdistr(a,b,c)
 942       asymdistr(a,b,c,d)
 943       skewcor(a,b,c,d)
 944       distr(a,b,c,d)
 945   - Clock detection in 'tma_Abstract' when behavioral figure exists.
 946   - Explicit mention of added/removed cycles in slack report in case of multicycle path.
 947   - Better handling of syntax/errors in SPEF parser.
 948   - Precharge transparancy. Activated by setting "avtTransparentPrecharge" to "yes".
 949   - Asynchronous commands detection by setting "yagSetResetDetection" to "yes".
 950
 951 # 2 - Bug fixes
 952   - Binary avt_shell in 32 bits can now generate reports > 2GB.
 953   - 'ttv_DisplayPathDetail' crashed when NULL path given.
 954   - Incoherent results when annotation coupling capacitances in DSPF.
 955   - Missing slacks between stb and .sto parse.
 956   - Slack report crashed when CKLATCH section in INF file existed.
 957   - Handling name issue in avttools.conf
 958   - Unsupported operator '!=' in spice equations.
 959   - Bad implementation of mobility parameters in BSIM4.5
 960   - .include order issue in spice parser.
 961   - Disable gate delay not working with "avtVectorize" set to "yes".
 962   - Bad implementation of Vsat calculation when 'tempmod' parameter was set to '1'.
 963
 964 # 3 - Configuration changes
 965   - The setting "tmaDetectClock" is no longer supported.
 966
 967 # 4 - Distribution changes
 968   - RedHat Enterprise Linux 4.0 supported, using binaries for 3.0.
 969   - Solaris 10 supported, using binaries for Solaris 9.
 970
 971 ###############################################################################
 972 # AvtTools version 3.0p5 Release Notes
 973 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
 974 # March 14th, 2007
 975 #
 976 ###############################################################################
 977
 978 # 1 - New functionalities
 979   - New standard TCL API to load complete crosstalk results database.
 980   - The SPEF parser no longer causes abort in cases of missing devices.
 981   - SPEF parser now accepts all legal SPEF syntax.
 982
 983 # 2 - Bug fixes
 984   - Scaling error when counting RC delay internal to a cone such as before
 985     a transfer gate.
 986   - Incomplete criteria for choosing to calculate RC delays internal to cones.
 987   - 32bit avt_shell could not create user report files larger than 2GB.
 988   - Fixed fatal error in TCL function "ttv_DisplayPathDetail" when given a
 989     NULL path.
 990   - Fixed issue of missing coupling capacitance from DSPF depending on net
 991     declaration order.
 992   - Fixed incorrect DSPF parasitic connections in case of missing *|S.
 993   - Fixed issue of potential optimism in fall transition for transfer
 994     gate command delay when using avtNewSwitchModel.
 995   - Fixed issue where CKLATCH caused connectors to be clocks for STA.
 996
 997 ###############################################################################
 998 # AvtTools version 3.0p4 Release Notes
 999 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
1000 # February 21st, 2007
1001 #
1002 ###############################################################################
1003
1004 # 1 - New functionalities
1005   - Spice parser support for user-defined functions.
1006   - New standard TCL scripts showing individual gate simulation and custom
1007     slack report generation.
1008   - Precision characterisation mode using propagated slope values, activated
1009     by setting "tmaCharacPrecision" to "yes".
1010   - Annotation of passive devices (resistors, capacitors, diodes) now permitted
1011     by SPEF parser by setting "avtAnnotationPreserveExistingParasitics" to "yes"
1012   - Stability analysis now takes full account of false path and false slack
1013     settings. This allows false DATA LAG reports to be removed. This
1014     functionality is activated by setting "stbStabilityCorrection" to "yes"
1015   - Custom configuration of device connector names for DSPF and SPEF parasitic
1016     annotation to handle outputs of any extractor. See documentation of
1017     "avtAnnotationDeviceConnectorSetting" for details.
1018   - TYPE property of timing path detail now gives precise gate type if known.
1019   - Optmisation of regular expression handling.
1020
1021 # 2 - Bug fixes
1022   - More robust parasitic annotation for DSPF and SPEF formats. Node connections
1023     are fully determinist and corected an issue where a parasitic file could
1024     open circuit a connection existing in the device netlist.
1025   - "inf_DisableTimingArc" will now give a warning if the specified names do
1026     not exist.
1027   - Issue of XTAS process remaining on license checkout failure, unusable but
1028     using CPU.
1029   - CPE issue where initial conditions not set for non-dual CMOS gates.
1030   - CPE issue where results not read due to measure label mismatch in case of
1031     bussed signals
1032   - Total net capacitance in DSPF file is now calculated properly in case of
1033     crosstalk capacitance.
1034   - Corrected issue of total capacitance update if the crosstalk capacitance
1035     is specified by an expression.
1036   - Corrected issue in "avtSpiKeepCards" "capacitance" setting which behaved
1037     the exect opposite to the setting.
1038   - Intrinsic charge calculation bug for BSIM3 CAPMOD=0 technology files.
1039   - Convergence issue calculating branch current, could result in reduced
1040     precision for transfer gates.
1041   - Corrected issue in "LoadSwitchingWindows" where incorrect slack could be
1042     reported due to incomplete connecter stability in ".STO" file.
1043   - Corrected issue in "LoadSwitchingWindows" in case of missing clock
1044     specification for multi-clock latches.
1045   - Corrected issue of missing clock path detail in case of precharge with
1046     no direct clocking of precharge or evaluation phase.
1047   - Corrected issue of nonsensical display of data required in slack report
1048     in case of combinational circuits.
1049   - Missing property for "THRU" latch in slack object.
1050   - Corrected handling issue of new BSIM4.5 transistor instance specific
1051     parameters.
1052   - Correct handling of net name in DSPF interpreted as spice.
1053   - Corrected issue in setting Vcard on pin logically connected to another
1054     external pin.
1055   - Corrected issue of very strange delay results in some cases when using
1056     avtNewSwitchModel
1057   - Corrected issue in which variable avtNewSwitchModel had to be present
1058     for script recalculating delays in order to be taken into account even
1059     though UTD was built using avtNewSwitchModel
1060
1061 # 3 - Distribution changes
1062   - RedHat Linux 8.0 is no longer supported.
1063
1064 ###############################################################################
1065 # AvtTools version 3.0p3 Release Notes
1066 # Copyright (c) 1998-2007, AVERTEC All Rights Reserved
1067 # February 1st, 2007
1068 #
1069 ###############################################################################
1070
1071 # 1 - New functionalities
1072   - Support for crosstalk capacitances in DSPF parser.
1073   - Better effective gate-drain capacitance modeling.
1074   - Improvement in local crosstalk effect.
1075   - BSIM 4.5 partial support (well proximity effects not yet supported).
1076
1077 # 2 - Bug fixes
1078   - In .LIB driver clock related output pins necessarily have an access
1079     timing arc.
1080   - Correct phase and domain handling for user-defined timing directives and
1081     clock gating checks.
1082   - Bug in BSIM VERSION handling in 4.4 technology files
1083   - Delay recalculation issue in symmetric memory cells
1084
1085 ###############################################################################
1086 # AvtTools version 3.0p2 Release Notes
1087 # Copyright (c) 1998-2006, AVERTEC All Rights Reserved
1088 # January 22nd, 2007
1089 #
1090 ###############################################################################
1091
1092 # 1 - New functionalities
1093   - New TCL command inf_DefineFalseSlack to remove false slack errors.
1094   - User defined directives to specify clock filtering of data signals.
1095   - Handling of symmetrical bitcells as 2 latches with setting of
1096     yagMemsymLatch to yes.
1097
1098 # 2 - Bug fixes
1099   - Incorrect intrinsic setup in slack report.
1100   - Fatal error if netlist contains transistors identical apart from SA/SB.
1101   - INF marking of unused transistors.
1102   - Automatic clock gating not applied to stuck nets.
1103   - Voltage initialisation bug in NewSwitchModel.
1104   - Impossible convergence in NewSwitchModel for very low supply voltages.
1105   - set_false_paths now affects paths ending on high impedance state such
1106     as precharge nodes
1107   - More robust regular expression handling
1108
1109 # 3 - Distribution changes
1110   - FlexLM updated to v10.8.5.0 to correct automatic heartbeat issue with
1111     64bit Linux.
1112   - Solaris 2.6 is no longer supported.
1113
1114 ###############################################################################
1115 # AvtTools version 3.0p1 Release Notes
1116 # Copyright (c) 1998-2006, AVERTEC All Rights Reserved
1117 # December 20th, 2006
1118 #
1119 ###############################################################################
1120
1121 # 1 - New functionalities
1122   - Handling of conditional "a ? b : c" and "int" operators in technology file.
1123   - Handling of user parameters in transistor instance.
1124
1125 # 2 - Bug fixes
1126   - Fixed bug when *|NET within .subckt in spice netlist.
1127   - Input slope in spicedeck when the first timing arc is a parasitic
1128     was incorrect.
1129   - Use of unknown property caused a fatal error after warning message.
1130
1131 ###############################################################################
1132 # AvtTools version 3.0 Release Notes
1133 # Copyright (c) 1998-2006, AVERTEC All Rights Reserved
1134 # November 20th, 2006
1135 #
1136 ###############################################################################
1137
1138 # 1 - New functionalities
1139   - Arithmetic on propagated clocks. Using the SDC directive
1140     "create_generated_clock" it is possible to specify clock
1141     multipliers/dividers, duty cycle changes, inversion and
1142     edge_shifting.
1143   - User defined Setup/Hold timing checks between any two
1144     data or clock signals.
1145   - Automatic detection of clock gating check points.
1146   - Timing reports contain more detail on type of gate if it
1147     is a standard CMOS gate.
1148   - New API function "ttv_DumpHeader" to create a standard header
1149     for timing reports.
1150   - Support for auto-loading of TCL functions defined in the
1151     distribution TCL directory.
1152   - Reports of number of warnings/errors at the end of execution
1153     of any script.
1154   - Parasitic annotation on diodes and capacitances.
1155   - Support of spice .connect directive to connect circuit nodes.
1156   - Full error message documentation.
1157   - Full support of virtual clocks in data departure/arrival
1158     specifiations.
1159   - Support for spice voltage sources with one level of hierarchy.
1160   - Improved modeling of gate output overshoot.
1161   - Modeling of local crosstalk effect between input and output
1162     of a gate.
1163   - Improved modeling of effective gate input capacitance.
1164   - Better fitting of transistor characteristics for advanced
1165     technologies.
1166   - Improved modeling of current in series connected transistors
1167     simultaneously switching due to a common input.
1168
1169 # 2 - Bug fixes
1170   - Improved license management stability.
1171   - Incorrect master/slave latch markings in case of toggle or
1172     cascaded flip-flops.
1173   - "set_case_analysis" timing constraints are now propagated
1174     through latches. A latch is considered stuck if the data
1175     is stuck.
1176   - The timing path characterisation function "ttv_CharacPaths"
1177     now generates coherent path detail reports.
1178   - Slew and Load axes for characterisation can now be specified
1179     per timing figure before loading of the figure.
1180   - avt_shell no longer blocks when started in the background.
1181   - Fixed false transistor characterisation warnings for stuck
1182     nodes.
1183   - Handling of comments in SPEF parser.
1184   - Fatal error in case of illegal false path directives.
1185   - Directive "set_false_path" no longer requires "from" and "to"
1186     if "through" is specified.
1187   - Failure of "set_case_analysis" directive when used to specify
1188     a particular transition on a bussed signal.
1189
1190 # 3 - Configuration changes
1191   - The setting "tasGenerateDetailTimingFile" is no longer supported.
1192     The detailed timing file is now always generated, equivalent to
1193     the "yes" setting.
1194   - The setting "tasExitAfterDetailTimingFile" now defaults to "yes".
1195     The timing path file can be optionally generated by setting this
1196     variable to "no"
1197   - The setting "yagAutomaticLatchDetection now defaults to "yes".
1198   - The setting "yagDetectBistable" is no longer supported. Use the
1199     setting "yagAutomaticRSDetection" instead. This variable defaults
1200     to yes but requires "yagAutomaticLatchDetection=yes". By default
1201     RS bistables are recognised but not treated as latches. This
1202     behaviour can be customised using "yagAutomaticRSDetection".
1203   - The settings "tmaTtxInput", "tmaTtxInput", "tmaTtxInput" are
1204     no longer supported. The API tma_Abstract automatically uses
1205     whatever form of the timing figure has been loaded. If both
1206     path and detail are loaded, then the detail is used.
1207   - The settings "avtAnnotationKeepM" and "avtAnnotationKeepX" are
1208     obsolete. They are replaced by the more general setting
1209     "avtAnnotationKeepCards"
1210   - Clocks automatically "Equivalent" if they  are generated from
1211     the same source clock and have the same period.
1212