Initial version of donated sources by Avertec, 3.4p5.
[tas-yagle.git] / distrib / share / gns_templates / column_input.vhd
1 --
2 -- Template column_input
3 -- Recognition rule
4 --
5 entity column_input is
6 port ( datain, wen, ckp : in bit;
7 q, nq : inout bit;
8 vdd,vss : in bit);
9 end;
10
11 architecture precharge_included of column_input is
12 component tn
13 port ( gate : in bit;
14 source : inout bit;
15 drain : inout bit;
16 bulk : in bit);
17 end component;
18
19 component tp
20 port ( gate : in bit;
21 source : inout bit;
22 drain : inout bit;
23 bulk : in bit);
24 end component;
25
26 signal nsig, nsig2, sig, PCsig : bit;
27
28 begin
29 inv_tn : tn port map ( datain ,vss ,nsig ,vss);
30 inv_tp : tp port map ( datain ,vdd ,nsig ,vdd);
31
32 buf_tn1 : tn port map ( datain ,vss ,nsig2 ,vss);
33 buf_tp1 : tp port map ( datain ,vdd ,nsig2 ,vdd);
34 buf_tn2 : tn port map ( nsig2 ,vss ,sig ,vss);
35 buf_tp2 : tp port map ( nsig2 ,vdd ,sig ,vdd);
36
37 precharge_tn1 : tn port map ( ckp ,nq ,vdd ,vss);
38 precharge_tn2 : tn port map ( ckp ,q ,vdd ,vss);
39 precharge_tn3 : tn port map ( ckp ,nq ,q ,vss);
40
41 write_q : tn port map ( wen ,nq ,nsig ,vss);
42 write_nq : tn port map ( wen ,q ,sig ,vss);
43
44 end;