distrib/share/gns_templates/sense_amplifier.vhd

   1 --
   2 -- Template sense_amplifier
   3 -- Recognition rule
   4 --
   5 entity sense_amplifier is
   6     port    ( data, ndata       : in    bit;
   7               cke, ckp          : in    bit;
   8               X                 : out   bit;
   9               vdd, vss          : in    bit);
  10 end;
  11
  12 architecture template of sense_amplifier is
  13     component differential_amplifier
  14         port    ( i_1, i_2      : in    bit;
  15                   g             : in    bit;
  16                   x             : out   bit;
  17                   vdd, vss      : in    bit);
  18     end component;
  19
  20     component TN
  21        port     ( gate          : in    bit;
  22                   source,drain  : inout bit;
  23                   bulk          : in    bit);
  24     end component;
  25
  26     signal g1, g2, g3, x1, x2 : bit;
  27
  28 begin
  29     tn_1 : TN port map (cke ,g1 ,vss ,vss);
  30     DA_1 : differential_amplifier port map ( ndata ,data  ,g1 ,x1 ,vdd ,vss);
  31
  32     tn_2 : TN port map (cke ,g2 ,vss ,vss);
  33     DA_2 : differential_amplifier port map ( data  ,ndata ,g2 ,x2 ,vdd ,vss);
  34
  35     tn_3 : TN port map (cke ,g3 ,vss ,vss);
  36     DA_3 : differential_amplifier port map ( x1, x2, g3, X, vdd, vss);
  37
  38     link : TN port map (ckp ,x2 ,x1  ,vss);
  39
  40 end;
  41
  42 architecture mixt of sense_amplifier is
  43     component differential_amplifier
  44         port    ( i_1, i_2      : in    bit;
  45                   g             : in    bit;
  46                   x             : out   bit;
  47                   vdd, vss      : in    bit);
  48     end component;
  49
  50     component TP
  51         port     ( gate          : in    bit;
  52                    source,drain  : inout bit;
  53                    bulk          : in    bit);
  54     end component;
  55
  56     component TN
  57         port     ( gate          : in    bit;
  58                    source,drain  : inout bit;
  59                    bulk          : in    bit);
  60     end component;
  61
  62     signal g1, g2, g3, x1, x2, sig1, sig2 : bit;
  63
  64 begin
  65     tn_1 : TN port map (cke ,g1 ,vss ,vss);
  66     custom_amp_1_tp1 : TP port map  (sig1   ,sig1   ,vdd    ,vdd);
  67     custom_amp_1_tp2 : TP port map  (sig1   ,x1     ,vdd    ,vdd);
  68     custom_amp_1_tn1 : TN port map  (ndata  ,g1     ,sig1   ,vss);
  69     custom_amp_1_tn2 : TN port map  (data   ,x1     ,g2     ,vss);
  70
  71     tn_2 : TN port map (cke ,g2 ,vss ,vss);
  72     custom_amp_2_tp1 : TP port map  (sig2   ,sig2   ,vdd    ,vdd);
  73     custom_amp_2_tp2 : TP port map  (sig2   ,x2     ,vdd    ,vdd);
  74     custom_amp_2_tn1 : TN port map  (data   ,g1     ,sig2   ,vss);
  75     custom_amp_2_tn2 : TN port map  (ndata  ,x2     ,g2     ,vss);
  76
  77     tn_3 : TN port map (cke ,g3 ,vss ,vss);
  78     DA   : differential_amplifier port map ( x1, x2, g3, X, vdd, vss);
  79
  80     -- pass transistor
  81     PT : TN port map (ckp ,x2 ,x1  ,vss);
  82
  83 end;