distrib/share/man/man1/yagle.1

   1 .TH YAGLE 1 "30 March 2000" "AVERTEC" "AVERTEC CAD Tools"
   2
   3 .SH NAME
   4 yagle \- Disassembly and functional abstraction of CMOS circuits
   5
   6 .so man1/avt_origin.1
   7
   8 .SH SYNOPSIS
   9 .B "yagle "
  10 [
  11 .B \-i
  12 ]
  13 [
  14 .B \-v
  15 ]
  16 [
  17 .B \-p=n
  18 ]
  19 [
  20 .B \-nc
  21 ]
  22 [
  23 .B \-nl
  24 ]
  25 [
  26 .B \-fcl
  27 ]
  28 [
  29 .B \-elp
  30 ]
  31 [
  32 .B \-o
  33 ]
  34 [
  35 .B \-z
  36 ]
  37 [
  38 .B \-s
  39 ]
  40 [
  41 .B \-nb
  42 ]
  43 [
  44 .B \-h
  45 ]
  46 [
  47 .B \-d
  48 ]
  49 [
  50 .B \-t
  51 ]
  52 [
  53 .B \-a
  54 ]
  55 .I input_name
  56 [
  57 .I output_name
  58 ]
  59
  60 .SH DESCRIPTION
  61 .B yagle
  62 is a circuit disassembler and functional abstractor for CMOS digital circuits.
  63 It generates a VHDL data flow description and an oriented gate net-list
  64 from a transistor level description of the circuit. The transistor net-list
  65 can be either flat or hierarchical.
  66 .LP
  67 The VHDL subset generated by
  68 .B yagle
  69 is supported by most simulation and synthesis tools.
  70 .LP
  71 .B yagle
  72 does not use a predefined gate library except for latches and flip-flops.
  73 All styles or circuitry are supported: dual-cmos, precharge, pass-transistor, etc.
  74 In addition a user-defined gate library can be provided in order to handle complex latches
  75 or analog circuitry.
  76 .LP
  77 \fBAll power supplies and grounds signals must be connected to an external connector.\fB
  78 .LP
  79 In the first phase,
  80 .B yagle
  81 extracts the CMOS dual circuitry.
  82 In the second phase,
  83 .B yagle
  84 builds the gate net-list for the remaining circuitry whilst performing functional
  85 analysis in parallel, in order to prevent the fabrication of false branches
  86 within a gate and to verify the behaviour of the gate.
  87 .LP
  88 This functional analysis depends on the '-p=n' option which defines the maximum
  89 depth (in gates) of the analysis.
  90 .LP
  91 .B yagle
  92 reads the transistor net-list given by
  93 .I input_name
  94 and generates a VHDL data flow description in
  95 .I output_name.
  96 If no
  97 .I output_name
  98 is given then
  99 .I input_name
 100 is used.
 101
 102 .SH OPTIONS
 103 .sp 1
 104 Options may be given in any order before or after the filename(s).
 105 .LP
 106 .TP 0.5i
 107 .B \-v
 108 When this option is set, the interface and the internal signal of the behavioural
 109 description are vectorised. Every bit of the vector has to be of the same type
 110 otherwise the functional description will not be generated.
 111 .TP 0.5i
 112 .BI \-p= n
 113 This option sets the maximum depth for the functional analysis.
 114 This is the depth of circuitry (in gates) taken into account when detecting
 115 reconvergences in the circuit. The default value is 5.
 116 When
 117 .I n
 118 = 0, the functional analysis process is disabled.
 119 .TP 0.5i
 120 .B \-nc
 121 Disables the detection of complex gates. Without this option complex gates such
 122 as edge-triggered flip-flops are identified by pattern-matching applied to the
 123 disassembled gate net-list. Special predefined behavioural descriptions are then
 124 generated for these gates. This option is useful if a one to one correspondance
 125 between the elements of the behavioural description and the elements of the
 126 disassembled gate net-list is required.
 127 .TP 0.5i
 128 .B \-nl
 129 Disables the detection of latches and memory points using the built-in latch
 130 library. This option is useful if all memory points are to be detected by
 131 the use of a user-defined library with the
 132 .B \-fcl
 133 option.
 134 .TP 0.5i
 135 .B \-fcl
 136 This option makes
 137 .B yagle
 138 use library-based transistor netlist recognition (see man fcl). This
 139 allows the user to specify a number of netlists to be identified within the
 140 circuit to be disassembled. These netlists are specified in the Spice format and
 141 can contain a number of special directives for the marking of the identified
 142 signals and transistors in the circuit, for example signals corresponding to
 143 memory points or transistors to be ignored.
 144 .br
 145 In addition the user can specify a behavioural description for the transistor
 146 netlist which is used to generate the global
 147 behavioural description of the circuit. This allows the functional abstraction
 148 of circuits containing analog blocks for example RAMs containing sense amplifiers.
 149 .TP 0.5i
 150 .B \-xfcl
 151 Same as \-fcl. In addition, it makes yagle stop after the recognition process.
 152 .TP 0.5i
 153 .B \-elp
 154 With this option set
 155 .B yagle
 156 uses the elp tecnology file (man elp) to update the capacitances in the input
 157 transistor net-list. So that the cns and structural views contain accurate
 158 capacitance values.
 159 .TP 0.5i
 160 .B \-o
 161 .B yagle
 162 orients transistors using a simple rule:
 163 A transistor whose source is connected to the output of a CMOS Duals gate, and
 164 not connected to a transistor gate, is oriented form source to drain. This
 165 orientation is performed during the phase of extraction of CMOS duals.
 166 .TP 0.5i
 167 .B \-z
 168 When this option is set,
 169 .B yagle
 170 exploits high impedance nodes during the phase of
 171 functional analysis. This allows, for example, the resolution of false conflicts
 172 in circuits which use precharge logic.
 173 .TP 0.5i
 174 .B \-s
 175 This option provides only one power supply and ground connector in the interface
 176 of the behavioural description. This can be useful in order to compare the
 177 abstracted description with the initial specification. When this option is set,
 178 the name of power supply and ground
 179 are given by
 180 .B MBK_VDD
 181 and
 182 .B MBK_VSS.
 183 .B \-nb
 184 Disables the generation of the behavioural description of the circuit, useful if
 185 the user is solely interested in the gate-level net-list.
 186 .TP 0.5i
 187 .B \-h
 188 .B yagle generates a structural gate level net-list. The variable MBK_OUT_LO has to be set to
 189 choose the format of the out files: the net-list and the gates. A behavioural
 190 description is generated for each gate.
 191 .TP 0.5i
 192 .B \-d
 193 .B yagle
 194 generates a .cns file which contains the flat gate net-list. This file is mainly
 195 used for debugging.
 196 .TP 0.5i
 197 .B \-i
 198 This option makes
 199 .B yagle
 200 read the .inf file. This file should have the same name
 201 as the input file with extesion .inf. It may contain mutual exclusion
 202 conditions on ports of the circuit. These conditions are only used in the
 203 functional analysis process.
 204 .br
 205 # lines beginning with '#' are comment lines
 206 .br
 207 Syntax for the mutual exclusion conditions
 208 .br
 209         MUTEX
 210 .br
 211             muxUP{a,...,d};
 212 .br
 213             muxDN{m,...,p};
 214 .br
 215             cmpUP{i,...,l};
 216 .br
 217             cmpDN{x,...,z};
 218 .br
 219         END
 220 .br
 221
 222 muxUP expresses that one port at most in the list is "one".
 223 .br
 224 muxDN expresses that one port at most in the list is "zero".
 225 .br
 226 cmpUP expresses that one and only one port in the list is "one".
 227 .br
 228 cmpDN expresses that one and only one port in the list is "zero".
 229
 230 .br
 231 Port name may be preceded by the character '~' which minds that it is the inverse
 232 of the port which has to be taken into account.
 233 .br
 234
 235 The user can also use this file to rename internal signals in the behavioural
 236 description in order to use the formal proof.
 237
 238 .br
 239 Syntax to rename signals for the behavioural description
 240 .br
 241         RENAME
 242 .br
 243             existing_name : new_name  ;
 244 .br
 245             *gno* : *latch_data* ;
 246 .br
 247         END
 248 .br
 249
 250 "new_name" will replace "existing_name" in the behavioural description file.
 251 It is possible to  use the joker '*'. When the names contain the string "gno",
 252 this string is replaced by the string "latch_data" (l2_y_gno_01 is replaced by
 253 l2_y_latch_data_01).
 254
 255 Beware that only one rule can be applied to a name, (the following rules
 256 are then ignored when one has been applied) and that the rules are
 257 taken into account in the order in which they appear in the 'inf' file.
 258 .TP 0.5i
 259 .B \-t
 260 Set the trace mode during execution, used only for debugging purposes.
 261 .br
 262
 263 .TP 0.5i
 264 .B \-a
 265 Activate transistor orientation taking into account the  \fB_s\fP
 266 convention on signal's names.
 267 .br
 268
 269 .SH OUTPUT FILES
 270 .TP 10
 271 .B vbe
 272 The functional description is described in a file called
 273 .I input_name
 274 or
 275 .I output_name, with extension .vbe.
 276 .TP 10
 277 .B cns
 278 The disassembled gate net-list or cone net-list description when the
 279 .B \-d
 280 option is set.
 281 .TP 10
 282 .B vst/hns/al/spi
 283 The structural description when the
 284 .B \-h
 285 option is set.
 286 .TP 10
 287 .B rep
 288 The errors and warnings report file.
 289 .B loop
 290 File containing list of combinatorial loops file, only created if loops exist
 291 and the environment variable
 292 .B YAGLE_LOOP_MODE
 293 is set.
 294
 295 .SH ENVIRONMENT VARIABLES
 296 .TP 7
 297 MBK_IN_LO
 298 indicates the format of the input net-list.
 299 .br
 300
 301         spi     for     Spice net-list.
 302 .br
 303         al      for     Alliance extracted net-list.
 304 .br
 305
 306 .TP 7
 307 .B MBK_OUT_LO
 308 indicates the format of the output net-list when the
 309 .B \-h
 310 option is set. Same values as
 311 .B MBK_IN_LO
 312 .TP 7
 313 .B MBK_WORK_LIB
 314 Indicates where YAGLE has to read the input file and write the resulting files.
 315 .TP 7
 316 .B MBK_CATA_LIB
 317 If the input net-list is hierarchical, the leaf cells may not be in the working
 318 directory MBK_WORK_LIB. In that case, MBK_CATA_LIB indicates where YAGLE can
 319 find the cells.
 320 .TP 7
 321 .B CNS_VDDNAME
 322 Sets the name of power supply. "vdd" is the default. Every external port of the
 323 circuit whose name contain this string will be considered as a power supply.
 324 .TP 7
 325 .B CNS_VSSNAME
 326 Sets the name of the ground. "vss" is the default.  Every external port of the
 327 circuit whose name contain this string will be considered as a ground.
 328 .TP 7
 329 .B CNS_GRIDNAME
 330 Sets the name of the grid connector of a transistor. "grid" is the default.
 331 .TP 7
 332 .B CNS_SOURCENAME
 333 Sets the name of the source connector of a transistor. "source" is the default.
 334 .TP 7
 335 .B CNS_DRAINNAME
 336 Sets the name of the drain connector of a transistor. "drain" is the default.
 337 .TP 7
 338 .B ELP_TECHNO_NAME
 339 Sets the full access path and name of the technology file (.elp) used to correct
 340 the node capacitances in the circuit.
 341 .TP 7
 342 .B VH_BEHSFX
 343 Sets the extension of the file that will contain the VHDL description. "vbe" is
 344 the default value.
 345 .TP 7
 346 .B YAGLE_LANGUAGE
 347 When set to F,
 348 .B yagle
 349 will report errors and warnings in French.
 350 When set to E,
 351 .B yagle
 352 will report errors and warnings in English.
 353 The default is English.
 354 .TP 7
 355 .B YAGLE_STAT_MODE
 356 When set to Y,
 357 .B yagle
 358 generates a file with the extension .stat which contains statistics of the
 359 transistor net-list.
 360 .TP 7
 361 .B YAGLE_MAX_LINKS
 362 Sets the the maximum possible length of a branch within a gate. The default is
 363 six.
 364 .TP 7
 365 .B YAGLE_LOOP_MODE
 366 When set to Y,
 367 .B yagle
 368 looks for combinatorial loops in the disassembled circuit, if any are found,
 369 they
 370 are reported in a file with extension
 371 .B \.loop.
 372 Note that any two gate loops are systematically reported in the
 373 .B \.rep
 374 file.
 375 .TP 7
 376 .B YAGLE_BDDCEILING
 377 Sets the the maximum number of BDD nodes. The default is 10000, 0 means no ceiling.
 378 .TP 7
 379 .B YAGLE_BLOCK_BIDIR
 380 When set to 'yes', this variable inhibits the construction of branches through a transistor already used
 381 in the opposite orientation.
 382 .TP 7
 383 .B YAGLE_GEN_SIGNATURE
 384 When set to 'no', yagle does not generate signatures for the cones, therefore .slib icones are not
 385 used.
 386 .TP 7
 387 .B FCL_LIB_PATH
 388 Indicates the access path to the directory containing the user-defined cell
 389 library used if the
 390 .B \-fcl
 391 option is set. The default is a subdirectory
 392 .B /cells
 393 in
 394 .B MBK_WORK_LIB
 395 .TP 7
 396 .B FCL_LIB_NAME
 397 The name of the file (located in
 398 .B FCL_LIB_PATH
 399 ) containing the list of cells in the user-defined cell library used if the
 400 .B \-fcl
 401 option is set. The default is
 402 .B LIBRARY.
 403 .SH DIAGNOSTICS
 404 Reported in the
 405 .B rep
 406 file.
 407 .br
 408 "[WAR] Possible unconnected supply ?"
 409 .br
 410 means that an internal signal whose name contains
 411 .B CNS_VDDNAME
 412 or
 413 .B CNS_VSSNAME
 414 has been found. Verify if this signal should be connected to an external supply.
 415 .br
 416 "[WAR] Transistor used as a resistance"
 417 .br
 418 Indicates that a transistor P (resp. N) with gate connected to the ground
 419 (resp. power supply) has been found in the circuit.
 420 .br
 421 "[WAR] Transistor used as a diode"
 422 .br
 423 Indicates that a transistor with drain (or source) connected to gate has been
 424 found in the circuit, and the signal connecting them is neither power supply nor
 425 ground.
 426 .br
 427 "[WAR] Transistor is always off"
 428 .br
 429 Indicates that a transistor P (resp. N) with gate connected to power supply
 430 (resp. ground) has been found in the circuit.
 431 .br
 432 "[WAR] Transistor used as a capacitance"
 433 .br
 434 Indicates that a transistor with drain and source connected together has been
 435 found in the circuit.
 436 .br
 437 "[WAR] Gate of transistor is not connected"
 438 .br
 439 Indicates that a transistor gate which is connected to nothing has been found
 440 in the circuit.
 441 .br
 442 "[WAR] Drain of transistor is not connected"
 443 .br
 444 Indicates that a transistor drain which is connected to nothing has been found
 445 in the circuit.
 446 .br
 447 "[WAR] Source of transistor is not connected"
 448 .br
 449 Indicates that a transistor source which is connected to nothing has been found
 450 in the circuit.
 451 .br
 452 "[WAR] Transistors are not used in the circuit"
 453 .br
 454 This means that these transistor are not used to pull up or pull down any
 455 transistor gate in the circuit, or any external port. This occurs if the output
 456 of an inverter does not drive anything: In this case
 457 .B yagle
 458 considers both
 459 transistors of the inverter to be unused.
 460 .br
 461 "[WAR] Loop between 2 gates (bleeder found)"
 462 .br
 463 This means that a loop corresponding to a bleeder has been found in the circuit.
 464 .br
 465 "[WAR] Loop between 2 gates (latch found)"
 466 .br
 467 This means that a loop corresponding to a latch has been found in the circuit.
 468 .br
 469 "[WAR] Loop between 2 gates (bistable found)"
 470 .br
 471 This means that a loop corresponding to a bistable has been found in the circuit.
 472 .br
 473 "[WAR] Loop between 2 gates (nothing found)"
 474 .br
 475 This means that a two gate loop which does not correspond to a latch, bleeder
 476 or bistable has been found in the circuit.
 477 .br
 478 "[WAR] Conflict may occur on signal"
 479 .br
 480 This means that the signal may be pulled-up and pulled-down simultaneously. This
 481 is a warning since this message  may disappear with a greater depth for the
 482 functional analysis process.
 483 .br
 484 "[WAR] HZ state may occur on signal"
 485 .br
 486 This means that the signal is not pulled up or pulled down for every input
 487 pattern on the cone entries.  This is a warning since this message may disappear
 488 with a greater depth for the functional analysis process.
 489 .br
 490 "[WAR] Signal does not drive anything"
 491 .br
 492 This means that the the signal is not used as the input to any gate or used
 493 to drive any external connector.
 494 .br
 495 "[WAR] Connector unused"
 496 .br
 497 This means that the external connector is neither the input nor the output of
 498 any of the extracted transistor gates.
 499 .br
 500 "[ERR] Bad direction on connector"
 501 .br
 502 Indicates that the orientation of an external connector after disassembly does not correspond
 503 to that specified in the input net-list.
 504 .br
 505 "[ERR] Transistor gate signal is not driven"
 506 .br
 507 Indicates that a transistor gate can not be pulled up or down.
 508 .SH FATAL ERRORS
 509 "[FATAL ERR] No VDD/VSS connector in the circuit"
 510 .br
 511 This means that
 512 .B yagle
 513 did not find any external ports whose name is the name of the power supply in the
 514 circuit. Have CNS_VDDNAME and CNS_VSSNAME the right value?
 515 .br
 516 "[FATAL ERR] Connector is power supply and ground"
 517 .br
 518 This means that
 519 .B yagle
 520 found a connector whose name includes
 521 .B CNS_VDDNAME
 522 and
 523 .B CNS_VSSNAME.
 524 "[FATAL ERR] No VDD/VSS signal in the circuit"
 525 .br
 526 This means that
 527 .B yagle
 528 did not find any signal whose name is the name of the power supply in the
 529 circuit.
 530 .br
 531 "[FATAL ERR] Several external connectors on signal"
 532 .br
 533 This means that
 534 .B yagle
 535 found several external connectors connected to the same equipotential, a configuration
 536 which it considers illegal.
 537 .br
 538
 539 .so man1/avt_bug_rprt.1
 540
 541 .SH SEE ALSO
 542 .BR inf (5),
 543 .BR fcl (5),