Initial version of donated sources by Avertec, 3.4p5.
[tas-yagle.git] / distrib / share / tcl / help / avt / report / ttv_DisplayConnectorToLatchMargin
1
2 void ttv_DisplayConnectorToLatchMargin(FILE *f, TimingFigure *tf, char
3 *inputconnector, char *mode);
4
5 D\bDE\bES\bSC\bCR\bRI\bIP\bPT\bTI\bIO\bON\bN
6 Prints a report displaying setup and hold constraints on latch points,
7 originating from input connectors (both from rising and falling transi-
8 tions).
9
10 A\bAR\bRG\bGU\bUM\bME\bEN\bNT\bTS\bS
11 f\bf File where to save the report, _\bs_\bt_\bd_\bo_\bu_\bt for standard output
12
13 t\btf\bf Pointer on the timing figure to consider
14
15 i\bin\bnp\bpu\but\btc\bco\bon\bnn\bne\bec\bct\bto\bor\br
16 Names of the connectors to consider, can be wildcards.
17
18 m\bmo\bod\bde\be Controls the amount of information displayed. Valid val-
19 ues are _\bs_\bu_\bm_\bm_\ba_\br_\by or _\ba_\bl_\bl (display path detail) associated
20 with _\bs_\bp_\bl_\bi_\bt. Using _\bs_\bp_\bl_\bi_\bt displays the report connector one
21 connector at a time. This option can also be used to
22 reduce memory usage on huge UTDs. _\bm_\ba_\br_\bg_\bi_\bn_\bs will show the
23 computed contsraints for each path in the summary. _\bp_\ba_\bt_\bh_\b-
24 _\bc_\bo_\bm_\bp permits will display the spice total error as total
25 spice delay versus total tas delay + path margin. By
26 default, the path margin is not included.
27
28 E\bEX\bXA\bAM\bMP\bPL\bLE\bE _\bt_\bt_\bv_\b__\bD_\bi_\bs_\bp_\bl_\ba_\by_\bC_\bo_\bn_\bn_\be_\bc_\bt_\bo_\br_\bT_\bo_\bL_\ba_\bt_\bc_\bh_\bM_\ba_\br_\bg_\bi_\bn _\b$_\bo_\bf_\bi_\bl_\be _\b$_\bf_\bi_\bg _\b"_\b*_\b" _\b"_\bs_\bu_\bm_\b-
29 _\bm_\ba_\br_\by _\bs_\bp_\bl_\bi_\bt_\b"
30