1 ################################################################################
4 # Copyright 2000 (c) Synopsys.
7 ################################################################################
9 # Title : SDC-parser commands declaration for SDC version 1.2
11 # Project : SDC-parser
13 # Authors : A.Gratchev
18 ################################################################################
25 {-level_sensitive Flag
}
26 {-edge_triggered Flag
}
28 } {!(param
(-level_sensitive) && param
(-edge_triggered))}
31 {-level_sensitive Flag
}
32 {-edge_triggered Flag
}
34 } {!(param
(-level_sensitive) && param
(-edge_triggered))}
36 declare create_clock
{
37 {-period Float
{$par>=0}}
39 {-waveform List
{type_Float
{length
($length>=2 && ($length % 2)==0)} } }
41 } {param
(-period) && (param
(-name) || param
(port_pin_list
))}
43 declare current_design
{
46 declare current_instance
{
54 {-hsc Enum
{{/} {@} {^
} {#} {.} {|}}}
55 } {(param
(patterns
) && !param
(-of_objects)) ||
\
56 (param
(-of_objects) && !param
(patterns
))}
57 # && !param(-hierarchical))}
63 declare get_lib_cells
{
65 {-hsc Enum
{{/} {@} {^
} {#} {.} {|}}}
68 declare get_lib_pins
{
70 {-hsc Enum
{{/} {@} {^
} {#} {.} {|}}}
80 {-hsc Enum
{{/} {@} {^
} {#} {.} {|}}}
86 {-hsc Enum
{{/} {@} {^
} {#} {.} {|}}}
93 declare set_case_analysis
{
94 {value Enum
{0 1 rising falling zero one rise fall
}}
96 } {param
(value
) && param
(port_pin_list
)}
98 declare set_clock_gating_check
{
99 {-setup Float
{$par>=0}}
100 {-hold Float
{$par>=0}}
106 } {(param
(-setup) || param
(-hold) || param
(-high) || param
(-low)) && \
107 !(param
(-high) && param
(-low))}
109 declare set_clock_latency
{
119 } {param
(delay
) && param
(object_list
)}
121 declare set_clock_transition
{
122 {transition Float
{1}}
128 } {param
(transition
) && param
(clock_list
) && \
129 !(param
(-rise) && param
(-fall))}
131 declare set_clock_uncertainty
{
132 {uncertainty Float
{1}}
140 } {param
(uncertainty
) && !(param
(object_list
) && (param
(-from) || param
(-to)))}
142 declare set_disable_timing
{
146 } {param
(object_list
) && \
147 !(param
(-to) ^ param
(-from))}
150 {resistance Float
{$par>=0}}
156 } {param
(resistance
) && param
(port_list
)}
158 declare set_driving_cell
{
165 {-multiply_by Float
{$par>=0}}
167 {-no_design_rule Flag
}
168 {-input_transition_rise Float
{$par>=0}}
169 {-input_transition_fall Float
{$par>=0}}
173 declare set_false_path
{
180 {-through List
{dup
}}
181 } {(param
(-from) || param
(-to) || param
(-through)) && \
182 !(param
(-rise) && param
(-fall)) && !(param
(-setup) && param
(-hold))}
184 declare set_fanout_load
{
185 {value Float
{$par>=0}}
187 } {param
(value
) && param
(port_list
)}
189 declare set_hierarchy_separator
{
190 {hchar Enum
{{/} {@} {^
} {#} {.} {|}}}
193 declare set_input_delay
{
196 {-level_sensitive Flag
}
202 {delay_value Float
{1}}
203 {port_pin_list List
}
204 } {param
(delay_value
) && param
(port_pin_list
) && \
205 !((param
(-clock_fall) || param
(-level_sensitive)) && !param
(-clock))}
207 declare set_input_transition
{
212 {transition Float
{$par>=0}}
214 } {param
(transition
) && param
(port_list
)}
219 {-substract_pin_load Flag
}
222 {value Float
{$par>=0}}
224 } {param
(value
) && param
(objects
)}
226 declare set_logic_dc
{
230 declare set_logic_one
{
234 declare set_logic_zero
{
238 declare set_max_area
{
239 {area_value Float
{$par>=0}}
240 } {param
(area_value
)}
242 declare set_max_capacitance
{
243 {capacitance_value Float
{$par>=0}}
245 } {param
(capacitance_value
) && param
(object_list
)}
247 declare set_max_delay
{
248 {delay_value Float
{1}}
253 {-through List
{dup
}}
254 } {param
(delay_value
) && \
255 !(param
(-rise) && param
(-fall))}
257 declare set_max_fanout
{
258 {fanout_value Float
{$par>=0}}
260 } {param
(fanout_value
) && param
(object_list
)}
262 declare set_max_time_borrow
{
263 {delay_value Float
{$par>=0}}
265 } {param
(delay_value
) && param
(object_list
)}
267 declare set_max_transition
{
268 {transition_value Float
{$par>=0}}
270 } {param
(transition_value
) && param
(object_list
)}
272 declare set_min_capacitance
{
273 {capacitance_value Float
{$par>=0}}
275 } {param
(capacitance_value
) && param
(object_list
)}
277 declare set_min_delay
{
278 {delay_value Float
{1}}
283 {-through List
{dup
}}
284 } {param
(delay_value
) && \
285 !(param
(-rise) && param
(-fall))}
287 declare set_multicycle_path
{
288 {path_multiplier Int
{1}}
297 {-through List
{dup
}}
298 } {param
(path_multiplier
)}
300 declare set_operating_conditions
{
301 {-analysis_type Enum
{single bc_wc on_chip_variation
}}
310 declare set_output_delay
{
313 {-level_sensitive Flag
}
319 {delay_value Float
{1}}
320 {port_pin_list List
}
321 } {param
(delay_value
) && param
(port_pin_list
) && \
322 !((param
(-clock_fall) || param
(-level_sensitive)) && !param
(-clock))}
324 declare set_port_fanout_number
{
325 {fanout_number Int
{($par>=0) && ($par<=100000)}}
327 } {param
(fanout_number
) && param
(port_list
)}
329 declare set_propagated_clock
{
331 } {param
(object_list
)}
333 declare set_resistance
{
334 {value Float
{$par>=0}}
338 } {param
(value
) && param
(net_list
)}
340 declare set_wire_load_min_block_size
{
341 {size Float
{$par>=0}}
344 declare set_wire_load_mode
{
345 {mode_name Enum
{top enclosed segmented
}}
348 declare set_wire_load_model
{
356 declare set_wire_load_selection_group
{
357 {-group_name String
}
364 # register_new_type EdgeList {
365 # if {[sdc::check_type List $value]} {
366 # if {[expr {[llength $value] % 2}] || [llength $value]==0} {
370 # set startvalue -0.1
372 # foreach parv $value {
373 # if {[catch {expr {$parv + 1}}]} {
376 # if {$parv<=$startvalue} {
379 # set startvalue $parv