Initial version of donated sources by Avertec, 3.4p5.
[tas-yagle.git] / distrib / share / tutorials / hitas / clock_gating / db.tcl
1 #!/usr/bin/env avt_shell
2
3 # Disassembly Configuration
4 avt_config yagDetectClockGating yes
5
6 # Drive partitionning report (facultative)
7 avt_config tasGenerateConeFile yes
8 avt_config avtVerboseConeFile yes
9
10 # Timing Configuration
11 inf_SetFigureName "circuit"
12 source circuit.sdc
13
14 # Technology Parameters
15 avt_LoadFile "../techno/bsim4_dummy.hsp" spice
16
17 # Netlist loading
18 avt_LoadFile "circuit.spi" spice
19
20 # Timing Database Generation
21 set fig [hitas "circuit"]
22
23 inf_ExportSections directives.inf directives