distrib/share/tutorials/yagle/dram/cells/cell_plus_sa.vhd

   1 entity cell_plus_sa is
   2   port(
   3     wl0, wl1 : in bit;
   4     wlen0, wlen1, prech, bl, blb, tozero, toone, eq0, eq1, blen: in bit;
   5     saen, saenb : in bit
   6     );
   7 end;
   8
   9 architecture normal of cell_plus_sa is
  10
  11 component cells
  12   port(
  13     bl0_up, blb0_up, bl1_dn, blb1_dn, wl0, wl1 : in bit
  14     );
  15 end component;
  16
  17 component gns_sensamp
  18   port(
  19     bl0, blb0, bl1, blb1, wlen0, wlen1, prech, bl, blb, tozero, toone, eq0, eq1, blen: in bit
  20     );
  21 end component;
  22
  23 component tn
  24    port    ( gate          : in    bit;
  25              source, drain : inout bit;
  26              bulk          : in    bit);
  27 end component;
  28
  29 component tp
  30    port    ( gate          : in    bit;
  31              source, drain : inout bit;
  32              bulk          : in    bit);
  33 end component;
  34
  35 signal bl0, blb0, bl1, blb1, vdd, vss : bit;
  36
  37 begin
  38
  39 -- pragma exclude sense trans_p trans_n
  40 -- pragma exclude_at_end cells
  41
  42   sense : gns_sensamp
  43     port map (
  44                bl0, blb0, bl1, blb1, wlen0, wlen1, prech, bl, blb, tozero, toone, eq0, eq1, blen
  45              );
  46
  47   cells : cells
  48     port map (
  49 --               bl0, blb0, bl1, blb1, wl0, wl1
  50                bl1, blb1, bl0, blb0, wl0, wl1
  51              );
  52
  53   trans_p : tp
  54     port map (
  55                saenb, toone, vdd, vdd
  56              );
  57
  58   trans_n : tn
  59     port map (
  60                saen, tozero, vss, vss
  61              );
  62 end;
  63