distrib/share/tutorials/yagle/dram/cells/cells.tcl

   1
   2 proc cells {} {
   3   global writesig
   4   begCreateInterface
   5   begAddMemDriver "mem00" "ext@$writesig and wl0 and (bl0_up xor blb0_up)" "bl0_up" 0 "fastwrite_delay"
   6   begAddMemDriver "mem01" "ext@$writesig and wl1 and (bl0_up xor blb0_up)" "blb0_up" 0 "slowwrite_delay"
   7   begAddMemDriver "mem10" "ext@$writesig and wl0 and (bl1_dn xor blb1_dn)" "bl1_dn" 0 "slowwrite_delay"
   8   begAddMemDriver "mem11" "ext@$writesig and wl1 and (bl1_dn xor blb1_dn)" "blb1_dn" 0 "fastwrite_delay"
   9
  10   begAddMemDriver "bl0_up" "not ext@$writesig and wl0" "mem00" 0 "fastread_delay"
  11   begAddMemDriver "blb0_up" "not ext@$writesig and wl1" "mem01" 0 "slowread_delay"
  12   begAddMemDriver "bl1_dn" "not ext@$writesig and wl0" "mem10" 0 "slowread_delay"
  13   begAddMemDriver "blb1_dn" "not ext@$writesig and wl1" "mem11" 0 "fastread_delay"
  14   begKeepModel
  15 }