distrib/share/tutorials/yagle/dram/test.v

   1 `timescale 1 ps/1 ps
   2
   3 module test;
   4
   5   reg ck ;
   6   wire dout;
   7   reg [1:0] a, din;
   8   reg sel = 1;
   9   reg write = 1;
  10
  11   /* Make a reset that pulses once. */
  12   initial begin
  13   $dumpfile("test.vcd");
  14   $dumpvars(10, test);
  15   $dumpon;
  16       a = 0;
  17       din=0;
  18       #5000 ck = 0;
  19       #15000 ck = 1;
  20      # 2000000 $finish;
  21  end
  22
  23   /* Make a regular pulsing clock. */
  24
  25   //always #10000 ck = !ck;
  26   always @(ck) #10000 ck <= !ck;
  27
  28   always #40000 din = din + 1;
  29   always #40000 a = a + 1;
  30   always #160000 write = write +1;
  31   always #320000 sel = sel +1;
  32
  33
  34
  35   dram ram(a,din,dout,write,ck,sel);
  36
  37   initial
  38      $monitor("At time %t, adr = %0d, din=%0d, dout = %0d, ck = %0d, write = %0d, sel = %0d",
  39               $time, a, din, dout, ck, write, sel);
  40 endmodule // test