distrib/share/tutorials/yagle/ram/cells/bank.vhd

   1 entity bank is
   2     generic (size, capacity, nbcolumn : integer);
   3     port ( data_in                  : in bit_vector(size - 1 downto 0);
   4            data_out                 : out bit_vector(size - 1 downto 0);
   5            com                      : in bit_vector(capacity - 1 downto 0);
   6            sel                      : in bit_vector(nbcolumn - 1 downto 0);
   7            wen                      : in bit;
   8            ck, cke, ckp             : in bit;
   9            vdd, vss                 : in bit);
  10     -- pragma symmetric com
  11     -- pragma symmetric data_in
  12     -- pragma symmetric data_out
  13     -- pragma symmetric sel
  14 end;
  15
  16 architecture structural of bank is
  17
  18     component bit_line
  19         generic ( capacity, nbcolumn: integer);
  20         port    ( data_in           : in    bit;
  21                   data_out          : out   bit;
  22                   com               : in    bit_vector(capacity - 1 downto 0);
  23                   sel               : in    bit_vector(nbcolumn - 1 downto 0);
  24                   wen               : in    bit;
  25                   ck, cke, ckp      : in    bit;
  26                   vdd, vss          : in    bit);
  27     end component;
  28
  29 begin
  30     loop : for i in 0 to size - 1 generate
  31         bit_line_i : bit_line
  32             generic map ( capacity, nbcolumn)
  33             port map    ( data_in(i), data_out(i),
  34                           com(capacity-1 downto 0), sel(nbcolumn-1 downto 0),
  35                           wen, ck, cke, ckp, vdd, vss);
  36     end generate;
  37 end;