distrib/share/tutorials/yagle_gns/ram4x128/ram4x128.c

   1 #include TBG_H
   2
   3 #define DESIGN      "ram4x128"
   4 #define DATA_SIZE    4
   5 #define ADR_SIZE     7
   6 #define UNIT         300
   7
   8 int    TCL = 120, TCH = 120, TCC = 240;
   9
  10 long puiss2(long a)
  11 {
  12   if (a)
  13     return puiss2(a-1)*2;
  14   else
  15     return 1;
  16 }
  17
  18 long invert(long a, long nb_bit)
  19 {
  20   long    i, r=0, m=puiss2(nb_bit-1);
  21
  22   for (i = 0; i < nb_bit; i ++)
  23   {
  24     r  += (a%2)*m;
  25     m  /= 2;
  26     a  /= 2;
  27   }
  28
  29   return r;
  30 }
  31
  32 void cycle(int nbcycle)
  33 {
  34   int    i;
  35
  36   for (i = 0; i < nbcycle; i ++)
  37     ExecuteCycle();
  38 }
  39
  40 int time(int i, int a)
  41 {
  42   return i*TCC + TCL + a;
  43 }
  44
  45
  46 int timer(int base, int a)
  47 {
  48   static int old, obase = 0;
  49   int        res;
  50
  51   if (base != obase)
  52   {
  53     obase   = base;
  54     res     = base + a;
  55     old     = a;
  56   }
  57   else
  58   {
  59     res     = a - old;
  60     old     = a;
  61   }
  62
  63   return res;
  64 }
  65
  66 void ckUP()
  67 {
  68   Assign ("ck"      , 1);
  69 }
  70
  71 void ckDW()
  72 {
  73   Assign ("ck"      , 0);
  74 }
  75
  76 void init()
  77 {
  78   Assign ("dout"    , FORCE_UNK);
  79   Assign ("adr"     , FORCE_UNK);
  80   Assign ("write"   , FORCE_UNK);
  81   Assign ("ck"      , FORCE_UNK);
  82   Assign ("en"      , 1);
  83   Assign ("vdd"     , 1);
  84   Assign ("vss"     , 0);
  85 }
  86
  87 void dead_cycle()
  88 {
  89   timer(0,0);
  90
  91   // __/¨¨
  92   ckUP();
  93   cycle(timer(TCH,0));
  94   // ¨¨\__
  95   ckDW();
  96   cycle(timer(TCH,TCL));
  97 }
  98
  99 void write_mem(long nextadress, long data)
 100 {
 101   data      = invert(data,4);
 102   timer(0,0);
 103   // __/¨¨
 104   ckUP ();
 105   cycle  (timer(TCH,-40));
 106   Assign ("write"    , 1);
 107   Assign ("dout"     , data);
 108   cycle(timer(TCH,0));
 109   // ¨¨\__
 110   ckDW();
 111   cycle  (timer(TCH,80));
 112   Assign ("adr"      , nextadress);
 113   cycle  (timer(TCH,100));
 114   Assign ("dout"     , WEAK_UNK);
 115   cycle  (timer(TCH,TCL));
 116   ckUP();
 117 }
 118
 119 void read_mem(long adress)
 120 {
 121   timer(0,0);
 122   // ¨¨\__
 123   ckDW();
 124   cycle  (timer(TCH,-40));
 125   Assign ("adr"      , adress);
 126   Assign ("write"    , 0);
 127   cycle(timer(TCH,0));
 128   // __/¨¨
 129   ckUP ();
 130   cycle  (timer(TCH,100));
 131   //Assign ("dout"     , WEAK_UNK);
 132   cycle  (timer(TCH,TCL));
 133   // ¨¨\__
 134   ckDW();
 135 }
 136
 137 void half_cycle()
 138 {
 139   timer(0,0);
 140   cycle(timer(TCH,0));
 141   ckDW ();
 142 }
 143
 144 int main (void)
 145 {
 146   int        i;
 147   int        test;
 148
 149   Period (UNIT, "ps");
 150   Design (DESIGN".vhd", DESIGN);
 151
 152   init();
 153
 154 //  dead_cycle();
 155 //  read_write_mem(long adress, long data, int read, int write)
 156 //  for (i = 0; i < ValMax("adr"); i ++)
 157   for (i = 0; i < 5; i ++)
 158     write_mem(i,i%ValMax("dout"));
 159   half_cycle();
 160 //  for (i = 0; i < ValMax("adr"); i ++)
 161   for (i = 0; i < 5; i ++)
 162     read_mem(i);
 163   write_mem(3,8);
 164   half_cycle();
 165   read_mem(3);
 166
 167   GenerateTestbench ("TB_"DESIGN);
 168
 169   return 0;
 170 }