distrib/sources/beh/bhl/beh_chkbefig.c

   1
   2 /* ###--------------------------------------------------------------### */
   3 /* file         : beh_chkbefig.c                                        */
   4 /* date         : Oct 30 1995                                           */
   5 /* version      : v109                                                  */
   6 /* authors      : Pirouz BAZARGAN SABET                                 */
   7 /* description  : high level function                                   */
   8 /* ###--------------------------------------------------------------### */
   9
  10 #include <stdio.h>
  11 #include "bhl_lib.h"
  12
  13 /* ###--------------------------------------------------------------### */
  14 /* function     : beh_chkbefig                                          */
  15 /* description  : check the consistency of a behavioural description    */
  16 /* called func. : none                                                  */
  17 /* ###--------------------------------------------------------------### */
  18
  19 int beh_chkbefig (befig_list *pt_befig, unsigned int  mode)
  20
  21   {
  22   struct beout *pt_beout ;
  23   struct beaux *pt_beaux ;
  24   struct bebus *pt_bebus ;
  25   struct bebux *pt_bebux ;
  26   struct bereg *pt_bereg ;
  27   int           err_flg  = 0;
  28
  29         /* ###------------------------------------------------------### */
  30         /*   check that the description is not empty                    */
  31         /* ###------------------------------------------------------### */
  32
  33   if (pt_befig == NULL)
  34     err_flg = 1;
  35
  36   else
  37     {
  38         /* ###------------------------------------------------------### */
  39         /*   check that each output has at least one driver. Outputs    */
  40         /* are simple output ports, bussed output ports, simple         */
  41         /* internal signals, delayed internal signals, bussed internal  */
  42         /* signals, and internal registers.                             */
  43         /* ###------------------------------------------------------### */
  44
  45     if ((mode & BEH_CHK_DRIVERS) != 0)
  46       {
  47         /* ###------------------------------------------------------### */
  48         /*   simple output ports                                        */
  49         /* ###------------------------------------------------------### */
  50
  51       pt_beout = pt_befig->BEOUT;
  52       while (pt_beout != NULL)
  53         {
  54         if (pt_beout->ABL == NULL)
  55           err_flg += beh_error (40, pt_beout->NAME);
  56         pt_beout = pt_beout->NEXT;
  57         }
  58
  59         /* ###------------------------------------------------------### */
  60         /*   simple internal signals                                    */
  61         /* ###------------------------------------------------------### */
  62
  63       pt_beaux = pt_befig->BEAUX;
  64       while (pt_beaux != NULL)
  65         {
  66         if (pt_beaux->ABL == NULL)
  67           err_flg += beh_error (40, pt_beaux->NAME);
  68         pt_beaux = pt_beaux->NEXT;
  69         }
  70
  71         /* ###------------------------------------------------------### */
  72         /*   delayed internal signals                                   */
  73         /* ###------------------------------------------------------### */
  74
  75       pt_beaux = pt_befig->BEDLY;
  76       while (pt_beaux != NULL)
  77         {
  78         if (pt_beaux->ABL == NULL)
  79           err_flg += beh_error (40, pt_beaux->NAME);
  80         pt_beaux = pt_beaux->NEXT;
  81         }
  82
  83         /* ###------------------------------------------------------### */
  84         /*   bussed output ports                                        */
  85         /* ###------------------------------------------------------### */
  86
  87       pt_bebus = pt_befig->BEBUS;
  88       while (pt_bebus != NULL)
  89         {
  90         if (pt_bebus->BIABL == NULL)
  91           err_flg += beh_error (40, pt_bebus->NAME);
  92         pt_bebus = pt_bebus->NEXT;
  93         }
  94
  95         /* ###------------------------------------------------------### */
  96         /*   bussed internal signals                                    */
  97         /* ###------------------------------------------------------### */
  98
  99       pt_bebux = pt_befig->BEBUX;
 100       while (pt_bebux != NULL)
 101         {
 102         if (pt_bebux->BIABL == NULL)
 103           err_flg += beh_error (40, pt_bebux->NAME);
 104         pt_bebux = pt_bebux->NEXT;
 105         }
 106
 107         /* ###------------------------------------------------------### */
 108         /*   internal registers                                         */
 109         /* ###------------------------------------------------------### */
 110
 111       pt_bereg = pt_befig->BEREG;
 112       while (pt_bereg != NULL)
 113         {
 114         if (pt_bereg->BIABL == NULL)
 115           err_flg += beh_error (40, pt_bereg->NAME);
 116         pt_bereg = pt_bereg->NEXT;
 117         }
 118
 119       }
 120
 121         /* ###------------------------------------------------------### */
 122         /*   check that the descriptiona has an empty architecture.     */
 123         /* that means, no internal signal is declared and output ports  */
 124         /* have no dreivers.                                            */
 125         /* ###------------------------------------------------------### */
 126
 127     if ((mode & BEH_CHK_EMPTY) != 0)
 128       {
 129         /* ###------------------------------------------------------### */
 130         /*   check that simple output ports have no drivers             */
 131         /* ###------------------------------------------------------### */
 132
 133       pt_beout = pt_befig->BEOUT;
 134       while (pt_beout != NULL)
 135         {
 136         if (pt_beout->ABL != NULL)
 137           break;
 138         pt_beout = pt_beout->NEXT;
 139         }
 140
 141         /* ###------------------------------------------------------### */
 142         /*   check that bussed output ports have no drivers             */
 143         /* ###------------------------------------------------------### */
 144
 145       pt_bebus = pt_befig->BEBUS;
 146       while (pt_bebus != NULL)
 147         {
 148         if (pt_bebus->BIABL != NULL)
 149           break;
 150         pt_bebus = pt_bebus->NEXT;
 151         }
 152
 153         /* ###------------------------------------------------------### */
 154         /*   check that the architecture is empty                       */
 155         /* ###------------------------------------------------------### */
 156
 157       if ((pt_befig->BEAUX != NULL) || (pt_befig->BEBUX != NULL) ||
 158           (pt_befig->BEDLY != NULL) || (pt_befig->BEREG != NULL) ||
 159           (pt_befig->BEMSG != NULL) || (pt_beout        != NULL) ||
 160           (pt_bebus        != NULL) )
 161         err_flg += beh_error (41, pt_befig->NAME);
 162
 163       }
 164
 165     pt_befig->ERRFLG = err_flg;
 166     }
 167
 168   return (err_flg);
 169   }