Initial version of donated sources by Avertec, 3.4p5.
[tas-yagle.git] / distrib / sources / man / man1 / hitas.1
1 .TH HITAS 1 "06 November 2001" "AVERTEC" "AVERTEC CAD Tools"
2
3 .SH NAME
4 .PP
5 \fBhitas\fP \- A switch level hierarchical static timing analyzer for CMOS circuits
6
7 .so man1/avt_origin.1
8
9 .SH SYNOPSIS
10 .PP
11 hitas \fI[options] root_file \fP
12
13 .SH DESCRIPTION
14 .PP
15 See the man \fBtas\fP(1).
16
17 .br
18 \fBhitas\fP assumes that the circuit under study is hierarchical.
19
20
21 .SH NOTES
22 \fBhitas\fP is equivalent to \fBtas\fP with the -hr option.
23 For more information see the man of \fBtas\fP, both
24 tools are identicals in regards of technicals informations.
25 .br
26
27
28 .SH OPTIONS
29 .PP
30
31 Options may appear in any order before or after the
32 input filename.
33 Options called with one single letter can be concatenated
34 (\fB-bei\fP for instance).
35
36
37 \fBhitas\fP has the same options as \fBtas\fP safe that the options
38 of \fBtas\fP incompatible with the -hr option is not availlable for
39 \fBhitas\fP.
40
41 .SH ENVIRONMENT VARIABLES
42 .PP
43 \fBhitas\fP has the same varialbes as \fBtas\fP.
44
45 .SH OUTPUT FILES
46 .PP
47 \fBhitas\fP has the same outputs as \fBtas\fP.
48
49 .SH SEE ALSO
50 .PP
51 tas(1), xtas(1), etas(1), yagle(1), dtv(5), ttv(5), inf(5), fcl(5)
52
53 .so man1/avt_bug_report.1
54