1 .TH HITAS 1 "06 November 2001" "AVERTEC" "AVERTEC CAD Tools"
5 \fBhitas\fP \- A switch level hierarchical static timing analyzer for CMOS circuits
11 hitas \fI[options] root_file \fP
15 See the man \fBtas\fP(1).
18 \fBhitas\fP assumes that the circuit under study is hierarchical.
22 \fBhitas\fP is equivalent to \fBtas\fP with the -hr option.
23 For more information see the man of \fBtas\fP, both
24 tools are identicals in regards of technicals informations.
31 Options may appear in any order before or after the
33 Options called with one single letter can be concatenated
34 (\fB-bei\fP for instance).
37 \fBhitas\fP has the same options as \fBtas\fP safe that the options
38 of \fBtas\fP incompatible with the -hr option is not availlable for
41 .SH ENVIRONMENT VARIABLES
43 \fBhitas\fP has the same varialbes as \fBtas\fP.
47 \fBhitas\fP has the same outputs as \fBtas\fP.
51 tas(1), xtas(1), etas(1), yagle(1), dtv(5), ttv(5), inf(5), fcl(5)
53 .so man1/avt_bug_report.1