1 .TH STB 1 "06 November 2001" "AVERTEC" "AVERTEC CAD Tools"
5 \fBstb\fP \- A stability analyzer that verify that setup and hold constraints are met.
11 stb \fI[options] root_file \fP
15 \fBstb\fP is a stability analyzer, which performs calculation of setup times and
16 hold times in CMOS circuits, handling clock skew and enabling cycle sharing exploitation.
17 Constraints are calculated for flip-flops and latches, precharged points, commands, output
18 connectors and user-defined points.
19 \fBstb\fP enables multiple clock domains analysis, and handles flip-flop based designs as well
20 as latch-based multiphases designs.
21 \fBstb\fP generates comprehensive stability reports, enabling the visualization of all the stability
22 states for constrained points.
26 Options may appear in any order before or after the input filename.
30 To be used generally with the -da option for crosstalk analysis.
31 With this option, STB uses the timing database in DTX format (gate graph). In this case, stability intervals for auxiliary nodes are also calculated.
35 Essential for crosstalk analysis.
36 With this option, all stability intervals are maintained, instead of merging them into a single interval for setup/hold verification.
40 With this option, STB performs a worst case analysis. Any latches are initialized assuming zero exploitation of the transparency, and the system is relaxed to identify stable operation with minimum transparency.
41 The default is to initialize the latches assuming maximum transparency.
45 With this option, latches clocked on the same phase as the origin of their data input are assumed to be flip-flops.
49 With this option, latches clocked on the same phase as the origin of their data input are assumed to be transparent.
53 With this option, latches clocked on the same phase as the origin of their data input are assumed to be errors.
57 With this option, only setup times are calculated.
61 With this option, only hold times are calculated.
65 With this option, only top level paths are taked into account for stability analysis.
69 With this option, all errors saved are redirected to a separate error file (suffix .ste).
73 With this option, the execution is in silent mode. No errors or warnings are reported unless they are fatal.
75 .SH INPUT SPECIFICATION FORMAT
77 The input format is generate by \fBhitas(1)\fP. It contains the information on the shortest and longest path delays, this is the timing database of a particular circuit or block.
81 The ".stb" file is an ascii text file made up of five sections. Any blank lines are ignored and lines starting with the "#" character are considered to be comment.
84 The five sections are:
88 - Clock Specifications
96 - Conditioned clock states
98 - Input connector stability specifications
100 - Output connector constraints to verify
104 As part of the general header any or all of the sections can be omitted. This sections must appear in the specified order.
105 The character '*' canbe used for any of the specified node names, matching any legal character string.
109 com* matches com1, com2, command, etc...
112 \fIThe general header\fP
113 The format of the header is as follows :
128 The name is the name of the block to analyse, and is the the as the basename of the file.
129 The version "1.00" corresponds to the current file format version.The last three values are integers representing times in picoseconds.
130 The period is the default clock period for clocks whose period is not specified. The setup and hold are global margins of safety for the setup and hold verifications.
131 It is possible to omit the default period specification so long as each clock has a period associated with its definition or via the domain definition.
134 \fIClock specifications\fP
135 This section is used to define all the external clock signals.
137 The syntax is as follows:
168 For each of the external clock connectors, four parameters must be given:
169 the earliest and latest instant of the falling edge, and the earliest and latest instant of the rising edge.
170 The order is irrelevant, the actual values themselves are used to order the clock phases within the period.
173 \fIClock domains specifications\fP
174 This section allows the user to assign clock connectors to clock domains. Timing checks are only performed on paths which do not cross domain boundaries. Each domain must be given a name, however the name itself is purely facultatif.
176 The syntax is as follows :
179 asynchronous clock groups
183 <domain1>: <list_of_clocks>
191 <domainn>: <list_of_clocks>
199 Each domain contains the list of clock connectors which make up the domain. The period of the clocks can be specified here, since clocks in the same domain must have identical periods.
202 \fIEquivalent clocks\fP
203 This section allows the user to indicate that separate clock connectors should be treated as having identical phases.
205 The syntax is as follows :
208 equivalent clock groups
212 <group1>: <list_of_clocks>
218 <groupn>: <list_of_clocks>
224 Each group contains the list of clock connectors which make up the equivalent group.
227 \fIMultiple clock priority\fP
228 This section allows the user to specify which clock should be considered as having the priority in the case of clocked signals (latches, flip-flops or precharges) which depend on multiple clocks.
229 Defining priority clocks is useful in the case4 of multiple clocks due to multiple operating modes (e.g. test mode or functional mode).
231 The syntax is as follows :
234 multiple clock priority
238 <clocked_signal>: <clock_connector>
244 <clocked_signal>: <clock_connector>
249 Each line associates a clocked signal with its highest priority clock connector.
251 .SH THE OUTPUT STABILITY FILE FORMAT
253 \fBstb\fP generates the extension ".sto", and an extension ".str" for the timing report.
256 \fIoutput_file.sto\fP
257 The '.sto' file is an ascii text file made up of six distinct sections.
259 The six sections are :
262 - Clock Specifications
264 - Conditioned clock states
266 - Input connector stabilityintervals
268 - Output connector stability intervals
270 - Internal node stability intervals
273 Apart from the general header, some of the sections may be omitted.
276 \fIInput connector stability intervals\fP
277 This section gives the stability intervals at the input terminals.
279 The syntax is as follows :
282 input connectors stability
286 <input1> [from <phase>]:
296 <inputn> [from <phase>]:
305 That will be equivalent to the input connectors stability specification given in the '.stb' file except that every input connector is specified explicitly.
306 INOUT connectors are grouped with the output connectos in the subsequent section.
310 \fIOutput connector stability intervals\fP
311 This section specifies the stability intervals at the output terminals.
313 The syntax is as follows:
316 output connectors stability
319 <output1> [from <phase>]:
329 <outputn> [from <phase>]:
338 This section gives the stability intervals calculated for all internal nodes.
339 If the analysis is performed on the critical path graph (the default), then the set of internal nodes consists solely of latch data and command input and precharges. If the analysis is performed on the causality (gate) graph, then the set includes all auxiliary nodes.
342 \fIThe timing report\fP
343 Generated by \fBstb\fP, it has the suffix '.str' and a basename identical to that of the original circuit. It lists the setup and hold margins calculated for all critical circuit nodes.
351 - Conditioned memory commands
356 All memory and conditioned command nodes are specified with the details of their local clock, since this is the reference for the setup and hold calculations.
357 A negative value for a setup or hold margin indicates a violation. In the event of a violation on a particular node, all data sources resulting in a violation are listed for that node, together with their individual setup and hold margins.
359 .SH ENVIRONMENT VARIABLES
363 If this variable is "yes" then STB displays all intermediary values of the stability intervals calculations on stdout.
364 Useful to see how the relaxation progresse
368 Indicates the language used by TAS and STB, "english" by default or "french".
372 Indicates where STB has to read the input file and write the resulting files.
373 The default is the current directory.
378 The STB command is used as follows :
379 stb \fI[options] root_file\fP
382 \fBstb\fP requires a complete timing database for the circuit to be analyzed (in DTX or TTX format, corresponding to the gate graph and the critical path graph respectively).
383 The default mode generates a timing report STR file containing the calculated setup and hold margins and an STO file containing the stability intervals calculated at the interface of the circuit analyzed.
385 .SH EXAMPLE STABILITY SPECIFICATION FILE
387 Since this file must be provided by the user, an example is shown here for clarification.
416 conditioned command states
428 specify input connectors
434 unstable 1000 after ck rising;
436 stable 3000 after ck rising;
440 unstable 500 after ck rising;
442 stable 4000 after ck rising;
448 verify output connectors
454 unstable 1000 after ck rising;
456 stable 3000 after ck rising;
460 unstable 500 after ck rising;
462 stable 4000 after ck rising;
469 hitas(1), tas(1), inf(5), dtx(5), ttx(5)
474 .so man1/avt_bug_report.1
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