1 .TH YAGLE 1 "30 March 2000" "AVERTEC" "AVERTEC CAD Tools"
4 yagle \- Disassembly and functional abstraction of CMOS circuits
62 is a circuit disassembler and functional abstractor for CMOS digital circuits.
63 It generates a VHDL data flow description and an oriented gate net-list
64 from a transistor level description of the circuit. The transistor net-list
65 can be either flat or hierarchical.
67 The VHDL subset generated by
69 is supported by most simulation and synthesis tools.
72 does not use a predefined gate library except for latches and flip-flops.
73 All styles or circuitry are supported: dual-cmos, precharge, pass-transistor, etc.
74 In addition a user-defined gate library can be provided in order to handle complex latches
77 \fBAll power supplies and grounds signals must be connected to an external connector.\fB
81 extracts the CMOS dual circuitry.
84 builds the gate net-list for the remaining circuitry whilst performing functional
85 analysis in parallel, in order to prevent the fabrication of false branches
86 within a gate and to verify the behaviour of the gate.
88 This functional analysis depends on the '-p=n' option which defines the maximum
89 depth (in gates) of the analysis.
92 reads the transistor net-list given by
94 and generates a VHDL data flow description in
104 Options may be given in any order before or after the filename(s).
108 When this option is set, the interface and the internal signal of the behavioural
109 description are vectorised. Every bit of the vector has to be of the same type
110 otherwise the functional description will not be generated.
113 This option sets the maximum depth for the functional analysis.
114 This is the depth of circuitry (in gates) taken into account when detecting
115 reconvergences in the circuit. The default value is 5.
118 = 0, the functional analysis process is disabled.
121 Disables the detection of complex gates. Without this option complex gates such
122 as edge-triggered flip-flops are identified by pattern-matching applied to the
123 disassembled gate net-list. Special predefined behavioural descriptions are then
124 generated for these gates. This option is useful if a one to one correspondance
125 between the elements of the behavioural description and the elements of the
126 disassembled gate net-list is required.
129 Disables the detection of latches and memory points using the built-in latch
130 library. This option is useful if all memory points are to be detected by
131 the use of a user-defined library with the
138 use library-based transistor netlist recognition (see man fcl). This
139 allows the user to specify a number of netlists to be identified within the
140 circuit to be disassembled. These netlists are specified in the Spice format and
141 can contain a number of special directives for the marking of the identified
142 signals and transistors in the circuit, for example signals corresponding to
143 memory points or transistors to be ignored.
145 In addition the user can specify a behavioural description for the transistor
146 netlist which is used to generate the global
147 behavioural description of the circuit. This allows the functional abstraction
148 of circuits containing analog blocks for example RAMs containing sense amplifiers.
151 Same as \-fcl. In addition, it makes yagle stop after the recognition process.
156 uses the elp tecnology file (man elp) to update the capacitances in the input
157 transistor net-list. So that the cns and structural views contain accurate
162 orients transistors using a simple rule:
163 A transistor whose source is connected to the output of a CMOS Duals gate, and
164 not connected to a transistor gate, is oriented form source to drain. This
165 orientation is performed during the phase of extraction of CMOS duals.
168 When this option is set,
170 exploits high impedance nodes during the phase of
171 functional analysis. This allows, for example, the resolution of false conflicts
172 in circuits which use precharge logic.
175 This option provides only one power supply and ground connector in the interface
176 of the behavioural description. This can be useful in order to compare the
177 abstracted description with the initial specification. When this option is set,
178 the name of power supply and ground
184 Disables the generation of the behavioural description of the circuit, useful if
185 the user is solely interested in the gate-level net-list.
188 .B yagle generates a structural gate level net-list. The variable MBK_OUT_LO has to be set to
189 choose the format of the out files: the net-list and the gates. A behavioural
190 description is generated for each gate.
194 generates a .cns file which contains the flat gate net-list. This file is mainly
200 read the .inf file. This file should have the same name
201 as the input file with extesion .inf. It may contain mutual exclusion
202 conditions on ports of the circuit. These conditions are only used in the
203 functional analysis process.
205 # lines beginning with '#' are comment lines
207 Syntax for the mutual exclusion conditions
222 muxUP expresses that one port at most in the list is "one".
224 muxDN expresses that one port at most in the list is "zero".
226 cmpUP expresses that one and only one port in the list is "one".
228 cmpDN expresses that one and only one port in the list is "zero".
231 Port name may be preceded by the character '~' which minds that it is the inverse
232 of the port which has to be taken into account.
235 The user can also use this file to rename internal signals in the behavioural
236 description in order to use the formal proof.
239 Syntax to rename signals for the behavioural description
243 existing_name : new_name ;
245 *gno* : *latch_data* ;
250 "new_name" will replace "existing_name" in the behavioural description file.
251 It is possible to use the joker '*'. When the names contain the string "gno",
252 this string is replaced by the string "latch_data" (l2_y_gno_01 is replaced by
255 Beware that only one rule can be applied to a name, (the following rules
256 are then ignored when one has been applied) and that the rules are
257 taken into account in the order in which they appear in the 'inf' file.
260 Set the trace mode during execution, used only for debugging purposes.
265 Activate transistor orientation taking into account the \fB_s\fP
266 convention on signal's names.
272 The functional description is described in a file called
275 .I output_name, with extension .vbe.
278 The disassembled gate net-list or cone net-list description when the
283 The structural description when the
288 The errors and warnings report file.
290 File containing list of combinatorial loops file, only created if loops exist
291 and the environment variable
295 .SH ENVIRONMENT VARIABLES
298 indicates the format of the input net-list.
301 spi for Spice net-list.
303 al for Alliance extracted net-list.
308 indicates the format of the output net-list when the
310 option is set. Same values as
314 Indicates where YAGLE has to read the input file and write the resulting files.
317 If the input net-list is hierarchical, the leaf cells may not be in the working
318 directory MBK_WORK_LIB. In that case, MBK_CATA_LIB indicates where YAGLE can
322 Sets the name of power supply. "vdd" is the default. Every external port of the
323 circuit whose name contain this string will be considered as a power supply.
326 Sets the name of the ground. "vss" is the default. Every external port of the
327 circuit whose name contain this string will be considered as a ground.
330 Sets the name of the grid connector of a transistor. "grid" is the default.
333 Sets the name of the source connector of a transistor. "source" is the default.
336 Sets the name of the drain connector of a transistor. "drain" is the default.
339 Sets the full access path and name of the technology file (.elp) used to correct
340 the node capacitances in the circuit.
343 Sets the extension of the file that will contain the VHDL description. "vbe" is
349 will report errors and warnings in French.
352 will report errors and warnings in English.
353 The default is English.
358 generates a file with the extension .stat which contains statistics of the
362 Sets the the maximum possible length of a branch within a gate. The default is
368 looks for combinatorial loops in the disassembled circuit, if any are found,
370 are reported in a file with extension
372 Note that any two gate loops are systematically reported in the
377 Sets the the maximum number of BDD nodes. The default is 10000, 0 means no ceiling.
380 When set to 'yes', this variable inhibits the construction of branches through a transistor already used
381 in the opposite orientation.
383 .B YAGLE_GEN_SIGNATURE
384 When set to 'no', yagle does not generate signatures for the cones, therefore .slib icones are not
388 Indicates the access path to the directory containing the user-defined cell
391 option is set. The default is a subdirectory
397 The name of the file (located in
399 ) containing the list of cells in the user-defined cell library used if the
401 option is set. The default is
408 "[WAR] Possible unconnected supply ?"
410 means that an internal signal whose name contains
414 has been found. Verify if this signal should be connected to an external supply.
416 "[WAR] Transistor used as a resistance"
418 Indicates that a transistor P (resp. N) with gate connected to the ground
419 (resp. power supply) has been found in the circuit.
421 "[WAR] Transistor used as a diode"
423 Indicates that a transistor with drain (or source) connected to gate has been
424 found in the circuit, and the signal connecting them is neither power supply nor
427 "[WAR] Transistor is always off"
429 Indicates that a transistor P (resp. N) with gate connected to power supply
430 (resp. ground) has been found in the circuit.
432 "[WAR] Transistor used as a capacitance"
434 Indicates that a transistor with drain and source connected together has been
435 found in the circuit.
437 "[WAR] Gate of transistor is not connected"
439 Indicates that a transistor gate which is connected to nothing has been found
442 "[WAR] Drain of transistor is not connected"
444 Indicates that a transistor drain which is connected to nothing has been found
447 "[WAR] Source of transistor is not connected"
449 Indicates that a transistor source which is connected to nothing has been found
452 "[WAR] Transistors are not used in the circuit"
454 This means that these transistor are not used to pull up or pull down any
455 transistor gate in the circuit, or any external port. This occurs if the output
456 of an inverter does not drive anything: In this case
459 transistors of the inverter to be unused.
461 "[WAR] Loop between 2 gates (bleeder found)"
463 This means that a loop corresponding to a bleeder has been found in the circuit.
465 "[WAR] Loop between 2 gates (latch found)"
467 This means that a loop corresponding to a latch has been found in the circuit.
469 "[WAR] Loop between 2 gates (bistable found)"
471 This means that a loop corresponding to a bistable has been found in the circuit.
473 "[WAR] Loop between 2 gates (nothing found)"
475 This means that a two gate loop which does not correspond to a latch, bleeder
476 or bistable has been found in the circuit.
478 "[WAR] Conflict may occur on signal"
480 This means that the signal may be pulled-up and pulled-down simultaneously. This
481 is a warning since this message may disappear with a greater depth for the
482 functional analysis process.
484 "[WAR] HZ state may occur on signal"
486 This means that the signal is not pulled up or pulled down for every input
487 pattern on the cone entries. This is a warning since this message may disappear
488 with a greater depth for the functional analysis process.
490 "[WAR] Signal does not drive anything"
492 This means that the the signal is not used as the input to any gate or used
493 to drive any external connector.
495 "[WAR] Connector unused"
497 This means that the external connector is neither the input nor the output of
498 any of the extracted transistor gates.
500 "[ERR] Bad direction on connector"
502 Indicates that the orientation of an external connector after disassembly does not correspond
503 to that specified in the input net-list.
505 "[ERR] Transistor gate signal is not driven"
507 Indicates that a transistor gate can not be pulled up or down.
509 "[FATAL ERR] No VDD/VSS connector in the circuit"
513 did not find any external ports whose name is the name of the power supply in the
514 circuit. Have CNS_VDDNAME and CNS_VSSNAME the right value?
516 "[FATAL ERR] Connector is power supply and ground"
520 found a connector whose name includes
524 "[FATAL ERR] No VDD/VSS signal in the circuit"
528 did not find any signal whose name is the name of the power supply in the
531 "[FATAL ERR] Several external connectors on signal"
535 found several external connectors connected to the same equipotential, a configuration
536 which it considers illegal.
539 .so man1/avt_bug_rprt.1