1 .TH CNS 5 "06 November 2002" "AVERTEC" "File Formats"
6 YAGLE and TAS data structure to represent extracted gate net-lists.
12 The CNS data structure is designed to represent extracted gate net-lists.
13 It has evolved out of the need for a common data structure for CAD-CLSI
14 verification tools such as: formal verification, timing and power
15 analysis, and logico-temporal simulation.
17 The CNS data structure combines the precision advantage of a transistor
18 net-list with the speed advantage of a logical gate net-list.
19 This is achieved by representing the circuit as a directed acyclic graph
20 representing signal-flow within the circuit.
21 Each node of this graph is a type of pseudo logical gate known as a cone.
22 A graph representation of the circuit allows the direct implementation
23 of rapid transversal algorithms useful in simulation and timing analysis.
27 A Cone is the disassembled equivalent of a logical gate. It is made up of branches,
28 a branch corresponding to a path from the node on which the cone is built to an external
29 port across transistor source-drain junctions.
32 Each cone contains up to four sets of branches but at least one. These set correspond
33 to the type of external port on which the branch ends.
35 The four types are: VDD, VSS, EXT and GND, corresponding to branches terminating on Vdd
36 or Vss power supplies, external connectors, or ground (inclued for GaAs compatibility)
39 For external connector branches the final link of the branch points to the corresponding
43 The connectivity between cones is represented by edges. Each cone contains two list of
44 edges: one for the inputs, and one for the outputs.
45 An edge contains a pointer to an object to which the cone is connected (cone or external
46 connector) and a type indicating the type of object and certains characteristics of the
49 .SH ENVIRONMENT VARIABLES
51 The environment variables allow selection of the ouput format and icontrol the display of trace and debug information.
54 \fICNS_DRIVE_VERBOSE\fP
55 If the value of this variable is set to "yes", then
56 a CNV format file is driven.
59 \fICNS_DRIVE_NORMAL\fP
60 If the value of this variable is set to "yes", then
61 a CNS format file is driven.
65 An integer which, if greater than or egal to 1, indicates that
66 an execution trace of all
67 CNS functions is displayed. the default value is 0.
71 An integer which, if greater than or egal to 2, indicates that additionnal
72 figure coherency checks should be performed, this can significantly increase
73 execution time. The default value is 0.
77 The file format is "file_name.cns" or "filename.cnv", where
78 "file_name" is the name of the figure.
79 If neither \fICNS_DRIVE_VERBOSE\fP nor \fICNS_DRIVE_NORMAL\fP is set to "yes" then
80 the CNS format is driven.
81 If both are specify, CNS and CNVformats are driven.
85 The CNV file is a more readable version of the CNS file.
86 Both files contains the same information and are equivalent.
87 The CNS file is a less readeable format more suited for parsing.
89 .SH CNS AND CNV SECTIONS
91 The CNS and CNV files have the same structure. These files are made
92 up of distinct sections.
94 The five sections are:
107 .SH THE CNS and CNV SECTIONS
109 The following descriptions of the sections match with the CNV file.
110 Even is the CNS file contains the same informations than the CNV file,
111 the redaction of the two file is quite different.
112 In order to have a better understanding what follows, make sure you have
113 generated the CNV file by setting the proper Environment Variable.
117 The Header in CNV looks like:
120 CNS V<number> <techno> Created by <name> on <date>
122 Figure: <figure name>
124 Netlist format: <format name>
126 Capacitance Scale: <number>
131 The first information in the HEADER is the CNS version number.
135 Following the CNS version is the technology of the figure.
136 Usually set to 'npmosfet' to indicate MOS technology.
140 The informations given in the HEADER contains the user name and
141 the date of creation of the file.
145 This is the figure name.
149 This is the input netlist format.
152 \fICapacitance Scale\fB
153 The capacitance scale factor.
156 .B EXTERNAL CONNECTORS
157 There is an example on EXTERNAL CONNECTOR description in CNV:
160 <index number>) <name> (<type>)
165 An index associated to the connector, counting the number of connector to this point.
166 References can be made to this number in order to identify the connector in the list.
170 This is the connector name.
174 The connector type can be INPUT, OUTPUT, TRISTATE or a POWER SUPPLY.
175 The connector type is indicated in brackets following the connector name.
179 In CNV a transistor is described as follows:
182 <index>) <name>, Type <type> driven by '<name>',
183 Position = (<number>,<number>),
184 Width=<number>, Length=<number>,
185 PS=<number>, PD=<number>,
186 XS=<number>, XD=<number>
191 An index associated with the transistor.
192 References can be made to this number in order to identify the transistor in the list.
196 The name of the transistor is composed of two letters: "tr", followed by a number.
200 Indicate the transistor type.
202 Can be TN or TP, respectively for N and P transistor.
206 The name of the cone connected to the transistor gate.
209 \fITransistor Position\fB
210 If the information has been extracted, it gives the localistation of the transistor in the layout.
212 By default set to (0,0).
216 Width, Length, PS, PD, XS, XD define the pysical dimensions of the transistor.
220 In CNV, a cell is described as follows:
223 <index>) Model <number>
232 An index associated to the cell, counting the number of cell to this point.
233 References can be made to this number in order to identify the cell in the list.
237 Regroupes under the same model an ensemble of cone which structure has been defined
238 by the user in order to perform pattern matching.
244 In CNV a cone is described as follows:
250 TecTytpe: <technology>
254 <edge type> '<name of the edge>'
258 <edge type> '<name of the edge>'
262 <index>) <type of the branche>
264 <link type> <name> (Index=<number>)
265 Driven by '<cone name>', Capa = <number>
270 An index associated to the cones, counting the number of cones to this point.
271 References can be made to this number in order to identify the cones in the list.
275 Following the index is the cone name.
279 Specifiy certains of the cone particularity if needed.
283 The technologic characteristics of the cone.
287 Indicates the type and name of the input edges.
289 Type can be either a cone or an external connector.
293 Indicates the type and name of the output edges.
295 Type can be either a cone or an external connector.
299 For each branche there is an index followed by the
300 branch which can be Vdd, Vss, Ext or Gnd (See \fITHE CONES\fP).
301 The branch type can be followed by a list in brackets.
302 Each terms of this list indicating characteristics of the branch.
304 Each branch contains a list of links, each one beginning by the link
305 type, TN or TP, followed by the number appearing in the name of the
308 For convenience, the index of the link is indicated in brackets just after
309 this number, refering to the list of transistor.
311 Follows the name of the cone driving the transistor gate, and the capacitance
316 A more complete exemple of Cone is given for comprehension:
322 Type: Flip-Flop,Master
324 TecTytpe: Degraded Vdd
332 Cone loop feedback 'spi_81'
342 TN 47 (Index=190) (Command) Driven by 'ck', Capa = 16.40
344 TP 169 (Index=68) Driven by 'auxsc33', Capa = 7.00
346 2) Vdd (Non-Functional,Feedback)
348 TP 168 (Index=69) Driven by 'spi_81', Capa = 16.40
352 TN 47 (Index=190) (Command) Driven by 'ck', Capa = 16.40
354 TN 51 (Index=186) Driven by 'auxsc33', Capa = 7.00
356 4) Vss (Non-Functional,Feedback)
358 TN 42 (Index=195) Driven by 'spi_81', Capa = 16.40
367 yagle(1), tas(1), hitas(1)
369 .so man1/avt_bug_report.1
projects / tas-yagle.git / blob