1 /****************************************************************************/
3 /* Chaine de CAO & VLSI Alliance */
5 /* Produit : GENIUS v1.00 */
6 /* Fichier : gen_verif_PortMap.h */
8 /* Auteur(s) : Francois DONNET le : 10/06/1999 */
10 /* (c) copyright 1999 Laboratoire MASI equipe CAO & VLSI */
11 /* Tous droits reserves */
12 /* Support : e-mail alliance-support@asim.lip6.fr */
15 /****************************************************************************/
17 #define DEFAULT_ARRAY 0x4 /* for a generic vector, give a minimal size */
18 #define RAND_BYTE ((rand()&0xF)+DEFAULT_ARRAY) /* value for a generic variable */
21 /***************************************************************************/
22 /* change a tree of generic variables in a list of ptypeput on top of var */
23 /***************************************************************************/
24 extern ptype_list
*GenTree2chain(tree_list
*tree
, ptype_list
*var
);
26 /***************************************************************************/
27 /* Verify that all instances of tree match with components Comp and generic*/
28 /* variables and signals Sig */
29 /* result put on top of Ins */
30 /***************************************************************************/
31 extern chain_list
*Verif_Instance(tree_list
*tree
, chain_list
*Sig
,
32 ptype_list
*env
, chain_list
*Comp
,