Initial version of donated sources by Avertec, 3.4p5.
[tas-yagle.git] / distrib / sources / yagle / genius / gen_verif_PortMap.h
1 /****************************************************************************/
2 /* */
3 /* Chaine de CAO & VLSI Alliance */
4 /* */
5 /* Produit : GENIUS v1.00 */
6 /* Fichier : gen_verif_PortMap.h */
7 /* */
8 /* Auteur(s) : Francois DONNET le : 10/06/1999 */
9 /* */
10 /* (c) copyright 1999 Laboratoire MASI equipe CAO & VLSI */
11 /* Tous droits reserves */
12 /* Support : e-mail alliance-support@asim.lip6.fr */
13 /* */
14 /* */
15 /****************************************************************************/
16
17 #define DEFAULT_ARRAY 0x4 /* for a generic vector, give a minimal size */
18 #define RAND_BYTE ((rand()&0xF)+DEFAULT_ARRAY) /* value for a generic variable */
19
20
21 /***************************************************************************/
22 /* change a tree of generic variables in a list of ptypeput on top of var */
23 /***************************************************************************/
24 extern ptype_list *GenTree2chain(tree_list *tree, ptype_list *var);
25
26 /***************************************************************************/
27 /* Verify that all instances of tree match with components Comp and generic*/
28 /* variables and signals Sig */
29 /* result put on top of Ins */
30 /***************************************************************************/
31 extern chain_list *Verif_Instance(tree_list *tree, chain_list *Sig,
32 ptype_list *env, chain_list *Comp,
33 chain_list *Ins);
34
35