distrib/sources/yagle/genius/gen_verif_exp_VHDL.c

   1 /****************************************************************************/
   2 /*                                                                          */
   3 /*                      Chaine de CAO & VLSI   Alliance                     */
   4 /*                                                                          */
   5 /*    Produit : GENIUS   v1.00                                              */
   6 /*    Fichier : gen_verif_exp_VHDL.c                                        */
   7 /*                                                                          */
   8 /*    Auteur(s) : Francois DONNET                        le : 10/06/1999    */
   9 /*                                                                          */
  10 /*    (c) copyright 1999 Laboratoire MASI equipe CAO & VLSI                 */
  11 /*    Tous droits reserves                                                  */
  12 /*    Support : e-mail alliance-support@asim.lip6.fr                        */
  13 /*                                                                          */
  14 /*                                                                          */
  15 /****************************************************************************/
  16
  17
  18 #include <stdio.h>
  19 #include MUT_H
  20 #include MLO_H
  21 #include API_H
  22 #include AVT_H
  23 #include "gen_verif_utils.h"
  24 #include "gen_verif_exp_VHDL.h"
  25
  26
  27
  28 /***************************************************************************/
  29 /*          Control the expression of FOR in VHDL for later searching      */
  30 /*                 env list of variables with their values                 */
  31 /***************************************************************************/
  32 extern int Verif_HighBound_FOR(tree,env)
  33    tree_list *tree;
  34    ptype_list *env;
  35 {
  36   int var1,var2;
  37   if (!tree) {
  38     avt_errmsg(GNS_ERRMSG, "004", AVT_FATAL, 208);
  39     //fprintf(stderr,"Verif_HighBound_FOR: NULL pointer\n");
  40     EXIT(1);
  41   }
  42   switch (TOKEN(tree)) {
  43   case '+':  case '-':  case '*':  case '/':
  44       var1=Verif_HighBound_FOR(tree->NEXT,env);
  45       var2=Verif_HighBound_FOR(tree->NEXT->NEXT,env);
  46       if (var1 && var2) {
  47     avt_errmsg(GNS_ERRMSG, "134", AVT_ERROR, FILE_NAME(tree),LINE(tree));
  48    //      fprintf(stderr,"%s:%d: Only one variable authorized in a 'for' expression. Use Hierarchy!\n",FILE_NAME(tree),LINE(tree));
  49          Inc_Error();
  50          return 0;
  51       }
  52       return var1||var2;
  53       break;
  54   case '%':
  55       var1=Verif_HighBound_FOR(tree->NEXT,env);
  56       var2=Verif_HighBound_FOR(tree->NEXT->NEXT,env);
  57       if (var1 && var2) {
  58     avt_errmsg(GNS_ERRMSG, "134", AVT_ERROR, FILE_NAME(tree),LINE(tree));
  59   //       fprintf(stderr,"%s:%d: Only one variable authorized in a 'for' expression. Use Hierarchy!\n",FILE_NAME(tree),LINE(tree));
  60          Inc_Error();
  61          return 0;
  62       }
  63       if (var1||var2) {
  64     avt_errmsg(GNS_ERRMSG, "135", AVT_ERROR, FILE_NAME(tree),LINE(tree),"rem");
  65 //         fprintf(stderr,"%s:%d: forbidden operator 'rem' on variable\n",FILE_NAME(tree),LINE(tree));
  66          Inc_Error();
  67       }
  68       return var1||var2;
  69       break;
  70   case GEN_TOKEN_MOD:
  71       var1=Verif_HighBound_FOR(tree->NEXT,env);
  72       var2=Verif_HighBound_FOR(tree->NEXT->NEXT,env);
  73       if (var1 && var2) {
  74     avt_errmsg(GNS_ERRMSG, "134", AVT_ERROR, FILE_NAME(tree),LINE(tree));
  75     //     fprintf(stderr,"%s:%d: Only one variable authorized in a 'for' expression. Use Hierarchy!\n",FILE_NAME(tree),LINE(tree));
  76          Inc_Error();
  77          return 0;
  78       }
  79       if (var1||var2) {
  80     avt_errmsg(GNS_ERRMSG, "135", AVT_ERROR, FILE_NAME(tree),LINE(tree),"mod");
  81   //       fprintf(stderr,"%s:%d: forbidden operator 'mod' on variable\n",FILE_NAME(tree),LINE(tree));
  82          Inc_Error();
  83       }
  84       return var1||var2;
  85       break;
  86   case GEN_TOKEN_POW:
  87       var1=Verif_HighBound_FOR(tree->NEXT,env);
  88       var2=Verif_HighBound_FOR(tree->NEXT->NEXT,env);
  89       if (var1 && var2) {
  90     avt_errmsg(GNS_ERRMSG, "134", AVT_ERROR, FILE_NAME(tree),LINE(tree));
  91     //     fprintf(stderr,"%s:%d: Only one variable authorized in a 'for' expression. Use Hierarchy!\n",FILE_NAME(tree),LINE(tree));
  92          Inc_Error();
  93          return 0;
  94       }
  95       if (var1||var2) {
  96     avt_errmsg(GNS_ERRMSG, "135", AVT_ERROR, FILE_NAME(tree),LINE(tree),"**");
  97     //     fprintf(stderr,"%s:%d: forbidden operator '**' on variable\n",FILE_NAME(tree),LINE(tree));
  98          Inc_Error();
  99       }
 100       return var1||var2;
 101       break;
 102   /*nodes..*/
 103   case GEN_TOKEN_NODE:
 104       return Verif_HighBound_FOR(tree->DATA,env);
 105       break;
 106   case GEN_TOKEN_OPPOSITE:
 107       return Verif_HighBound_FOR(tree->NEXT,env);
 108       break;
 109   case GEN_TOKEN_DIGIT:
 110       return 0;
 111       break;
 112   case GEN_TOKEN_IDENT:
 113       return 1;
 114       break;
 115   default:
 116     Error_Tree("Verif_HighBound_FOR",tree);
 117     EXIT(1); return 0;
 118   }
 119 }
 120
 121
 122 /***************************************************************************/
 123 /*               eval and verify a scalar expression in VHDL               */
 124 /*                 env list of variables with their values                 */
 125 /***************************************************************************/
 126 extern int Verif_Exp_VHDL(tree_list *tree, ptype_list *env)
 127 {
 128   int i,ope,ope2;
 129   if (!tree) {
 130     avt_errmsg(GNS_ERRMSG, "004", AVT_FATAL, 209);
 131 //    fprintf(stderr,"Verif_Exp_VHDL: NULL pointer\n");
 132     EXIT(1);
 133   }
 134   switch (TOKEN(tree)) {
 135   /*nodes..*/
 136   case GEN_TOKEN_NODE:
 137       return Verif_Exp_VHDL(tree->DATA,env);
 138       break;
 139   case '+':
 140       return Verif_Exp_VHDL(tree->NEXT,env)+Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 141       break;
 142   case '-':
 143       return Verif_Exp_VHDL(tree->NEXT,env)-Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 144       break;
 145   case '*':
 146       return Verif_Exp_VHDL(tree->NEXT,env)*Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 147       break;
 148   case '/':
 149       ope=Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 150       if (ope==0) {
 151          /*here LINE represents where the 2nd operand ends*/
 152     avt_errmsg(GNS_ERRMSG, "136", AVT_FATAL, FILE_NAME(tree),LINE(tree));
 153     //     fprintf(stderr,"%s:%d: division by zero could appear\n",FILE_NAME(tree),LINE(tree));
 154          Inc_Error();
 155          return Verif_Exp_VHDL(tree->NEXT,env);
 156       }
 157       return Verif_Exp_VHDL(tree->NEXT,env)/ope;
 158       break;
 159   case '%':
 160       ope=Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 161       if (ope==0) {
 162          /*here LINE represents where the 2nd operand ends*/
 163     avt_errmsg(GNS_ERRMSG, "136", AVT_FATAL, FILE_NAME(tree),LINE(tree));
 164     //     fprintf(stderr,"%s:%d: division by zero could appear\n",FILE_NAME(tree),LINE(tree));
 165          Inc_Error();
 166          return Verif_Exp_VHDL(tree->NEXT,env);
 167       }
 168       return Verif_Exp_VHDL(tree->NEXT,env)%ope;
 169       break;
 170   case GEN_TOKEN_MOD:
 171       ope=Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 172       if (ope==0) {
 173          /*here LINE represents where the 2nd operand ends*/
 174     avt_errmsg(GNS_ERRMSG, "136", AVT_FATAL, FILE_NAME(tree),LINE(tree));
 175     //     fprintf(stderr,"%s:%d: division by zero could appear\n",FILE_NAME(tree),LINE(tree));
 176          Inc_Error();
 177          return Verif_Exp_VHDL(tree->NEXT,env);
 178       }
 179       ope=Verif_Exp_VHDL(tree->NEXT,env)%ope;
 180       return ope<0?-ope:ope;
 181       break;
 182   case GEN_TOKEN_POW:
 183       ope2=1;
 184       ope=Verif_Exp_VHDL(tree->NEXT,env);
 185       for (i=Verif_Exp_VHDL(tree->NEXT->NEXT,env);i>0;i--) ope2*=ope;
 186       return ope2;
 187       break;
 188   case GEN_TOKEN_OPPOSITE:
 189       return -Verif_Exp_VHDL(tree->NEXT,env);
 190       break;
 191   case GEN_TOKEN_DIGIT:
 192       return (int)(long)tree->DATA;
 193       break;
 194   case GEN_TOKEN_IDENT:
 195       ope=fetch_value(tree,env); /*check if exists and take the value*/
 196       return ope;
 197       break;
 198   default:
 199     Error_Tree("Verif_Exp_VHDL",tree);
 200     EXIT(1); return 0;
 201   }
 202 }
 203
 204
 205 /***************************************************************************/
 206 /*            Verify and Evaluate a boolean expression in VHDL             */
 207 /*                 env list of variables with their values                 */
 208 /***************************************************************************/
 209 extern int Verif_Bool_VHDL(tree, env)
 210    tree_list *tree;
 211    ptype_list *env;
 212 {
 213   if (!tree) {
 214     avt_errmsg(GNS_ERRMSG, "004", AVT_FATAL, 210);
 215 //    fprintf(stderr,"Verif_Bool_VHDL: NULL pointer\n");
 216     EXIT(1);
 217   }
 218   switch (TOKEN(tree)) {
 219   /*nodes..*/
 220   case GEN_TOKEN_NODE:
 221       return Verif_Bool_VHDL(tree->DATA,env);
 222       break;
 223   case GNS_TOKEN_AND:
 224       return
 225       Verif_Bool_VHDL(tree->NEXT,env)&&Verif_Bool_VHDL(tree->NEXT->NEXT,env);
 226       break;
 227   case GEN_TOKEN_OR:
 228       return
 229       Verif_Bool_VHDL(tree->NEXT,env)||Verif_Bool_VHDL(tree->NEXT->NEXT,env);
 230       break;
 231   case GEN_TOKEN_XOR:
 232       return 0x1&&
 233       (Verif_Bool_VHDL(tree->NEXT,env)^Verif_Bool_VHDL(tree->NEXT->NEXT,env));
 234       break;
 235   case GEN_TOKEN_NOT:
 236       return !Verif_Bool_VHDL(tree->NEXT,env);
 237       break;
 238   case '<':
 239       return
 240       Verif_Exp_VHDL(tree->NEXT,env)<Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 241       break;
 242   case '>':
 243       return
 244       Verif_Exp_VHDL(tree->NEXT,env)>Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 245       break;
 246   case GEN_TOKEN_EG:
 247       return
 248       Verif_Exp_VHDL(tree->NEXT,env)==Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 249       break;
 250   case GEN_TOKEN_SUPEG:
 251       return
 252       Verif_Exp_VHDL(tree->NEXT,env)>=Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 253       break;
 254   case GEN_TOKEN_INFEG:
 255       return
 256       Verif_Exp_VHDL(tree->NEXT,env)<=Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 257       break;
 258   case GEN_TOKEN_NOTEG:
 259       return
 260       Verif_Exp_VHDL(tree->NEXT,env)!=Verif_Exp_VHDL(tree->NEXT->NEXT,env);
 261       break;
 262   default:
 263     Error_Tree("Verif_Bool_VHDL",tree);
 264     EXIT(1); return 0;
 265   }
 266 }
 267
 268
 269