1 /****************************************************************************/
3 /* Chaine de CAO & VLSI Alliance */
5 /* Produit : GENIUS v1.00 */
6 /* Fichier : gen_verif_exp_VHDL.h */
8 /* Auteur(s) : Francois DONNET le : 10/06/1999 */
10 /* (c) copyright 1999 Laboratoire MASI equipe CAO & VLSI */
11 /* Tous droits reserves */
12 /* Support : e-mail alliance-support@asim.lip6.fr */
15 /****************************************************************************/
19 /***************************************************************************/
20 /* Control the expression of FOR in VHDL for later searching */
21 /* env list of variables with their values */
22 /***************************************************************************/
23 extern int Verif_HighBound_FOR(tree_list
*tree
, ptype_list
*env
);
26 /***************************************************************************/
27 /* eval and verify a scalar expression in VHDL */
28 /* env list of variables with their values */
29 /***************************************************************************/
30 extern int Verif_Exp_VHDL(tree_list
*tree
, ptype_list
*env
);
32 /***************************************************************************/
33 /* Verify and Evaluate a boolean expression in VHDL */
34 /* env list of variables with their values */
35 /***************************************************************************/
36 extern int Verif_Bool_VHDL(tree_list
*tree
, ptype_list
*env
);