dmi_dtm_ecp5.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.math_real.all;
   4
   5 library work;
   6 use work.wishbone_types.all;
   7
   8 entity dmi_dtm is
   9     generic(ABITS : INTEGER:=8;
  10             DBITS : INTEGER:=64);
  11
  12     port(sys_clk   : in std_ulogic;
  13          sys_reset : in std_ulogic;
  14          dmi_addr  : out std_ulogic_vector(ABITS - 1 downto 0);
  15          dmi_din   : in std_ulogic_vector(DBITS - 1 downto 0);
  16          dmi_dout  : out std_ulogic_vector(DBITS - 1 downto 0);
  17          dmi_req   : out std_ulogic;
  18          dmi_wr    : out std_ulogic;
  19          dmi_ack   : in std_ulogic
  20 --         dmi_err : in std_ulogic TODO: Add error response
  21          );
  22 end entity dmi_dtm;
  23
  24 architecture behaviour of dmi_dtm is
  25     -- Signals coming out of the JTAGG block
  26     signal jtag_reset_n : std_ulogic;
  27     signal tdi        : std_ulogic;
  28     signal tdo        : std_ulogic;
  29     signal tck        : std_ulogic;
  30     signal jce1       : std_ulogic;
  31     signal jshift     : std_ulogic;
  32     signal update     : std_ulogic;
  33
  34     -- signals to match dmi_dtb_xilinx
  35     signal jtag_reset : std_ulogic;
  36     signal capture    : std_ulogic;
  37     signal jtag_clk   : std_ulogic;
  38     signal sel        : std_ulogic;
  39     signal shift      : std_ulogic;
  40
  41     -- delays
  42     signal jce1_d     : std_ulogic;
  43     constant TCK_DELAY : INTEGER := 8;
  44     signal tck_d : std_ulogic_vector(TCK_DELAY+1 downto 1);
  45
  46     -- ** JTAG clock domain **
  47
  48     -- Shift register
  49     signal shiftr : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
  50
  51     -- Latched request
  52     signal request : std_ulogic_vector(ABITS + DBITS + 1 downto 0);
  53
  54     -- A request is present
  55     signal jtag_req : std_ulogic;
  56
  57     -- Synchronizer for jtag_rsp (sys clk -> jtag_clk)
  58     signal dmi_ack_0 : std_ulogic;
  59     signal dmi_ack_1 : std_ulogic;
  60
  61     -- ** sys clock domain **
  62
  63     -- Synchronizer for jtag_req (jtag clk -> sys clk)
  64     signal jtag_req_0 : std_ulogic;
  65     signal jtag_req_1 : std_ulogic;
  66
  67     -- ** combination signals
  68     signal jtag_bsy : std_ulogic;
  69     signal op_valid : std_ulogic;
  70     signal rsp_op   : std_ulogic_vector(1 downto 0);
  71
  72     -- ** Constants **
  73     constant DMI_REQ_NOP : std_ulogic_vector(1 downto 0) := "00";
  74     constant DMI_REQ_RD  : std_ulogic_vector(1 downto 0) := "01";
  75     constant DMI_REQ_WR  : std_ulogic_vector(1 downto 0) := "10";
  76     constant DMI_RSP_OK  : std_ulogic_vector(1 downto 0) := "00";
  77     constant DMI_RSP_BSY : std_ulogic_vector(1 downto 0) := "11";
  78
  79     attribute ASYNC_REG : string;
  80     attribute ASYNC_REG of jtag_req_0: signal is "TRUE";
  81     attribute ASYNC_REG of jtag_req_1: signal is "TRUE";
  82     attribute ASYNC_REG of dmi_ack_0: signal is "TRUE";
  83     attribute ASYNC_REG of dmi_ack_1: signal is "TRUE";
  84
  85     -- ECP5 JTAGG
  86     component JTAGG is
  87         generic (
  88             ER1 : string := "ENABLED";
  89             ER2 : string := "ENABLED"
  90         );
  91         port(
  92             JTDO1 : in std_ulogic;
  93             JTDO2 : in std_ulogic;
  94             JTDI : out std_ulogic;
  95             JTCK : out std_ulogic;
  96             JRTI1 : out std_ulogic;
  97             JRTI2 : out std_ulogic;
  98             JSHIFT : out std_ulogic;
  99             JUPDATE : out std_ulogic;
 100             JRSTN : out std_ulogic;
 101             JCE1 : out std_ulogic;
 102             JCE2 : out std_ulogic
 103         );
 104     end component;
 105
 106     component LUT4 is
 107         generic (
 108             INIT : std_logic_vector
 109         );
 110         port(
 111           A : in STD_ULOGIC;
 112           B : in STD_ULOGIC;
 113           C : in STD_ULOGIC;
 114           D : in STD_ULOGIC;
 115           Z : out STD_ULOGIC
 116         );
 117     end component;
 118
 119 begin
 120
 121     jtag: JTAGG
 122         generic map(
 123             ER2 => "DISABLED"
 124         )
 125         port map (
 126             JTDO1 => tdo,
 127             JTDO2 => '0',
 128             JTDI => tdi,
 129             JTCK => tck,
 130             JRTI1 => open,
 131             JRTI2 => open,
 132             JSHIFT => jshift,
 133             JUPDATE => update,
 134             JRSTN => jtag_reset_n,
 135             JCE1 => jce1,
 136             JCE2 => open
 137         );
 138
 139     -- JRTI1 looks like it could be connected to SEL, but
 140     -- in practise JRTI1 is only high briefly, not for the duration
 141     -- of the transmission. possibly mw_debug could be modified.
 142     -- The ecp5 is probably the only jtag device anyway.
 143     sel <= '1';
 144
 145     -- TDI needs to align with TCK, we use LUT delays here.
 146     -- From https://github.com/enjoy-digital/litex/pull/1087
 147     tck_d(1) <= tck;
 148     del: for i in 1 to TCK_DELAY generate
 149         attribute keep : boolean;
 150         attribute keep of l: label is true;
 151     begin
 152         l: LUT4
 153             generic map(
 154                 INIT => b"0000_0000_0000_0010"
 155             )
 156             port map (
 157                 A => tck_d(i),
 158                 B => '0', C => '0', D => '0',
 159                 Z => tck_d(i+1)
 160             );
 161     end generate;
 162     jtag_clk <= tck_d(TCK_DELAY+1);
 163
 164     -- capture signal
 165     jce1_sync : process(jtag_clk)
 166     begin
 167         if rising_edge(jtag_clk) then
 168             jce1_d <= jce1;
 169             capture <= jce1 and not jce1_d;
 170         end if;
 171     end process;
 172
 173     -- latch the shift signal, otherwise
 174     -- we miss the last shift in
 175     -- (maybe because we are delaying tck?)
 176     shift_sync : process(jtag_clk)
 177     begin
 178         if (sys_reset = '1') then
 179             shift <= '0';
 180         elsif rising_edge(jtag_clk) then
 181             shift <= jshift;
 182         end if;
 183     end process;
 184
 185     jtag_reset <= not jtag_reset_n;
 186
 187     -- dmi_req synchronization
 188     dmi_req_sync : process(sys_clk)
 189     begin
 190         -- sys_reset is synchronous
 191         if rising_edge(sys_clk) then
 192             if (sys_reset = '1') then
 193                 jtag_req_0 <= '0';
 194                 jtag_req_1 <= '0';
 195             else
 196                 jtag_req_0 <= jtag_req;
 197                 jtag_req_1 <= jtag_req_0;
 198             end if;
 199         end if;
 200     end process;
 201     dmi_req <= jtag_req_1;
 202
 203     -- dmi_ack synchronization
 204     dmi_ack_sync: process(jtag_clk, jtag_reset)
 205     begin
 206         -- jtag_reset is async (see comments)
 207         if jtag_reset = '1' then
 208             dmi_ack_0 <= '0';
 209             dmi_ack_1 <= '0';
 210         elsif rising_edge(jtag_clk) then
 211             dmi_ack_0 <= dmi_ack;
 212             dmi_ack_1 <= dmi_ack_0;
 213         end if;
 214     end process;
 215
 216     -- jtag_bsy indicates whether we can start a new request, we can when
 217     -- we aren't already processing one (jtag_req) and the synchronized ack
 218     -- of the previous one is 0.
 219     --
 220     jtag_bsy <= jtag_req or dmi_ack_1;
 221
 222     -- decode request type in shift register
 223     with shiftr(1 downto 0) select op_valid <=
 224         '1' when DMI_REQ_RD,
 225         '1' when DMI_REQ_WR,
 226         '0' when others;
 227
 228     -- encode response op
 229     rsp_op <= DMI_RSP_BSY when jtag_bsy = '1' else DMI_RSP_OK;
 230
 231     -- Some DMI out signals are directly driven from the request register
 232     dmi_addr <= request(ABITS + DBITS + 1 downto DBITS + 2);
 233     dmi_dout <= request(DBITS + 1 downto 2);
 234     dmi_wr   <= '1' when request(1 downto 0) = DMI_REQ_WR else '0';
 235
 236     -- TDO is wired to shift register bit 0
 237     tdo <= shiftr(0);
 238
 239     -- Main state machine. Handles shift registers, request latch and
 240     -- jtag_req latch. Could be split into 3 processes but it's probably
 241     -- not worthwhile.
 242     --
 243     shifter: process(jtag_clk, jtag_reset, sys_reset)
 244     begin
 245         if jtag_reset = '1' or sys_reset = '1' then
 246             shiftr <= (others => '0');
 247             jtag_req <= '0';
 248             request <= (others => '0');
 249         elsif rising_edge(jtag_clk) then
 250
 251             -- Handle jtag "commands" when sel is 1
 252             if sel = '1' then
 253                 -- Shift state, rotate the register
 254                 if shift = '1' then
 255                     shiftr <= tdi & shiftr(ABITS + DBITS + 1 downto 1);
 256                 end if;
 257
 258                 -- Update state (trigger)
 259                 --
 260                 -- Latch the request if we aren't already processing one and
 261                 -- it has a valid command opcode.
 262                 --
 263                     if update = '1' and op_valid = '1' then
 264                     if jtag_bsy = '0' then
 265                         request <= shiftr;
 266                         jtag_req <= '1';
 267                     end if;
 268                     -- Set the shift register "op" to "busy". This will prevent
 269                     -- us from re-starting the command on the next update if
 270                     -- the command completes before that.
 271                     shiftr(1 downto 0) <= DMI_RSP_BSY;
 272                 end if;
 273
 274                 -- Request completion.
 275                 --
 276                 -- Capture the response data for reads and clear request flag.
 277                 --
 278                 -- Note: We clear req (and thus dmi_req) here which relies on tck
 279                 -- ticking and sel set. This means we are stuck with dmi_req up if
 280                 -- the jtag interface stops. Slaves must be resilient to this.
 281                 --
 282                 if jtag_req = '1' and dmi_ack_1 = '1' then
 283                     jtag_req <= '0';
 284                     if request(1 downto 0) = DMI_REQ_RD then
 285                         request(DBITS + 1 downto 2) <= dmi_din;
 286                     end if;
 287                 end if;
 288
 289                 -- Capture state, grab latch content with updated status
 290                 if capture = '1' then
 291                     shiftr <= request(ABITS + DBITS + 1 downto 2) & rsp_op;
 292                 end if;
 293
 294             end if;
 295         end if;
 296     end process;
 297 end architecture behaviour;
 298