dram_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity dram_tb is
  10     generic (
  11         DRAM_INIT_FILE : string  := "";
  12         DRAM_INIT_SIZE : natural := 0
  13         );
  14 end dram_tb;
  15
  16 architecture behave of dram_tb is
  17     signal clk, rst: std_logic;
  18     signal clk_in, soc_rst : std_ulogic;
  19
  20     -- testbench signals
  21     constant clk_period : time := 10 ns;
  22
  23     -- Sim DRAM
  24     signal wb_in : wishbone_master_out;
  25     signal wb_out : wishbone_slave_out;
  26     signal wb_ctrl_in : wb_io_master_out;
  27
  28     subtype addr_t is std_ulogic_vector(wb_in.adr'left downto 0);
  29     subtype data_t is std_ulogic_vector(wb_in.dat'left downto 0);
  30     subtype sel_t  is std_ulogic_vector(wb_in.sel'left downto 0);
  31
  32     -- Counter for acks
  33     signal acks : integer := 0;
  34     signal reset_acks : std_ulogic;
  35
  36     -- Read data fifo
  37     signal rd_ready : std_ulogic := '0';
  38     signal rd_valid : std_ulogic;
  39     signal rd_data  : data_t;
  40 begin
  41
  42     dram: entity work.litedram_wrapper
  43         generic map(
  44             DRAM_ABITS => 24,
  45             DRAM_ALINES => 1,
  46             DRAM_DLINES => 16,
  47             DRAM_PORT_WIDTH => 128,
  48             PAYLOAD_FILE => DRAM_INIT_FILE,
  49             PAYLOAD_SIZE => DRAM_INIT_SIZE
  50             )
  51         port map(
  52             clk_in              => clk_in,
  53             rst                 => rst,
  54             system_clk          => clk,
  55             system_reset        => soc_rst,
  56             core_alt_reset      => open,
  57             pll_locked          => open,
  58
  59             wb_in               => wb_in,
  60             wb_out              => wb_out,
  61             wb_ctrl_in          => wb_ctrl_in,
  62             wb_ctrl_out         => open,
  63             wb_ctrl_is_csr      => '0',
  64             wb_ctrl_is_init     => '0',
  65
  66             init_done           => open,
  67             init_error          => open,
  68
  69             ddram_a             => open,
  70             ddram_ba    => open,
  71             ddram_ras_n => open,
  72             ddram_cas_n => open,
  73             ddram_we_n  => open,
  74             ddram_cs_n  => open,
  75             ddram_dm    => open,
  76             ddram_dq    => open,
  77             ddram_dqs_p => open,
  78             ddram_dqs_n => open,
  79             ddram_clk_p => open,
  80             ddram_clk_n => open,
  81             ddram_cke   => open,
  82             ddram_odt   => open,
  83             ddram_reset_n       => open
  84             );
  85
  86     clk_process: process
  87     begin
  88         clk_in <= '0';
  89         wait for clk_period/2;
  90         clk_in <= '1';
  91         wait for clk_period/2;
  92     end process;
  93
  94     rst_process: process
  95     begin
  96         rst <= '1';
  97         wait for 10*clk_period;
  98         rst <= '0';
  99         wait;
 100     end process;
 101
 102     wb_ctrl_in.cyc <= '0';
 103     wb_ctrl_in.stb <= '0';
 104
 105     -- Read data receive queue
 106     data_queue: entity work.sync_fifo
 107         generic map (
 108             DEPTH => 16,
 109             WIDTH => rd_data'length
 110             )
 111         port map (
 112             clk      => clk,
 113             reset    => soc_rst or reset_acks,
 114             rd_ready => rd_ready,
 115             rd_valid => rd_valid,
 116             rd_data  => rd_data,
 117             wr_ready => open,
 118             wr_valid => wb_out.ack,
 119             wr_data  => wb_out.dat
 120             );
 121
 122     recv_acks: process(clk)
 123     begin
 124         if rising_edge(clk) then
 125             if rst = '1' or reset_acks = '1' then
 126                 acks <= 0;
 127             elsif wb_out.ack = '1' then
 128                 acks <= acks + 1;
 129 --                report "WB ACK ! DATA=" & to_hstring(wb_out.dat);
 130             end if;
 131         end if;
 132     end process;
 133
 134     sim: process
 135         procedure wb_write(addr: addr_t; data: data_t; sel: sel_t) is
 136         begin
 137             wb_in.adr <= addr;
 138             wb_in.sel <= sel;
 139             wb_in.dat <= data;
 140             wb_in.we  <= '1';
 141             wb_in.stb <= '1';
 142             wb_in.cyc <= '1';
 143             loop
 144                 wait until rising_edge(clk);
 145                 if wb_out.stall = '0' then
 146                     wb_in.stb <= '0';
 147                     exit;
 148                 end if;
 149             end loop;
 150         end procedure;
 151
 152         procedure wb_read(addr: addr_t) is
 153         begin
 154             wb_in.adr <= addr;
 155             wb_in.sel <= x"ff";
 156             wb_in.we  <= '0';
 157             wb_in.stb <= '1';
 158             wb_in.cyc <= '1';
 159             loop
 160                 wait until rising_edge(clk);
 161                 if wb_out.stall = '0' then
 162                     wb_in.stb <= '0';
 163                     exit;
 164                 end if;
 165             end loop;
 166         end procedure;
 167
 168         procedure wait_acks(count: integer) is
 169         begin
 170             wait until acks = count;
 171             wait until rising_edge(clk);
 172         end procedure;
 173
 174         procedure clr_acks is
 175         begin
 176             reset_acks <= '1';
 177             wait until rising_edge(clk);
 178             reset_acks <= '0';
 179         end procedure;
 180
 181         procedure read_data(data: out data_t) is
 182         begin
 183             assert rd_valid = '1' report "No data to read" severity failure;
 184             rd_ready <= '1';
 185             wait until rising_edge(clk);
 186             rd_ready <= '0';
 187             data := rd_data;
 188         end procedure;
 189
 190         function add_off(a: addr_t; off: integer) return addr_t is
 191         begin
 192             return addr_t(unsigned(a) + off);
 193         end function;
 194
 195         function make_pattern(num : integer) return data_t is
 196             variable r : data_t;
 197             variable t,b : integer;
 198         begin
 199             for i in 0 to (data_t'length/8)-1 loop
 200                 t := (i+1)*8-1;
 201                 b := i*8;
 202                 r(t downto b) := std_ulogic_vector(to_unsigned(num+1, 8));
 203             end loop;
 204             return r;
 205         end function;
 206
 207         procedure check_data(p: data_t) is
 208             variable d : data_t;
 209         begin
 210             read_data(d);
 211             assert d = p report "bad data, want " & to_hstring(p) &
 212                     " got " & to_hstring(d) severity failure;
 213         end procedure;
 214
 215         variable a : addr_t := (others => '0');
 216         variable d : data_t := (others => '0');
 217         variable d1 : data_t := (others => '0');
 218     begin
 219         reset_acks <= '0';
 220         rst <= '1';
 221         wait until rising_edge(clk_in);
 222         wait until rising_edge(clk_in);
 223         wait until rising_edge(clk_in);
 224         wait until rising_edge(clk_in);
 225         wait until rising_edge(clk_in);
 226         rst <= '0';
 227         wait until rising_edge(clk_in);
 228         wait until soc_rst = '0';
 229         wait until rising_edge(clk);
 230
 231         report "Simple write miss...";
 232         clr_acks;
 233         wb_write(a, x"0123456789abcdef", x"ff");
 234         wait_acks(1);
 235
 236         report "Simple read miss...";
 237         clr_acks;
 238         wb_read(a);
 239         wait_acks(1);
 240         read_data(d);
 241         assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure;
 242
 243         report "Simple read hit...";
 244         clr_acks;
 245         wb_read(a);
 246         wait_acks(1);
 247         read_data(d);
 248         assert d = x"0123456789abcdef" report "bad data, got " & to_hstring(d) severity failure;
 249
 250         report "Back to back 4 stores 4 reads on hit...";
 251         clr_acks;
 252         for i in 0 to 3 loop
 253             wb_write(add_off(a, i*8), make_pattern(i), x"ff");
 254         end loop;
 255         for i in 0 to 3 loop
 256             wb_read(add_off(a, i*8));
 257         end loop;
 258         wait_acks(8);
 259         for i in 0 to 7 loop
 260             if i < 4 then
 261                 read_data(d);
 262             else
 263                 check_data(make_pattern(i-4));
 264             end if;
 265         end loop;
 266
 267         report "Back to back 4 stores 4 reads on miss...";
 268         a(10) := '1';
 269         clr_acks;
 270         for i in 0 to 3 loop
 271             wb_write(add_off(a, i*8), make_pattern(i), x"ff");
 272         end loop;
 273         for i in 0 to 3 loop
 274             wb_read(add_off(a, i*8));
 275         end loop;
 276         wait_acks(8);
 277         for i in 0 to 7 loop
 278             if i < 4 then
 279                 read_data(d);
 280             else
 281                 check_data(make_pattern(i-4));
 282             end if;
 283         end loop;
 284
 285         report "Back to back interleaved 4 stores 4 reads on hit...";
 286         a(10) := '1';
 287         clr_acks;
 288         for i in 0 to 3 loop
 289             wb_write(add_off(a, i*8), make_pattern(i), x"ff");
 290             wb_read(add_off(a, i*8));
 291         end loop;
 292         wait_acks(8);
 293         for i in 0 to 3 loop
 294             read_data(d);
 295             check_data(make_pattern(i));
 296         end loop;
 297
 298         report "Pre-fill a line";
 299         a(11) := '1';
 300         clr_acks;
 301         wb_write(add_off(a,  0), x"1111111100000000", x"ff");
 302         wb_write(add_off(a,  8), x"3333333322222222", x"ff");
 303         wb_write(add_off(a, 16), x"5555555544444444", x"ff");
 304         wb_write(add_off(a, 24), x"7777777766666666", x"ff");
 305         wb_write(add_off(a, 32), x"9999999988888888", x"ff");
 306         wb_write(add_off(a, 40), x"bbbbbbbbaaaaaaaa", x"ff");
 307         wb_write(add_off(a, 48), x"ddddddddcccccccc", x"ff");
 308         wb_write(add_off(a, 56), x"ffffffffeeeeeeee", x"ff");
 309         wb_write(add_off(a, 64), x"1111111100000000", x"ff");
 310         wb_write(add_off(a, 72), x"3333333322222222", x"ff");
 311         wb_write(add_off(a, 80), x"5555555544444444", x"ff");
 312         wb_write(add_off(a, 88), x"7777777766666666", x"ff");
 313         wb_write(add_off(a, 96), x"9999999988888888", x"ff");
 314         wb_write(add_off(a,104), x"bbbbbbbbaaaaaaaa", x"ff");
 315         wb_write(add_off(a,112), x"ddddddddcccccccc", x"ff");
 316         wb_write(add_off(a,120), x"ffffffffeeeeeeee", x"ff");
 317         wait_acks(16);
 318
 319         report "Scattered from middle of line...";
 320         clr_acks;
 321         wb_read(add_off(a,24));
 322         wb_read(add_off(a,32));
 323         wb_read(add_off(a, 0));
 324         wb_read(add_off(a,16));
 325         wait_acks(4);
 326         read_data(d);
 327         assert d = x"7777777766666666" report "bad data (24), got " & to_hstring(d) severity failure;
 328         read_data(d);
 329         assert d = x"9999999988888888" report "bad data (32), got " & to_hstring(d) severity failure;
 330         read_data(d);
 331         assert d = x"1111111100000000" report "bad data (0), got " & to_hstring(d) severity failure;
 332         read_data(d);
 333         assert d = x"5555555544444444" report "bad data (16), got " & to_hstring(d) severity failure;
 334
 335         std.env.finish;
 336     end process;
 337 end architecture;