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  12 From: bugzilla-daemon@libre-riscv.org
  13 To: libre-riscv-dev@lists.libre-riscv.org
  14 Date: Fri, 13 Mar 2020 12:56:08 +0000
  15 X-Bugzilla-Reason: CC
  16 X-Bugzilla-Type: new
  17 X-Bugzilla-Watch-Reason: None
  18 X-Bugzilla-Product: Libre Shakti M-Class
  19 X-Bugzilla-Component: Specification
  20 X-Bugzilla-Version: unspecified
  21 X-Bugzilla-Keywords:
  22 X-Bugzilla-Severity: enhancement
  23 X-Bugzilla-Who: lkcl@lkcl.net
  24 X-Bugzilla-Status: CONFIRMED
  25 X-Bugzilla-Resolution:
  26 X-Bugzilla-Priority: ---
  27 X-Bugzilla-Assigned-To: lkcl@lkcl.net
  28 X-Bugzilla-Flags:
  29 X-Bugzilla-Changed-Fields: bug_id short_desc product version rep_platform
  30  op_sys bug_status bug_severity priority component assigned_to reporter cc
  31  cf_nlnet_milestone
  32 Message-ID: <bug-240-13@http.bugs.libre-riscv.org/>
  33 X-Bugzilla-URL: http://bugs.libre-riscv.org/
  34 Auto-Submitted: auto-generated
  35 MIME-Version: 1.0
  36 Subject: [libre-riscv-dev] [Bug 240] New: POWER-RISCV ISA switch formal
  37  standard writeup needed
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