examples/headless-ecpix5.py

   1 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2
   3 from nmigen import *
   4 from nmigen.lib.cdc import ResetSynchronizer
   5 from nmigen_soc import wishbone, memory
   6
   7 from lambdasoc.cpu.minerva import MinervaCPU
   8 from lambdasoc.periph.intc import GenericInterruptController
   9 from lambdasoc.periph.serial import AsyncSerialPeripheral
  10 from lambdasoc.periph.sram import SRAMPeripheral
  11 from lambdasoc.periph.timer import TimerPeripheral
  12 from lambdasoc.periph import Peripheral
  13 from lambdasoc.soc.base import SoC
  14
  15 from gram.core import gramCore
  16 from gram.phy.ecp5ddrphy import ECP5DDRPHY
  17 from gram.modules import MT41K256M16
  18 from gram.frontend.wishbone import gramWishbone
  19
  20 from nmigen_boards.ecpix5 import *
  21 from uartbridge import UARTBridge
  22 from crg import *
  23
  24 class DDR3SoC(SoC, Elaboratable):
  25     def __init__(self, *,
  26                  ddrphy_addr, dramcore_addr,
  27                  ddr_addr):
  28         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
  29                                          features={"cti", "bte"})
  30
  31         self.crg = ECPIX5CRG()
  32
  33         self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
  34
  35         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
  36             xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4})
  37         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
  38         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
  39
  40         ddrmodule = MT41K256M16(platform.default_clk_frequency, "1:2")
  41
  42         self.dramcore = DomainRenamer("dramsync")(gramCore(
  43             phy=self.ddrphy,
  44             geom_settings=ddrmodule.geom_settings,
  45             timing_settings=ddrmodule.timing_settings,
  46             clk_freq=platform.default_clk_frequency))
  47         self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
  48
  49         self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
  50         self._decoder.add(self.drambone.bus, addr=ddr_addr)
  51
  52         self.memory_map = self._decoder.bus.memory_map
  53
  54         self.clk_freq = platform.default_clk_frequency
  55
  56     def elaborate(self, platform):
  57         m = Module()
  58
  59         m.submodules.sysclk = self.crg
  60
  61         m.submodules.ub = self.ub
  62
  63         m.submodules.decoder = self._decoder
  64         m.submodules.ddrphy = self.ddrphy
  65         m.submodules.dramcore = self.dramcore
  66         m.submodules.drambone = self.drambone
  67
  68         m.d.comb += [
  69             self.ub.bus.connect(self._decoder.bus),
  70         ]
  71
  72         return m
  73
  74
  75 if __name__ == "__main__":
  76     platform = ECPIX585Platform()
  77
  78     soc = DDR3SoC(ddrphy_addr=0x00008000, dramcore_addr=0x00009000,
  79         ddr_addr=0x10000000)
  80
  81     soc.build(do_build=True)
  82     platform.build(soc, do_program=True)