execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40         bypass_data : out bypass_data_t;
  41         bypass_cr_data : out cr_bypass_data_t;
  42
  43         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  44
  45         icache_inval : out std_ulogic;
  46         terminate_out : out std_ulogic;
  47
  48         log_out : out std_ulogic_vector(14 downto 0);
  49         log_rd_addr : out std_ulogic_vector(31 downto 0);
  50         log_rd_data : in std_ulogic_vector(63 downto 0);
  51         log_wr_addr : in std_ulogic_vector(31 downto 0)
  52         );
  53 end entity execute1;
  54
  55 architecture behaviour of execute1 is
  56     type reg_type is record
  57         e : Execute1ToWritebackType;
  58         cur_instr : Decode2ToExecute1Type;
  59         busy: std_ulogic;
  60         terminate: std_ulogic;
  61         fp_exception_next : std_ulogic;
  62         trace_next : std_ulogic;
  63         prev_op : insn_type_t;
  64         next_lr : std_ulogic_vector(63 downto 0);
  65         br_taken : std_ulogic;
  66         mul_in_progress : std_ulogic;
  67         mul_finish : std_ulogic;
  68         div_in_progress : std_ulogic;
  69         cntz_in_progress : std_ulogic;
  70         last_nia : std_ulogic_vector(63 downto 0);
  71         redirect : std_ulogic;
  72         abs_br : std_ulogic;
  73         taken_br : std_ulogic;
  74         br_last : std_ulogic;
  75         do_intr : std_ulogic;
  76         vector : integer range 0 to 16#fff#;
  77         br_offset : std_ulogic_vector(63 downto 0);
  78         redir_mode : std_ulogic_vector(3 downto 0);
  79         log_addr_spr : std_ulogic_vector(31 downto 0);
  80     end record;
  81     constant reg_type_init : reg_type :=
  82         (e => Execute1ToWritebackInit,
  83          cur_instr => Decode2ToExecute1Init,
  84          busy => '0', terminate => '0',
  85          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL, br_taken => '0',
  86          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  87          next_lr => (others => '0'), last_nia => (others => '0'),
  88          redirect => '0', abs_br => '0', taken_br => '0', br_last => '0', do_intr => '0', vector => 0,
  89          br_offset => (others => '0'), redir_mode => "0000",
  90          others => (others => '0'));
  91
  92     signal r, rin : reg_type;
  93
  94     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  95     signal cr_in : std_ulogic_vector(31 downto 0);
  96     signal xerc_in : xer_common_t;
  97
  98     signal valid_in : std_ulogic;
  99     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
 100     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
 101     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
 102     signal rot_sign_ext: std_ulogic;
 103     signal rotator_result: std_ulogic_vector(63 downto 0);
 104     signal rotator_carry: std_ulogic;
 105     signal logical_result: std_ulogic_vector(63 downto 0);
 106     signal countzero_result: std_ulogic_vector(63 downto 0);
 107     signal alu_result: std_ulogic_vector(63 downto 0);
 108     signal adder_result: std_ulogic_vector(63 downto 0);
 109     signal misc_result: std_ulogic_vector(63 downto 0);
 110     signal muldiv_result: std_ulogic_vector(63 downto 0);
 111     signal spr_result: std_ulogic_vector(63 downto 0);
 112     signal result_mux_sel: std_ulogic_vector(2 downto 0);
 113     signal sub_mux_sel: std_ulogic_vector(2 downto 0);
 114     signal next_nia : std_ulogic_vector(63 downto 0);
 115     signal current: Decode2ToExecute1Type;
 116
 117     signal carry_32 : std_ulogic;
 118     signal carry_64 : std_ulogic;
 119     signal overflow_32 : std_ulogic;
 120     signal overflow_64 : std_ulogic;
 121
 122     signal trapval : std_ulogic_vector(4 downto 0);
 123
 124     signal write_cr_mask : std_ulogic_vector(7 downto 0);
 125     signal write_cr_data : std_ulogic_vector(31 downto 0);
 126
 127     -- multiply signals
 128     signal x_to_multiply: MultiplyInputType;
 129     signal multiply_to_x: MultiplyOutputType;
 130
 131     -- divider signals
 132     signal x_to_divider: Execute1ToDividerType;
 133     signal divider_to_x: DividerToExecute1Type;
 134
 135     -- random number generator signals
 136     signal random_raw  : std_ulogic_vector(63 downto 0);
 137     signal random_cond : std_ulogic_vector(63 downto 0);
 138     signal random_err  : std_ulogic;
 139
 140     -- signals for logging
 141     signal exception_log : std_ulogic;
 142     signal irq_valid_log : std_ulogic;
 143
 144     type privilege_level is (USER, SUPER);
 145     type op_privilege_array is array(insn_type_t) of privilege_level;
 146     constant op_privilege: op_privilege_array := (
 147         OP_ATTN => SUPER,
 148         OP_MFMSR => SUPER,
 149         OP_MTMSRD => SUPER,
 150         OP_RFID => SUPER,
 151         OP_TLBIE => SUPER,
 152         others => USER
 153         );
 154
 155     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 156         return boolean is
 157     begin
 158         if op_privilege(op) = SUPER then
 159             return true;
 160         elsif op = OP_MFSPR or op = OP_MTSPR then
 161             return insn(20) = '1';
 162         else
 163             return false;
 164         end if;
 165     end;
 166
 167     procedure set_carry(e: inout Execute1ToWritebackType;
 168                         carry32 : in std_ulogic;
 169                         carry : in std_ulogic) is
 170     begin
 171         e.xerc.ca32 := carry32;
 172         e.xerc.ca := carry;
 173     end;
 174
 175     procedure set_ov(e: inout Execute1ToWritebackType;
 176                      ov   : in std_ulogic;
 177                      ov32 : in std_ulogic) is
 178     begin
 179         e.xerc.ov32 := ov32;
 180         e.xerc.ov := ov;
 181         if ov = '1' then
 182             e.xerc.so := '1';
 183         end if;
 184     end;
 185
 186     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 187                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 188     begin
 189         return (ca xor msb_r) and not (msb_a xor msb_b);
 190     end;
 191
 192     function decode_input_carry(ic : carry_in_t;
 193                                 xerc : xer_common_t) return std_ulogic is
 194     begin
 195         case ic is
 196         when ZERO =>
 197             return '0';
 198         when CA =>
 199             return xerc.ca;
 200         when OV =>
 201             return xerc.ov;
 202         when ONE =>
 203             return '1';
 204         end case;
 205     end;
 206
 207     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 208         return std_ulogic_vector is
 209         variable msr_out: std_ulogic_vector(63 downto 0);
 210     begin
 211         -- ISA says this:
 212         --  Defined MSR bits are classified as either full func-
 213         --  tion or partial function. Full function MSR bits are
 214         --  saved in SRR1 or HSRR1 when an interrupt other
 215         --  than a System Call Vectored interrupt occurs and
 216         --  restored by rfscv, rfid, or hrfid, while partial func-
 217         --  tion MSR bits are not saved or restored.
 218         --  Full function MSR bits lie in the range 0:32, 37:41, and
 219         --  48:63, and partial function MSR bits lie in the range
 220         --  33:36 and 42:47. (Note this is IBM bit numbering).
 221         msr_out := (others => '0');
 222         msr_out(63 downto 31) := msr(63 downto 31);
 223         msr_out(26 downto 22) := msr(26 downto 22);
 224         msr_out(15 downto 0)  := msr(15 downto 0);
 225         return msr_out;
 226     end;
 227
 228     -- Tell vivado to keep the hierarchy for the random module so that the
 229     -- net names in the xdc file match.
 230     attribute keep_hierarchy : string;
 231     attribute keep_hierarchy of random_0 : label is "yes";
 232
 233 begin
 234
 235     rotator_0: entity work.rotator
 236         port map (
 237             rs => c_in,
 238             ra => a_in,
 239             shift => b_in(6 downto 0),
 240             insn => e_in.insn,
 241             is_32bit => e_in.is_32bit,
 242             right_shift => right_shift,
 243             arith => e_in.is_signed,
 244             clear_left => rot_clear_left,
 245             clear_right => rot_clear_right,
 246             sign_ext_rs => rot_sign_ext,
 247             result => rotator_result,
 248             carry_out => rotator_carry
 249             );
 250
 251     logical_0: entity work.logical
 252         port map (
 253             rs => c_in,
 254             rb => b_in,
 255             op => e_in.insn_type,
 256             invert_in => e_in.invert_a,
 257             invert_out => e_in.invert_out,
 258             result => logical_result,
 259             datalen => e_in.data_len
 260             );
 261
 262     countzero_0: entity work.zero_counter
 263         port map (
 264             clk => clk,
 265             rs => c_in,
 266             count_right => e_in.insn(10),
 267             is_32bit => e_in.is_32bit,
 268             result => countzero_result
 269             );
 270
 271     multiply_0: entity work.multiply
 272         port map (
 273             clk => clk,
 274             m_in => x_to_multiply,
 275             m_out => multiply_to_x
 276             );
 277
 278     divider_0: entity work.divider
 279         port map (
 280             clk => clk,
 281             rst => rst,
 282             d_in => x_to_divider,
 283             d_out => divider_to_x
 284             );
 285
 286     random_0: entity work.random
 287         port map (
 288             clk => clk,
 289             data => random_cond,
 290             raw => random_raw,
 291             err => random_err
 292             );
 293
 294     dbg_msr_out <= ctrl.msr;
 295     log_rd_addr <= r.log_addr_spr;
 296
 297     a_in <= e_in.read_data1;
 298     b_in <= e_in.read_data2;
 299     c_in <= e_in.read_data3;
 300     cr_in <= e_in.cr;
 301
 302     -- XER forwarding. To avoid having to track XER hazards, we use
 303     -- the previously latched value.  Since the XER common bits
 304     -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 305     -- handled here, we can just forward the result being sent to
 306     -- writeback.
 307     xerc_in <= r.e.xerc when r.e.write_xerc_enable = '1' or r.busy = '1' else e_in.xerc;
 308
 309     busy_out <= l_in.busy or r.busy or fp_in.busy;
 310     valid_in <= e_in.valid and not busy_out;
 311
 312     terminate_out <= r.terminate;
 313
 314     current <= e_in when r.busy = '0' else r.cur_instr;
 315
 316     -- Result mux
 317     with current.result_sel select alu_result <=
 318         adder_result       when "000",
 319         logical_result     when "001",
 320         rotator_result     when "010",
 321         muldiv_result      when "011",
 322         countzero_result   when "100",
 323         spr_result         when "101",
 324         next_nia           when "110",
 325         misc_result        when others;
 326
 327     execute1_0: process(clk)
 328     begin
 329         if rising_edge(clk) then
 330             if rst = '1' then
 331                 r <= reg_type_init;
 332                 ctrl.tb <= (others => '0');
 333                 ctrl.dec <= (others => '0');
 334                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 335                 ctrl.irq_state <= WRITE_SRR0;
 336             else
 337                 r <= rin;
 338                 ctrl <= ctrl_tmp;
 339                 if valid_in = '1' then
 340                     report "execute " & to_hstring(e_in.nia) & " op=" & insn_type_t'image(e_in.insn_type) &
 341                         " wr=" & to_hstring(rin.e.write_reg) & " we=" & std_ulogic'image(rin.e.write_enable) &
 342                         " tag=" & integer'image(rin.e.instr_tag.tag) & std_ulogic'image(rin.e.instr_tag.valid);
 343                 end if;
 344             end if;
 345         end if;
 346     end process;
 347
 348     -- Data path for integer instructions
 349     execute1_dp: process(all)
 350         variable a_inv : std_ulogic_vector(63 downto 0);
 351         variable b_or_m1 : std_ulogic_vector(63 downto 0);
 352         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 353         variable sign1, sign2 : std_ulogic;
 354         variable abs1, abs2 : signed(63 downto 0);
 355         variable addend : std_ulogic_vector(127 downto 0);
 356         variable addg6s : std_ulogic_vector(63 downto 0);
 357         variable crbit : integer range 0 to 31;
 358         variable isel_result : std_ulogic_vector(63 downto 0);
 359         variable darn : std_ulogic_vector(63 downto 0);
 360         variable setb_result : std_ulogic_vector(63 downto 0);
 361         variable mfcr_result : std_ulogic_vector(63 downto 0);
 362         variable lo, hi : integer;
 363         variable l : std_ulogic;
 364         variable zerohi, zerolo : std_ulogic;
 365         variable msb_a, msb_b : std_ulogic;
 366         variable a_lt : std_ulogic;
 367         variable a_lt_lo : std_ulogic;
 368         variable a_lt_hi : std_ulogic;
 369         variable newcrf : std_ulogic_vector(3 downto 0);
 370         variable bf, bfa : std_ulogic_vector(2 downto 0);
 371         variable crnum : crnum_t;
 372         variable scrnum : crnum_t;
 373         variable cr_operands : std_ulogic_vector(1 downto 0);
 374         variable crresult : std_ulogic;
 375         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 376         variable btnum : integer range 0 to 3;
 377         variable banum, bbnum : integer range 0 to 31;
 378         variable j : integer;
 379     begin
 380         -- Main adder
 381         if e_in.invert_a = '0' then
 382             a_inv := a_in;
 383         else
 384             a_inv := not a_in;
 385         end if;
 386         if e_in.addm1 = '0' then
 387             b_or_m1 := b_in;
 388         else
 389             b_or_m1 := (others => '1');
 390         end if;
 391         sum_with_carry := ppc_adde(a_inv, b_or_m1,
 392                                    decode_input_carry(e_in.input_carry, xerc_in));
 393         adder_result <= sum_with_carry(63 downto 0);
 394         carry_32 <= sum_with_carry(32) xor a_inv(32) xor b_in(32);
 395         carry_64 <= sum_with_carry(64);
 396         overflow_32 <= calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31));
 397         overflow_64 <= calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63));
 398
 399         -- signals to multiply and divide units
 400         sign1 := '0';
 401         sign2 := '0';
 402         if e_in.is_signed = '1' then
 403             if e_in.is_32bit = '1' then
 404                 sign1 := a_in(31);
 405                 sign2 := b_in(31);
 406             else
 407                 sign1 := a_in(63);
 408                 sign2 := b_in(63);
 409             end if;
 410         end if;
 411         -- take absolute values
 412         if sign1 = '0' then
 413             abs1 := signed(a_in);
 414         else
 415             abs1 := - signed(a_in);
 416         end if;
 417         if sign2 = '0' then
 418             abs2 := signed(b_in);
 419         else
 420             abs2 := - signed(b_in);
 421         end if;
 422
 423         -- Interface to multiply and divide units
 424         x_to_divider.is_signed <= e_in.is_signed;
 425         x_to_divider.is_32bit <= e_in.is_32bit;
 426         x_to_divider.is_extended <= '0';
 427         x_to_divider.is_modulus <= '0';
 428         if e_in.insn_type = OP_MOD then
 429             x_to_divider.is_modulus <= '1';
 430         end if;
 431
 432         addend := (others => '0');
 433         if e_in.insn(26) = '0' then
 434             -- integer multiply-add, major op 4 (if it is a multiply)
 435             addend(63 downto 0) := c_in;
 436             if e_in.is_signed = '1' then
 437                 addend(127 downto 64) := (others => c_in(63));
 438             end if;
 439         end if;
 440         if (sign1 xor sign2) = '1' then
 441             addend := not addend;
 442         end if;
 443
 444         x_to_multiply.is_32bit <= e_in.is_32bit;
 445         x_to_multiply.not_result <= sign1 xor sign2;
 446         x_to_multiply.addend <= addend;
 447         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 448         if e_in.is_32bit = '0' then
 449             -- 64-bit forms
 450             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 451             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 452             if e_in.insn_type = OP_DIVE then
 453                 x_to_divider.is_extended <= '1';
 454             end if;
 455             x_to_divider.dividend <= std_ulogic_vector(abs1);
 456             x_to_divider.divisor <= std_ulogic_vector(abs2);
 457         else
 458             -- 32-bit forms
 459             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 460             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 461             x_to_divider.is_extended <= '0';
 462             if e_in.insn_type = OP_DIVE then   -- extended forms
 463                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 464             else
 465                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 466             end if;
 467             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 468         end if;
 469
 470         case current.sub_select(1 downto 0) is
 471             when "00" =>
 472                 muldiv_result <= multiply_to_x.result(63 downto 0);
 473             when "01" =>
 474                 muldiv_result <= multiply_to_x.result(127 downto 64);
 475             when "10" =>
 476                 muldiv_result <= multiply_to_x.result(63 downto 32) &
 477                                  multiply_to_x.result(63 downto 32);
 478             when others =>
 479                 muldiv_result <= divider_to_x.write_reg_data;
 480         end case;
 481
 482         -- Compute misc_result
 483         case current.sub_select is
 484             when "000" =>
 485                 misc_result <= (others => '0');
 486             when "001" =>
 487                 -- addg6s
 488                 addg6s := (others => '0');
 489                 for i in 0 to 14 loop
 490                     lo := i * 4;
 491                     hi := (i + 1) * 4;
 492                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 493                         addg6s(lo + 3 downto lo) := "0110";
 494                     end if;
 495                 end loop;
 496                 if sum_with_carry(64) = '0' then
 497                     addg6s(63 downto 60) := "0110";
 498                 end if;
 499                 misc_result <= addg6s;
 500             when "010" =>
 501                 -- isel
 502                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 503                 if cr_in(31-crbit) = '1' then
 504                     isel_result := a_in;
 505                 else
 506                     isel_result := b_in;
 507                 end if;
 508                 misc_result <= isel_result;
 509             when "011" =>
 510                 -- darn
 511                 darn := (others => '1');
 512                 if random_err = '0' then
 513                     case e_in.insn(17 downto 16) is
 514                         when "00" =>
 515                             darn := x"00000000" & random_cond(31 downto 0);
 516                         when "10" =>
 517                             darn := random_raw;
 518                         when others =>
 519                             darn := random_cond;
 520                     end case;
 521                 end if;
 522                 misc_result <= darn;
 523             when "100" =>
 524                 -- mfmsr
 525                 misc_result <= ctrl.msr;
 526             when "101" =>
 527                 if e_in.insn(20) = '0' then
 528                     -- mfcr
 529                     mfcr_result := x"00000000" & cr_in;
 530                 else
 531                     -- mfocrf
 532                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 533                     mfcr_result := (others => '0');
 534                     for i in 0 to 7 loop
 535                         lo := (7-i)*4;
 536                         hi := lo + 3;
 537                         if crnum = i then
 538                             mfcr_result(hi downto lo) := cr_in(hi downto lo);
 539                         end if;
 540                     end loop;
 541                 end if;
 542                 misc_result <= mfcr_result;
 543             when "110" =>
 544                 -- setb
 545                 bfa := insn_bfa(e_in.insn);
 546                 crbit := to_integer(unsigned(bfa)) * 4;
 547                 setb_result := (others => '0');
 548                 if cr_in(31 - crbit) = '1' then
 549                     setb_result := (others => '1');
 550                 elsif cr_in(30 - crbit) = '1' then
 551                     setb_result(0) := '1';
 552                 end if;
 553                 misc_result <= setb_result;
 554             when others =>
 555                 misc_result <= (others => '0');
 556         end case;
 557
 558         -- compute comparison results
 559         -- Note, we have done RB - RA, not RA - RB
 560         if e_in.insn_type = OP_CMP then
 561             l := insn_l(e_in.insn);
 562         else
 563             l := not e_in.is_32bit;
 564         end if;
 565         zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 566         zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 567         if zerolo = '1' and (l = '0' or zerohi = '1') then
 568             -- values are equal
 569             trapval <= "00100";
 570         else
 571             a_lt_lo := '0';
 572             a_lt_hi := '0';
 573             if unsigned(a_in(30 downto 0)) < unsigned(b_in(30 downto 0)) then
 574                 a_lt_lo := '1';
 575             end if;
 576             if unsigned(a_in(62 downto 31)) < unsigned(b_in(62 downto 31)) then
 577                 a_lt_hi := '1';
 578             end if;
 579             if l = '1' then
 580                 -- 64-bit comparison
 581                 msb_a := a_in(63);
 582                 msb_b := b_in(63);
 583                 a_lt := a_lt_hi or (zerohi and (a_in(31) xnor b_in(31)) and a_lt_lo);
 584             else
 585                 -- 32-bit comparison
 586                 msb_a := a_in(31);
 587                 msb_b := b_in(31);
 588                 a_lt := a_lt_lo;
 589             end if;
 590             if msb_a /= msb_b then
 591                 -- Comparison is clear from MSB difference.
 592                 -- for signed, 0 is greater; for unsigned, 1 is greater
 593                 trapval <= msb_a & msb_b & '0' & msb_b & msb_a;
 594             else
 595                 -- MSBs are equal, so signed and unsigned comparisons give the
 596                 -- same answer.
 597                 trapval <= a_lt & not a_lt & '0' & a_lt & not a_lt;
 598             end if;
 599         end if;
 600
 601         -- CR result mux
 602         bf := insn_bf(e_in.insn);
 603         crnum := to_integer(unsigned(bf));
 604         newcrf := (others => '0');
 605         case current.sub_select is
 606             when "000" =>
 607                 -- CMP and CMPL instructions
 608                 if e_in.is_signed = '1' then
 609                     newcrf := trapval(4 downto 2) & xerc_in.so;
 610                 else
 611                     newcrf := trapval(1 downto 0) & trapval(2) & xerc_in.so;
 612                 end if;
 613             when "001" =>
 614                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 615             when "010" =>
 616                 newcrf := ppc_cmpeqb(a_in, b_in);
 617             when "011" =>
 618                 if current.insn(1) = '1' then
 619                     -- CR logical instructions
 620                     j := (7 - crnum) * 4;
 621                     newcrf := cr_in(j + 3 downto j);
 622                     bt := insn_bt(e_in.insn);
 623                     ba := insn_ba(e_in.insn);
 624                     bb := insn_bb(e_in.insn);
 625                     btnum := 3 - to_integer(unsigned(bt(1 downto 0)));
 626                     banum := 31 - to_integer(unsigned(ba));
 627                     bbnum := 31 - to_integer(unsigned(bb));
 628                     -- Bits 6-9 of the instruction word give the truth table
 629                     -- of the requested logical operation
 630                     cr_operands := cr_in(banum) & cr_in(bbnum);
 631                     crresult := e_in.insn(6 + to_integer(unsigned(cr_operands)));
 632                     for i in 0 to 3 loop
 633                         if i = btnum then
 634                             newcrf(i) := crresult;
 635                         end if;
 636                     end loop;
 637                 else
 638                     -- MCRF
 639                     bfa := insn_bfa(e_in.insn);
 640                     scrnum := to_integer(unsigned(bfa));
 641                     j := (7 - scrnum) * 4;
 642                     newcrf := cr_in(j + 3 downto j);
 643                 end if;
 644             when "100" =>
 645                 -- MCRXRX
 646                 newcrf := xerc_in.ov & xerc_in.ca & xerc_in.ov32 & xerc_in.ca32;
 647             when others =>
 648         end case;
 649         if current.insn_type = OP_MTCRF then
 650             if e_in.insn(20) = '0' then
 651                 -- mtcrf
 652                 write_cr_mask <= insn_fxm(e_in.insn);
 653             else
 654                 -- mtocrf: We require one hot priority encoding here
 655                 crnum := fxm_to_num(insn_fxm(e_in.insn));
 656                 write_cr_mask <= num_to_fxm(crnum);
 657             end if;
 658             write_cr_data <= c_in(31 downto 0);
 659         else
 660             write_cr_mask <= num_to_fxm(crnum);
 661             write_cr_data <= newcrf & newcrf & newcrf & newcrf &
 662                              newcrf & newcrf & newcrf & newcrf;
 663         end if;
 664
 665     end process;
 666
 667     execute1_1: process(all)
 668         variable v : reg_type;
 669         variable lo, hi : integer;
 670         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 671         variable bo, bi : std_ulogic_vector(4 downto 0);
 672         variable overflow : std_ulogic;
 673         variable lv : Execute1ToLoadstore1Type;
 674         variable irq_valid : std_ulogic;
 675         variable exception : std_ulogic;
 676         variable exception_nextpc : std_ulogic;
 677         variable illegal : std_ulogic;
 678         variable is_branch : std_ulogic;
 679         variable is_direct_branch : std_ulogic;
 680         variable taken_branch : std_ulogic;
 681         variable abs_branch : std_ulogic;
 682         variable spr_val : std_ulogic_vector(63 downto 0);
 683         variable do_trace : std_ulogic;
 684         variable hold_wr_data : std_ulogic;
 685         variable f : Execute1ToFetch1Type;
 686         variable fv : Execute1ToFPUType;
 687     begin
 688         is_branch := '0';
 689         is_direct_branch := '0';
 690         taken_branch := '0';
 691         abs_branch := '0';
 692         hold_wr_data := '0';
 693
 694         v := r;
 695         v.e := Execute1ToWritebackInit;
 696         v.redirect := '0';
 697         v.abs_br := '0';
 698         v.do_intr := '0';
 699         v.vector := 0;
 700         v.br_offset := (others => '0');
 701         v.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
 702                         not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
 703         v.taken_br := '0';
 704         v.br_last := '0';
 705         v.e.xerc := xerc_in;
 706
 707         lv := Execute1ToLoadstore1Init;
 708         fv := Execute1ToFPUInit;
 709
 710         x_to_multiply.valid <= '0';
 711         x_to_divider.valid <= '0';
 712         v.mul_in_progress := '0';
 713         v.div_in_progress := '0';
 714         v.cntz_in_progress := '0';
 715         v.mul_finish := '0';
 716
 717         spr_result <= (others => '0');
 718         spr_val := (others => '0');
 719
 720         ctrl_tmp <= ctrl;
 721         -- FIXME: run at 512MHz not core freq
 722         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 723         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 724
 725         irq_valid := '0';
 726         if ctrl.msr(MSR_EE) = '1' then
 727             if ctrl.dec(63) = '1' then
 728                 v.vector := 16#900#;
 729                 report "IRQ valid: DEC";
 730                 irq_valid := '1';
 731             elsif ext_irq_in = '1' then
 732                 v.vector := 16#500#;
 733                 report "IRQ valid: External";
 734                 irq_valid := '1';
 735             end if;
 736         end if;
 737
 738         v.terminate := '0';
 739         icache_inval <= '0';
 740         v.busy := '0';
 741
 742         -- Next insn adder used in a couple of places
 743         next_nia <= std_ulogic_vector(unsigned(e_in.nia) + 4);
 744
 745         -- rotator control signals
 746         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 747         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 748         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 749         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 750
 751         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 752         ctrl_tmp.irq_state <= WRITE_SRR0;
 753         exception := '0';
 754         illegal := '0';
 755         exception_nextpc := '0';
 756         v.e.exc_write_enable := '0';
 757         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 758         if valid_in = '1' then
 759             v.e.exc_write_data := e_in.nia;
 760             v.last_nia := e_in.nia;
 761         else
 762             v.e.exc_write_data := r.last_nia;
 763         end if;
 764
 765         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 766         v.e.instr_tag := current.instr_tag;
 767
 768         do_trace := valid_in and ctrl.msr(MSR_SE);
 769         if valid_in = '1' then
 770             v.prev_op := e_in.insn_type;
 771         end if;
 772
 773         -- Determine if there is any exception to be taken
 774         -- before/instead of executing this instruction
 775         if valid_in = '1' and e_in.second = '0' then
 776             if HAS_FPU and r.fp_exception_next = '1' then
 777                 -- This is used for FP-type program interrupts that
 778                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 779                 exception := '1';
 780                 v.vector := 16#700#;
 781                 ctrl_tmp.srr1(63 - 43) <= '1';
 782                 ctrl_tmp.srr1(63 - 47) <= '1';
 783             elsif r.trace_next = '1' then
 784                 -- Generate a trace interrupt rather than executing the next instruction
 785                 -- or taking any asynchronous interrupt
 786                 exception := '1';
 787                 v.vector := 16#d00#;
 788                 ctrl_tmp.srr1(63 - 33) <= '1';
 789                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 790                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 791                     ctrl_tmp.srr1(63 - 35) <= '1';
 792                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 793                     ctrl_tmp.srr1(63 - 36) <= '1';
 794                 end if;
 795
 796             elsif irq_valid = '1' then
 797                 -- Don't deliver the interrupt until we have a valid instruction
 798                 -- coming in, so we have a valid NIA to put in SRR0.
 799                 exception := '1';
 800
 801             elsif ctrl.msr(MSR_PR) = '1' and instr_is_privileged(e_in.insn_type, e_in.insn) then
 802                 -- generate a program interrupt
 803                 exception := '1';
 804                 v.vector := 16#700#;
 805                 -- set bit 45 to indicate privileged instruction type interrupt
 806                 ctrl_tmp.srr1(63 - 45) <= '1';
 807                 report "privileged instruction";
 808
 809             elsif not HAS_FPU and e_in.fac = FPU then
 810                 -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 811                 illegal := '1';
 812
 813             elsif HAS_FPU and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 814                 -- generate a floating-point unavailable interrupt
 815                 exception := '1';
 816                 v.vector := 16#800#;
 817                 report "FP unavailable interrupt";
 818             end if;
 819         end if;
 820
 821         if valid_in = '1' and exception = '0' and illegal = '0' and e_in.unit = ALU then
 822             v.cur_instr := e_in;
 823             v.next_lr := next_nia;
 824             v.e.valid := '1';
 825
 826             case_0: case e_in.insn_type is
 827
 828             when OP_ILLEGAL =>
 829                 -- we need two cycles to write srr0 and 1
 830                 -- will need more when we have to write HEIR
 831                 illegal := '1';
 832             when OP_SC =>
 833                 -- check bit 1 of the instruction is 1 so we know this is sc;
 834                 -- 0 would mean scv, so generate an illegal instruction interrupt
 835                 -- we need two cycles to write srr0 and 1
 836                 if e_in.insn(1) = '1' then
 837                     exception := '1';
 838                     exception_nextpc := '1';
 839                     v.vector := 16#C00#;
 840                     report "sc";
 841                 else
 842                     illegal := '1';
 843                 end if;
 844             when OP_ATTN =>
 845                 -- check bits 1-10 of the instruction to make sure it's attn
 846                 -- if not then it is illegal
 847                 if e_in.insn(10 downto 1) = "0100000000" then
 848                     v.terminate := '1';
 849                     report "ATTN";
 850                 else
 851                     illegal := '1';
 852                 end if;
 853             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 854                 -- Do nothing
 855             when OP_ADD =>
 856                 if e_in.output_carry = '1' then
 857                     if e_in.input_carry /= OV then
 858                         set_carry(v.e, carry_32, carry_64);
 859                     else
 860                         v.e.xerc.ov := carry_64;
 861                         v.e.xerc.ov32 := carry_32;
 862                     end if;
 863                 end if;
 864                 if e_in.oe = '1' then
 865                     set_ov(v.e, overflow_64, overflow_32);
 866                 end if;
 867             when OP_CMP =>
 868             when OP_TRAP =>
 869                 -- trap instructions (tw, twi, td, tdi)
 870                 v.vector := 16#700#;
 871                 -- set bit 46 to say trap occurred
 872                 ctrl_tmp.srr1(63 - 46) <= '1';
 873                 if or (trapval and insn_to(e_in.insn)) = '1' then
 874                     -- generate trap-type program interrupt
 875                     exception := '1';
 876                     report "trap";
 877                 end if;
 878             when OP_ADDG6S =>
 879             when OP_CMPRB =>
 880             when OP_CMPEQB =>
 881             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 882                     OP_BPERM | OP_BCD =>
 883
 884             when OP_B =>
 885                 is_branch := '1';
 886                 taken_branch := '1';
 887                 is_direct_branch := '1';
 888                 abs_branch := e_in.br_abs;
 889                 if ctrl.msr(MSR_BE) = '1' then
 890                     do_trace := '1';
 891                 end if;
 892             when OP_BC | OP_BCREG =>
 893                 -- read_data1 is CTR
 894                 -- for OP_BCREG, read_data2 is target register (CTR, LR or TAR)
 895                 -- If this instruction updates both CTR and LR, then it is
 896                 -- doubled; the first instruction decrements CTR and determines
 897                 -- whether the branch is taken, and the second does the
 898                 -- redirect and the LR update.
 899                 bo := insn_bo(e_in.insn);
 900                 bi := insn_bi(e_in.insn);
 901                 if e_in.second = '0' then
 902                     taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 903                 else
 904                     taken_branch := r.br_taken;
 905                 end if;
 906                 v.br_taken := taken_branch;
 907                 abs_branch := e_in.br_abs;
 908                 if e_in.repeat = '0' or e_in.second = '1' then
 909                     is_branch := '1';
 910                     if e_in.insn_type = OP_BC then
 911                         is_direct_branch := '1';
 912                     end if;
 913                     if ctrl.msr(MSR_BE) = '1' then
 914                         do_trace := '1';
 915                     end if;
 916                 end if;
 917
 918             when OP_RFID =>
 919                 v.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
 920                                 not a_in(MSR_LE) & not a_in(MSR_SF);
 921                 -- Can't use msr_copy here because the partial function MSR
 922                 -- bits should be left unchanged, not zeroed.
 923                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 924                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 925                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 926                 if a_in(MSR_PR) = '1' then
 927                     ctrl_tmp.msr(MSR_EE) <= '1';
 928                     ctrl_tmp.msr(MSR_IR) <= '1';
 929                     ctrl_tmp.msr(MSR_DR) <= '1';
 930                 end if;
 931                 -- mark this as a branch so CFAR gets updated
 932                 is_branch := '1';
 933                 taken_branch := '1';
 934                 abs_branch := '1';
 935                 if HAS_FPU then
 936                     v.fp_exception_next := fp_in.exception and
 937                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 938                 end if;
 939                 do_trace := '0';
 940
 941             when OP_CNTZ =>
 942                 v.e.valid := '0';
 943                 v.cntz_in_progress := '1';
 944                 v.busy := '1';
 945             when OP_ISEL =>
 946             when OP_CROP =>
 947             when OP_MCRXRX =>
 948             when OP_DARN =>
 949             when OP_MFMSR =>
 950             when OP_MFSPR =>
 951                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 952                     "=" & to_hstring(a_in);
 953                 if is_fast_spr(e_in.read_reg1) = '1' then
 954                     spr_val := a_in;
 955                     if decode_spr_num(e_in.insn) = SPR_XER then
 956                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 957                         spr_val(63 downto 32) := (others => '0');
 958                         spr_val(63-32) := xerc_in.so;
 959                         spr_val(63-33) := xerc_in.ov;
 960                         spr_val(63-34) := xerc_in.ca;
 961                         spr_val(63-35 downto 63-43) := "000000000";
 962                         spr_val(63-44) := xerc_in.ov32;
 963                         spr_val(63-45) := xerc_in.ca32;
 964                     end if;
 965                 else
 966                     spr_val := c_in;
 967                     case decode_spr_num(e_in.insn) is
 968                     when SPR_TB =>
 969                         spr_val := ctrl.tb;
 970                     when SPR_TBU =>
 971                         spr_val(63 downto 32) := (others => '0');
 972                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 973                     when SPR_DEC =>
 974                         spr_val := ctrl.dec;
 975                     when SPR_CFAR =>
 976                         spr_val := ctrl.cfar;
 977                     when SPR_PVR =>
 978                         spr_val(63 downto 32) := (others => '0');
 979                         spr_val(31 downto 0) := PVR_MICROWATT;
 980                     when 724 =>     -- LOG_ADDR SPR
 981                         spr_val := log_wr_addr & r.log_addr_spr;
 982                     when 725 =>     -- LOG_DATA SPR
 983                         spr_val := log_rd_data;
 984                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 985                     when others =>
 986                         -- mfspr from unimplemented SPRs should be a nop in
 987                         -- supervisor mode and a program interrupt for user mode
 988                         if is_fast_spr(e_in.read_reg1) = '0' and ctrl.msr(MSR_PR) = '1' then
 989                             illegal := '1';
 990                         end if;
 991                     end case;
 992                 end if;
 993                 spr_result <= spr_val;
 994
 995             when OP_MFCR =>
 996             when OP_MTCRF =>
 997             when OP_MTMSRD =>
 998                 if e_in.insn(16) = '1' then
 999                     -- just update EE and RI
1000                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
1001                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
1002                 else
1003                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
1004                     -- and 63 (LE) (IBM bit numbering)
1005                     if e_in.is_32bit = '0' then
1006                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
1007                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
1008                     end if;
1009                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1010                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
1011                     if c_in(MSR_PR) = '1' then
1012                         ctrl_tmp.msr(MSR_EE) <= '1';
1013                         ctrl_tmp.msr(MSR_IR) <= '1';
1014                         ctrl_tmp.msr(MSR_DR) <= '1';
1015                     end if;
1016                     if HAS_FPU then
1017                         v.fp_exception_next := fp_in.exception and
1018                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
1019                     end if;
1020                 end if;
1021             when OP_MTSPR =>
1022                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1023                     "=" & to_hstring(c_in);
1024                 if is_fast_spr(e_in.write_reg) then
1025                     if decode_spr_num(e_in.insn) = SPR_XER then
1026                         v.e.xerc.so := c_in(63-32);
1027                         v.e.xerc.ov := c_in(63-33);
1028                         v.e.xerc.ca := c_in(63-34);
1029                         v.e.xerc.ov32 := c_in(63-44);
1030                         v.e.xerc.ca32 := c_in(63-45);
1031                     end if;
1032                 else
1033                     -- slow spr
1034                     case decode_spr_num(e_in.insn) is
1035                     when SPR_DEC =>
1036                         ctrl_tmp.dec <= c_in;
1037                     when 724 =>     -- LOG_ADDR SPR
1038                         v.log_addr_spr := c_in(31 downto 0);
1039                     when others =>
1040                         -- mtspr to unimplemented SPRs should be a nop in
1041                         -- supervisor mode and a program interrupt for user mode
1042                         if ctrl.msr(MSR_PR) = '1' then
1043                             illegal := '1';
1044                         end if;
1045                     end case;
1046                 end if;
1047             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1048                 if e_in.output_carry = '1' then
1049                     set_carry(v.e, rotator_carry, rotator_carry);
1050                 end if;
1051             when OP_SETB =>
1052
1053             when OP_ISYNC =>
1054                 v.redirect := '1';
1055                 v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1056
1057             when OP_ICBI =>
1058                 icache_inval <= '1';
1059
1060             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1061                 v.e.valid := '0';
1062                 v.mul_in_progress := '1';
1063                 v.busy := '1';
1064                 x_to_multiply.valid <= '1';
1065
1066             when OP_DIV | OP_DIVE | OP_MOD =>
1067                 v.e.valid := '0';
1068                 v.div_in_progress := '1';
1069                 v.busy := '1';
1070                 x_to_divider.valid <= '1';
1071
1072             when others =>
1073                 v.terminate := '1';
1074                 report "illegal";
1075             end case;
1076
1077             -- Mispredicted branches cause a redirect
1078             if is_branch = '1' then
1079                 if taken_branch = '1' then
1080                     ctrl_tmp.cfar <= e_in.nia;
1081                 end if;
1082                 if taken_branch = '1' then
1083                     v.br_offset := b_in;
1084                     v.abs_br := abs_branch;
1085                 else
1086                     v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1087                 end if;
1088                 if taken_branch /= e_in.br_pred then
1089                     v.redirect := '1';
1090                 end if;
1091                 v.br_last := is_direct_branch;
1092                 v.taken_br := taken_branch;
1093             end if;
1094
1095         elsif valid_in = '1' and exception = '0' and illegal = '0' then
1096             -- instruction for other units, i.e. LDST
1097             if e_in.unit = LDST then
1098                 lv.valid := '1';
1099             elsif e_in.unit = NONE then
1100                 illegal := '1';
1101             elsif HAS_FPU and e_in.unit = FPU then
1102                 fv.valid := '1';
1103             end if;
1104             -- Handling an ITLB miss doesn't count as having executed an instruction
1105             if e_in.insn_type = OP_FETCH_FAILED then
1106                 do_trace := '0';
1107             end if;
1108         end if;
1109
1110         -- The following cases all occur when r.busy = 1 and therefore
1111         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1112         -- the cases above which depend on valid_in = 1.
1113
1114         if ctrl.irq_state = WRITE_SRR1 then
1115             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
1116             v.e.exc_write_data := ctrl.srr1;
1117             v.e.exc_write_enable := '1';
1118             ctrl_tmp.msr(MSR_SF) <= '1';
1119             ctrl_tmp.msr(MSR_EE) <= '0';
1120             ctrl_tmp.msr(MSR_PR) <= '0';
1121             ctrl_tmp.msr(MSR_SE) <= '0';
1122             ctrl_tmp.msr(MSR_BE) <= '0';
1123             ctrl_tmp.msr(MSR_FP) <= '0';
1124             ctrl_tmp.msr(MSR_FE0) <= '0';
1125             ctrl_tmp.msr(MSR_FE1) <= '0';
1126             ctrl_tmp.msr(MSR_IR) <= '0';
1127             ctrl_tmp.msr(MSR_DR) <= '0';
1128             ctrl_tmp.msr(MSR_RI) <= '0';
1129             ctrl_tmp.msr(MSR_LE) <= '1';
1130             v.trace_next := '0';
1131             v.fp_exception_next := '0';
1132             report "Writing SRR1: " & to_hstring(ctrl.srr1);
1133
1134         elsif r.cntz_in_progress = '1' then
1135             -- cnt[lt]z always takes two cycles
1136             v.e.valid := '1';
1137         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1138             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1139                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1140                 if r.mul_in_progress = '1' then
1141                     overflow := '0';
1142                 else
1143                     overflow := divider_to_x.overflow;
1144                 end if;
1145                 if r.mul_in_progress = '1' and current.oe = '1' then
1146                     -- have to wait until next cycle for overflow indication
1147                     v.mul_finish := '1';
1148                     v.busy := '1';
1149                 else
1150                     -- We must test oe because the RC update code in writeback
1151                     -- will use the xerc value to set CR0:SO so we must not clobber
1152                     -- xerc if OE wasn't set.
1153                     if current.oe = '1' then
1154                         v.e.xerc.ov := overflow;
1155                         v.e.xerc.ov32 := overflow;
1156                         if overflow = '1' then
1157                             v.e.xerc.so := '1';
1158                         end if;
1159                     end if;
1160                     v.e.valid := '1';
1161                 end if;
1162             else
1163                 v.busy := '1';
1164                 v.mul_in_progress := r.mul_in_progress;
1165                 v.div_in_progress := r.div_in_progress;
1166             end if;
1167         elsif r.mul_finish = '1' then
1168             hold_wr_data := '1';
1169             v.e.xerc.ov := multiply_to_x.overflow;
1170             v.e.xerc.ov32 := multiply_to_x.overflow;
1171             if multiply_to_x.overflow = '1' then
1172                 v.e.xerc.so := '1';
1173             end if;
1174             v.e.valid := '1';
1175         end if;
1176
1177         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1178         -- be set during the execution of a FP instruction.
1179         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1180         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1181         if HAS_FPU and fp_in.interrupt = '1' then
1182             v.vector := 16#700#;
1183             ctrl_tmp.srr1(63 - 43) <= '1';
1184             exception := '1';
1185         end if;
1186
1187         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1188             exception := '1';
1189             v.vector := 16#700#;
1190             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1191             -- set bit 44 to indicate we have an illegal
1192             ctrl_tmp.srr1(63 - 44) <= '1';
1193             report "illegal";
1194         end if;
1195         if exception = '1' then
1196             v.e.exc_write_enable := '1';
1197             if exception_nextpc = '1' then
1198                 v.e.exc_write_data := next_nia;
1199             end if;
1200         end if;
1201
1202         -- generate DSI or DSegI for load/store exceptions
1203         -- or ISI or ISegI for instruction fetch exceptions
1204         if l_in.exception = '1' then
1205             if l_in.alignment = '1' then
1206                 v.vector := 16#600#;
1207             elsif l_in.instr_fault = '0' then
1208                 if l_in.segment_fault = '0' then
1209                     v.vector := 16#300#;
1210                 else
1211                     v.vector := 16#380#;
1212                 end if;
1213             else
1214                 if l_in.segment_fault = '0' then
1215                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1216                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1217                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1218                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1219                     v.vector := 16#400#;
1220                 else
1221                     v.vector := 16#480#;
1222                 end if;
1223             end if;
1224             v.e.exc_write_enable := '1';
1225             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1226             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1227         end if;
1228
1229         if exception = '1' or l_in.exception = '1' then
1230             ctrl_tmp.irq_state <= WRITE_SRR1;
1231             v.redirect := '1';
1232             v.do_intr := '1';
1233         end if;
1234
1235         if do_trace = '1' then
1236             v.trace_next := '1';
1237         end if;
1238
1239         if hold_wr_data = '0' then
1240             v.e.write_data := alu_result;
1241         else
1242             v.e.write_data := r.e.write_data;
1243         end if;
1244         v.e.write_reg := current.write_reg;
1245         v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
1246         v.e.rc := current.rc and v.e.valid and not exception;
1247         v.e.write_cr_data := write_cr_data;
1248         v.e.write_cr_mask := write_cr_mask;
1249         v.e.write_cr_enable := current.output_cr and v.e.valid and not exception;
1250         v.e.write_xerc_enable := current.output_xer and v.e.valid and not exception;
1251
1252         bypass_data.tag.valid <= current.instr_tag.valid and current.write_reg_enable and v.e.valid;
1253         bypass_data.tag.tag <= current.instr_tag.tag;
1254         bypass_data.data <= v.e.write_data;
1255
1256         bypass_cr_data.tag.valid <= current.instr_tag.valid and current.output_cr and v.e.valid;
1257         bypass_cr_data.tag.tag <= current.instr_tag.tag;
1258         for i in 0 to 7 loop
1259             if v.e.write_cr_mask(i) = '1' then
1260                 bypass_cr_data.data(i*4 + 3 downto i*4) <= v.e.write_cr_data(i*4 + 3 downto i*4);
1261             else
1262                 bypass_cr_data.data(i*4 + 3 downto i*4) <= cr_in(i*4 + 3 downto i*4);
1263             end if;
1264         end loop;
1265
1266         -- Defer completion for one cycle when redirecting.
1267         -- This also ensures r.busy = 1 when ctrl.irq_state = WRITE_SRR1
1268         if v.redirect = '1' then
1269             v.busy := '1';
1270             v.e.valid := '0';
1271         end if;
1272         if r.redirect = '1' then
1273             v.e.valid := '1';
1274         end if;
1275
1276         -- Outputs to fetch1
1277         f.redirect := r.redirect;
1278         f.br_nia := r.last_nia;
1279         f.br_last := r.br_last and not r.do_intr;
1280         f.br_taken := r.taken_br;
1281         if r.do_intr = '1' then
1282             f.redirect_nia := std_ulogic_vector(to_unsigned(r.vector, 64));
1283             f.virt_mode := '0';
1284             f.priv_mode := '1';
1285             -- XXX need an interrupt LE bit here, e.g. from LPCR
1286             f.big_endian := '0';
1287             f.mode_32bit := '0';
1288         else
1289             if r.abs_br = '1' then
1290                 f.redirect_nia := r.br_offset;
1291             else
1292                 f.redirect_nia := std_ulogic_vector(unsigned(r.last_nia) + unsigned(r.br_offset));
1293             end if;
1294             -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
1295             f.virt_mode := r.redir_mode(3);
1296             f.priv_mode := r.redir_mode(2);
1297             f.big_endian := r.redir_mode(1);
1298             f.mode_32bit := r.redir_mode(0);
1299         end if;
1300
1301         -- Outputs to loadstore1 (async)
1302         lv.op := e_in.insn_type;
1303         lv.nia := e_in.nia;
1304         lv.instr_tag := e_in.instr_tag;
1305         lv.addr1 := a_in;
1306         lv.addr2 := b_in;
1307         lv.data := c_in;
1308         lv.write_reg := e_in.write_reg;
1309         lv.length := e_in.data_len;
1310         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1311         lv.sign_extend := e_in.sign_extend;
1312         lv.update := e_in.update;
1313         lv.xerc := xerc_in;
1314         lv.reserve := e_in.reserve;
1315         lv.rc := e_in.rc;
1316         lv.insn := e_in.insn;
1317         -- decode l*cix and st*cix instructions here
1318         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1319             e_in.insn(5 downto 1) = "10101" then
1320             lv.ci := '1';
1321         end if;
1322         lv.virt_mode := ctrl.msr(MSR_DR);
1323         lv.priv_mode := not ctrl.msr(MSR_PR);
1324         lv.mode_32bit := not ctrl.msr(MSR_SF);
1325         lv.is_32bit := e_in.is_32bit;
1326         lv.repeat := e_in.repeat;
1327         lv.second := e_in.second;
1328
1329         -- Outputs to FPU
1330         fv.op := e_in.insn_type;
1331         fv.nia := e_in.nia;
1332         fv.insn := e_in.insn;
1333         fv.itag := e_in.instr_tag;
1334         fv.single := e_in.is_32bit;
1335         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1336         fv.fra := a_in;
1337         fv.frb := b_in;
1338         fv.frc := c_in;
1339         fv.frt := e_in.write_reg;
1340         fv.rc := e_in.rc;
1341         fv.out_cr := e_in.output_cr;
1342
1343         -- Update registers
1344         rin <= v;
1345
1346         -- update outputs
1347         f_out <= f;
1348         l_out <= lv;
1349         e_out <= r.e;
1350         fp_out <= fv;
1351         flush_out <= f_out.redirect;
1352
1353         exception_log <= exception;
1354         irq_valid_log <= irq_valid;
1355     end process;
1356
1357     e1_log: if LOG_LENGTH > 0 generate
1358         signal log_data : std_ulogic_vector(14 downto 0);
1359     begin
1360         ex1_log : process(clk)
1361         begin
1362             if rising_edge(clk) then
1363                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1364                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1365                             exception_log &
1366                             irq_valid_log &
1367                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1368                             "000" &
1369                             r.e.write_enable &
1370                             r.e.valid &
1371                             f_out.redirect &
1372                             r.busy &
1373                             flush_out;
1374             end if;
1375         end process;
1376         log_out <= log_data;
1377     end generate;
1378 end architecture behaviour;