execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_in : in std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33         interrupt_in : std_ulogic;
  34
  35         -- asynchronous
  36         l_out : out Execute1ToLoadstore1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40         bypass_data : out bypass_data_t;
  41         bypass_cr_data : out cr_bypass_data_t;
  42
  43         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  44
  45         icache_inval : out std_ulogic;
  46         terminate_out : out std_ulogic;
  47
  48         log_out : out std_ulogic_vector(14 downto 0);
  49         log_rd_addr : out std_ulogic_vector(31 downto 0);
  50         log_rd_data : in std_ulogic_vector(63 downto 0);
  51         log_wr_addr : in std_ulogic_vector(31 downto 0)
  52         );
  53 end entity execute1;
  54
  55 architecture behaviour of execute1 is
  56     type reg_type is record
  57         e : Execute1ToWritebackType;
  58         cur_instr : Decode2ToExecute1Type;
  59         busy: std_ulogic;
  60         terminate: std_ulogic;
  61         fp_exception_next : std_ulogic;
  62         trace_next : std_ulogic;
  63         prev_op : insn_type_t;
  64         br_taken : std_ulogic;
  65         mul_in_progress : std_ulogic;
  66         mul_finish : std_ulogic;
  67         div_in_progress : std_ulogic;
  68         cntz_in_progress : std_ulogic;
  69         log_addr_spr : std_ulogic_vector(31 downto 0);
  70     end record;
  71     constant reg_type_init : reg_type :=
  72         (e => Execute1ToWritebackInit,
  73          cur_instr => Decode2ToExecute1Init,
  74          busy => '0', terminate => '0',
  75          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL, br_taken => '0',
  76          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  77          others => (others => '0'));
  78
  79     signal r, rin : reg_type;
  80
  81     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  82     signal cr_in : std_ulogic_vector(31 downto 0);
  83     signal xerc_in : xer_common_t;
  84
  85     signal valid_in : std_ulogic;
  86     signal ctrl: ctrl_t := (others => (others => '0'));
  87     signal ctrl_tmp: ctrl_t := (others => (others => '0'));
  88     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  89     signal rot_sign_ext: std_ulogic;
  90     signal rotator_result: std_ulogic_vector(63 downto 0);
  91     signal rotator_carry: std_ulogic;
  92     signal logical_result: std_ulogic_vector(63 downto 0);
  93     signal countzero_result: std_ulogic_vector(63 downto 0);
  94     signal alu_result: std_ulogic_vector(63 downto 0);
  95     signal adder_result: std_ulogic_vector(63 downto 0);
  96     signal misc_result: std_ulogic_vector(63 downto 0);
  97     signal muldiv_result: std_ulogic_vector(63 downto 0);
  98     signal spr_result: std_ulogic_vector(63 downto 0);
  99     signal result_mux_sel: std_ulogic_vector(2 downto 0);
 100     signal sub_mux_sel: std_ulogic_vector(2 downto 0);
 101     signal next_nia : std_ulogic_vector(63 downto 0);
 102     signal current: Decode2ToExecute1Type;
 103
 104     signal carry_32 : std_ulogic;
 105     signal carry_64 : std_ulogic;
 106     signal overflow_32 : std_ulogic;
 107     signal overflow_64 : std_ulogic;
 108
 109     signal trapval : std_ulogic_vector(4 downto 0);
 110
 111     signal write_cr_mask : std_ulogic_vector(7 downto 0);
 112     signal write_cr_data : std_ulogic_vector(31 downto 0);
 113
 114     -- multiply signals
 115     signal x_to_multiply: MultiplyInputType;
 116     signal multiply_to_x: MultiplyOutputType;
 117
 118     -- divider signals
 119     signal x_to_divider: Execute1ToDividerType;
 120     signal divider_to_x: DividerToExecute1Type;
 121
 122     -- random number generator signals
 123     signal random_raw  : std_ulogic_vector(63 downto 0);
 124     signal random_cond : std_ulogic_vector(63 downto 0);
 125     signal random_err  : std_ulogic;
 126
 127     -- signals for logging
 128     signal exception_log : std_ulogic;
 129     signal irq_valid_log : std_ulogic;
 130
 131     type privilege_level is (USER, SUPER);
 132     type op_privilege_array is array(insn_type_t) of privilege_level;
 133     constant op_privilege: op_privilege_array := (
 134         OP_ATTN => SUPER,
 135         OP_MFMSR => SUPER,
 136         OP_MTMSRD => SUPER,
 137         OP_RFID => SUPER,
 138         OP_TLBIE => SUPER,
 139         others => USER
 140         );
 141
 142     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 143         return boolean is
 144     begin
 145         if op_privilege(op) = SUPER then
 146             return true;
 147         elsif op = OP_MFSPR or op = OP_MTSPR then
 148             return insn(20) = '1';
 149         else
 150             return false;
 151         end if;
 152     end;
 153
 154     procedure set_carry(e: inout Execute1ToWritebackType;
 155                         carry32 : in std_ulogic;
 156                         carry : in std_ulogic) is
 157     begin
 158         e.xerc.ca32 := carry32;
 159         e.xerc.ca := carry;
 160     end;
 161
 162     procedure set_ov(e: inout Execute1ToWritebackType;
 163                      ov   : in std_ulogic;
 164                      ov32 : in std_ulogic) is
 165     begin
 166         e.xerc.ov32 := ov32;
 167         e.xerc.ov := ov;
 168         if ov = '1' then
 169             e.xerc.so := '1';
 170         end if;
 171     end;
 172
 173     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 174                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 175     begin
 176         return (ca xor msb_r) and not (msb_a xor msb_b);
 177     end;
 178
 179     function decode_input_carry(ic : carry_in_t;
 180                                 xerc : xer_common_t) return std_ulogic is
 181     begin
 182         case ic is
 183         when ZERO =>
 184             return '0';
 185         when CA =>
 186             return xerc.ca;
 187         when OV =>
 188             return xerc.ov;
 189         when ONE =>
 190             return '1';
 191         end case;
 192     end;
 193
 194     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 195         return std_ulogic_vector is
 196         variable msr_out: std_ulogic_vector(63 downto 0);
 197     begin
 198         -- ISA says this:
 199         --  Defined MSR bits are classified as either full func-
 200         --  tion or partial function. Full function MSR bits are
 201         --  saved in SRR1 or HSRR1 when an interrupt other
 202         --  than a System Call Vectored interrupt occurs and
 203         --  restored by rfscv, rfid, or hrfid, while partial func-
 204         --  tion MSR bits are not saved or restored.
 205         --  Full function MSR bits lie in the range 0:32, 37:41, and
 206         --  48:63, and partial function MSR bits lie in the range
 207         --  33:36 and 42:47. (Note this is IBM bit numbering).
 208         msr_out := (others => '0');
 209         msr_out(63 downto 31) := msr(63 downto 31);
 210         msr_out(26 downto 22) := msr(26 downto 22);
 211         msr_out(15 downto 0)  := msr(15 downto 0);
 212         return msr_out;
 213     end;
 214
 215     -- Tell vivado to keep the hierarchy for the random module so that the
 216     -- net names in the xdc file match.
 217     attribute keep_hierarchy : string;
 218     attribute keep_hierarchy of random_0 : label is "yes";
 219
 220 begin
 221
 222     rotator_0: entity work.rotator
 223         port map (
 224             rs => c_in,
 225             ra => a_in,
 226             shift => b_in(6 downto 0),
 227             insn => e_in.insn,
 228             is_32bit => e_in.is_32bit,
 229             right_shift => right_shift,
 230             arith => e_in.is_signed,
 231             clear_left => rot_clear_left,
 232             clear_right => rot_clear_right,
 233             sign_ext_rs => rot_sign_ext,
 234             result => rotator_result,
 235             carry_out => rotator_carry
 236             );
 237
 238     logical_0: entity work.logical
 239         port map (
 240             rs => c_in,
 241             rb => b_in,
 242             op => e_in.insn_type,
 243             invert_in => e_in.invert_a,
 244             invert_out => e_in.invert_out,
 245             result => logical_result,
 246             datalen => e_in.data_len
 247             );
 248
 249     countzero_0: entity work.zero_counter
 250         port map (
 251             clk => clk,
 252             rs => c_in,
 253             count_right => e_in.insn(10),
 254             is_32bit => e_in.is_32bit,
 255             result => countzero_result
 256             );
 257
 258     multiply_0: entity work.multiply
 259         port map (
 260             clk => clk,
 261             m_in => x_to_multiply,
 262             m_out => multiply_to_x
 263             );
 264
 265     divider_0: entity work.divider
 266         port map (
 267             clk => clk,
 268             rst => rst,
 269             d_in => x_to_divider,
 270             d_out => divider_to_x
 271             );
 272
 273     random_0: entity work.random
 274         port map (
 275             clk => clk,
 276             data => random_cond,
 277             raw => random_raw,
 278             err => random_err
 279             );
 280
 281     dbg_msr_out <= ctrl.msr;
 282     log_rd_addr <= r.log_addr_spr;
 283
 284     a_in <= e_in.read_data1;
 285     b_in <= e_in.read_data2;
 286     c_in <= e_in.read_data3;
 287     cr_in <= e_in.cr;
 288
 289     -- XER forwarding. To avoid having to track XER hazards, we use
 290     -- the previously latched value.  Since the XER common bits
 291     -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 292     -- handled here, we can just forward the result being sent to
 293     -- writeback.
 294     xerc_in <= r.e.xerc when r.e.write_xerc_enable = '1' or r.busy = '1' else e_in.xerc;
 295
 296     busy_out <= l_in.busy or r.busy or fp_in.busy;
 297     valid_in <= e_in.valid and not busy_out and not flush_in;
 298
 299     terminate_out <= r.terminate;
 300
 301     current <= e_in when r.busy = '0' else r.cur_instr;
 302
 303     -- Result mux
 304     with current.result_sel select alu_result <=
 305         adder_result       when "000",
 306         logical_result     when "001",
 307         rotator_result     when "010",
 308         muldiv_result      when "011",
 309         countzero_result   when "100",
 310         spr_result         when "101",
 311         next_nia           when "110",
 312         misc_result        when others;
 313
 314     execute1_0: process(clk)
 315     begin
 316         if rising_edge(clk) then
 317             if rst = '1' then
 318                 r <= reg_type_init;
 319                 ctrl.tb <= (others => '0');
 320                 ctrl.dec <= (others => '0');
 321                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 322             else
 323                 r <= rin;
 324                 ctrl <= ctrl_tmp;
 325                 if valid_in = '1' then
 326                     report "execute " & to_hstring(e_in.nia) & " op=" & insn_type_t'image(e_in.insn_type) &
 327                         " wr=" & to_hstring(rin.e.write_reg) & " we=" & std_ulogic'image(rin.e.write_enable) &
 328                         " tag=" & integer'image(rin.e.instr_tag.tag) & std_ulogic'image(rin.e.instr_tag.valid);
 329                 end if;
 330             end if;
 331         end if;
 332     end process;
 333
 334     -- Data path for integer instructions
 335     execute1_dp: process(all)
 336         variable a_inv : std_ulogic_vector(63 downto 0);
 337         variable b_or_m1 : std_ulogic_vector(63 downto 0);
 338         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 339         variable sign1, sign2 : std_ulogic;
 340         variable abs1, abs2 : signed(63 downto 0);
 341         variable addend : std_ulogic_vector(127 downto 0);
 342         variable addg6s : std_ulogic_vector(63 downto 0);
 343         variable crbit : integer range 0 to 31;
 344         variable isel_result : std_ulogic_vector(63 downto 0);
 345         variable darn : std_ulogic_vector(63 downto 0);
 346         variable setb_result : std_ulogic_vector(63 downto 0);
 347         variable mfcr_result : std_ulogic_vector(63 downto 0);
 348         variable lo, hi : integer;
 349         variable l : std_ulogic;
 350         variable zerohi, zerolo : std_ulogic;
 351         variable msb_a, msb_b : std_ulogic;
 352         variable a_lt : std_ulogic;
 353         variable a_lt_lo : std_ulogic;
 354         variable a_lt_hi : std_ulogic;
 355         variable newcrf : std_ulogic_vector(3 downto 0);
 356         variable bf, bfa : std_ulogic_vector(2 downto 0);
 357         variable crnum : crnum_t;
 358         variable scrnum : crnum_t;
 359         variable cr_operands : std_ulogic_vector(1 downto 0);
 360         variable crresult : std_ulogic;
 361         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 362         variable btnum : integer range 0 to 3;
 363         variable banum, bbnum : integer range 0 to 31;
 364         variable j : integer;
 365     begin
 366         -- Main adder
 367         if e_in.invert_a = '0' then
 368             a_inv := a_in;
 369         else
 370             a_inv := not a_in;
 371         end if;
 372         if e_in.addm1 = '0' then
 373             b_or_m1 := b_in;
 374         else
 375             b_or_m1 := (others => '1');
 376         end if;
 377         sum_with_carry := ppc_adde(a_inv, b_or_m1,
 378                                    decode_input_carry(e_in.input_carry, xerc_in));
 379         adder_result <= sum_with_carry(63 downto 0);
 380         carry_32 <= sum_with_carry(32) xor a_inv(32) xor b_in(32);
 381         carry_64 <= sum_with_carry(64);
 382         overflow_32 <= calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31));
 383         overflow_64 <= calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63));
 384
 385         -- signals to multiply and divide units
 386         sign1 := '0';
 387         sign2 := '0';
 388         if e_in.is_signed = '1' then
 389             if e_in.is_32bit = '1' then
 390                 sign1 := a_in(31);
 391                 sign2 := b_in(31);
 392             else
 393                 sign1 := a_in(63);
 394                 sign2 := b_in(63);
 395             end if;
 396         end if;
 397         -- take absolute values
 398         if sign1 = '0' then
 399             abs1 := signed(a_in);
 400         else
 401             abs1 := - signed(a_in);
 402         end if;
 403         if sign2 = '0' then
 404             abs2 := signed(b_in);
 405         else
 406             abs2 := - signed(b_in);
 407         end if;
 408
 409         -- Interface to multiply and divide units
 410         x_to_divider.is_signed <= e_in.is_signed;
 411         x_to_divider.is_32bit <= e_in.is_32bit;
 412         x_to_divider.is_extended <= '0';
 413         x_to_divider.is_modulus <= '0';
 414         if e_in.insn_type = OP_MOD then
 415             x_to_divider.is_modulus <= '1';
 416         end if;
 417
 418         addend := (others => '0');
 419         if e_in.insn(26) = '0' then
 420             -- integer multiply-add, major op 4 (if it is a multiply)
 421             addend(63 downto 0) := c_in;
 422             if e_in.is_signed = '1' then
 423                 addend(127 downto 64) := (others => c_in(63));
 424             end if;
 425         end if;
 426         if (sign1 xor sign2) = '1' then
 427             addend := not addend;
 428         end if;
 429
 430         x_to_multiply.is_32bit <= e_in.is_32bit;
 431         x_to_multiply.not_result <= sign1 xor sign2;
 432         x_to_multiply.addend <= addend;
 433         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 434         if e_in.is_32bit = '0' then
 435             -- 64-bit forms
 436             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 437             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 438             if e_in.insn_type = OP_DIVE then
 439                 x_to_divider.is_extended <= '1';
 440             end if;
 441             x_to_divider.dividend <= std_ulogic_vector(abs1);
 442             x_to_divider.divisor <= std_ulogic_vector(abs2);
 443         else
 444             -- 32-bit forms
 445             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 446             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 447             x_to_divider.is_extended <= '0';
 448             if e_in.insn_type = OP_DIVE then   -- extended forms
 449                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 450             else
 451                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 452             end if;
 453             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 454         end if;
 455
 456         case current.sub_select(1 downto 0) is
 457             when "00" =>
 458                 muldiv_result <= multiply_to_x.result(63 downto 0);
 459             when "01" =>
 460                 muldiv_result <= multiply_to_x.result(127 downto 64);
 461             when "10" =>
 462                 muldiv_result <= multiply_to_x.result(63 downto 32) &
 463                                  multiply_to_x.result(63 downto 32);
 464             when others =>
 465                 muldiv_result <= divider_to_x.write_reg_data;
 466         end case;
 467
 468         -- Compute misc_result
 469         case current.sub_select is
 470             when "000" =>
 471                 misc_result <= (others => '0');
 472             when "001" =>
 473                 -- addg6s
 474                 addg6s := (others => '0');
 475                 for i in 0 to 14 loop
 476                     lo := i * 4;
 477                     hi := (i + 1) * 4;
 478                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 479                         addg6s(lo + 3 downto lo) := "0110";
 480                     end if;
 481                 end loop;
 482                 if sum_with_carry(64) = '0' then
 483                     addg6s(63 downto 60) := "0110";
 484                 end if;
 485                 misc_result <= addg6s;
 486             when "010" =>
 487                 -- isel
 488                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 489                 if cr_in(31-crbit) = '1' then
 490                     isel_result := a_in;
 491                 else
 492                     isel_result := b_in;
 493                 end if;
 494                 misc_result <= isel_result;
 495             when "011" =>
 496                 -- darn
 497                 darn := (others => '1');
 498                 if random_err = '0' then
 499                     case e_in.insn(17 downto 16) is
 500                         when "00" =>
 501                             darn := x"00000000" & random_cond(31 downto 0);
 502                         when "10" =>
 503                             darn := random_raw;
 504                         when others =>
 505                             darn := random_cond;
 506                     end case;
 507                 end if;
 508                 misc_result <= darn;
 509             when "100" =>
 510                 -- mfmsr
 511                 misc_result <= ctrl.msr;
 512             when "101" =>
 513                 if e_in.insn(20) = '0' then
 514                     -- mfcr
 515                     mfcr_result := x"00000000" & cr_in;
 516                 else
 517                     -- mfocrf
 518                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 519                     mfcr_result := (others => '0');
 520                     for i in 0 to 7 loop
 521                         lo := (7-i)*4;
 522                         hi := lo + 3;
 523                         if crnum = i then
 524                             mfcr_result(hi downto lo) := cr_in(hi downto lo);
 525                         end if;
 526                     end loop;
 527                 end if;
 528                 misc_result <= mfcr_result;
 529             when "110" =>
 530                 -- setb
 531                 bfa := insn_bfa(e_in.insn);
 532                 crbit := to_integer(unsigned(bfa)) * 4;
 533                 setb_result := (others => '0');
 534                 if cr_in(31 - crbit) = '1' then
 535                     setb_result := (others => '1');
 536                 elsif cr_in(30 - crbit) = '1' then
 537                     setb_result(0) := '1';
 538                 end if;
 539                 misc_result <= setb_result;
 540             when others =>
 541                 misc_result <= (others => '0');
 542         end case;
 543
 544         -- compute comparison results
 545         -- Note, we have done RB - RA, not RA - RB
 546         if e_in.insn_type = OP_CMP then
 547             l := insn_l(e_in.insn);
 548         else
 549             l := not e_in.is_32bit;
 550         end if;
 551         zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 552         zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 553         if zerolo = '1' and (l = '0' or zerohi = '1') then
 554             -- values are equal
 555             trapval <= "00100";
 556         else
 557             a_lt_lo := '0';
 558             a_lt_hi := '0';
 559             if unsigned(a_in(30 downto 0)) < unsigned(b_in(30 downto 0)) then
 560                 a_lt_lo := '1';
 561             end if;
 562             if unsigned(a_in(62 downto 31)) < unsigned(b_in(62 downto 31)) then
 563                 a_lt_hi := '1';
 564             end if;
 565             if l = '1' then
 566                 -- 64-bit comparison
 567                 msb_a := a_in(63);
 568                 msb_b := b_in(63);
 569                 a_lt := a_lt_hi or (zerohi and (a_in(31) xnor b_in(31)) and a_lt_lo);
 570             else
 571                 -- 32-bit comparison
 572                 msb_a := a_in(31);
 573                 msb_b := b_in(31);
 574                 a_lt := a_lt_lo;
 575             end if;
 576             if msb_a /= msb_b then
 577                 -- Comparison is clear from MSB difference.
 578                 -- for signed, 0 is greater; for unsigned, 1 is greater
 579                 trapval <= msb_a & msb_b & '0' & msb_b & msb_a;
 580             else
 581                 -- MSBs are equal, so signed and unsigned comparisons give the
 582                 -- same answer.
 583                 trapval <= a_lt & not a_lt & '0' & a_lt & not a_lt;
 584             end if;
 585         end if;
 586
 587         -- CR result mux
 588         bf := insn_bf(e_in.insn);
 589         crnum := to_integer(unsigned(bf));
 590         newcrf := (others => '0');
 591         case current.sub_select is
 592             when "000" =>
 593                 -- CMP and CMPL instructions
 594                 if e_in.is_signed = '1' then
 595                     newcrf := trapval(4 downto 2) & xerc_in.so;
 596                 else
 597                     newcrf := trapval(1 downto 0) & trapval(2) & xerc_in.so;
 598                 end if;
 599             when "001" =>
 600                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 601             when "010" =>
 602                 newcrf := ppc_cmpeqb(a_in, b_in);
 603             when "011" =>
 604                 if current.insn(1) = '1' then
 605                     -- CR logical instructions
 606                     j := (7 - crnum) * 4;
 607                     newcrf := cr_in(j + 3 downto j);
 608                     bt := insn_bt(e_in.insn);
 609                     ba := insn_ba(e_in.insn);
 610                     bb := insn_bb(e_in.insn);
 611                     btnum := 3 - to_integer(unsigned(bt(1 downto 0)));
 612                     banum := 31 - to_integer(unsigned(ba));
 613                     bbnum := 31 - to_integer(unsigned(bb));
 614                     -- Bits 6-9 of the instruction word give the truth table
 615                     -- of the requested logical operation
 616                     cr_operands := cr_in(banum) & cr_in(bbnum);
 617                     crresult := e_in.insn(6 + to_integer(unsigned(cr_operands)));
 618                     for i in 0 to 3 loop
 619                         if i = btnum then
 620                             newcrf(i) := crresult;
 621                         end if;
 622                     end loop;
 623                 else
 624                     -- MCRF
 625                     bfa := insn_bfa(e_in.insn);
 626                     scrnum := to_integer(unsigned(bfa));
 627                     j := (7 - scrnum) * 4;
 628                     newcrf := cr_in(j + 3 downto j);
 629                 end if;
 630             when "100" =>
 631                 -- MCRXRX
 632                 newcrf := xerc_in.ov & xerc_in.ca & xerc_in.ov32 & xerc_in.ca32;
 633             when others =>
 634         end case;
 635         if current.insn_type = OP_MTCRF then
 636             if e_in.insn(20) = '0' then
 637                 -- mtcrf
 638                 write_cr_mask <= insn_fxm(e_in.insn);
 639             else
 640                 -- mtocrf: We require one hot priority encoding here
 641                 crnum := fxm_to_num(insn_fxm(e_in.insn));
 642                 write_cr_mask <= num_to_fxm(crnum);
 643             end if;
 644             write_cr_data <= c_in(31 downto 0);
 645         else
 646             write_cr_mask <= num_to_fxm(crnum);
 647             write_cr_data <= newcrf & newcrf & newcrf & newcrf &
 648                              newcrf & newcrf & newcrf & newcrf;
 649         end if;
 650
 651     end process;
 652
 653     execute1_1: process(all)
 654         variable v : reg_type;
 655         variable lo, hi : integer;
 656         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 657         variable bo, bi : std_ulogic_vector(4 downto 0);
 658         variable overflow : std_ulogic;
 659         variable lv : Execute1ToLoadstore1Type;
 660         variable irq_valid : std_ulogic;
 661         variable exception : std_ulogic;
 662         variable illegal : std_ulogic;
 663         variable is_branch : std_ulogic;
 664         variable is_direct_branch : std_ulogic;
 665         variable taken_branch : std_ulogic;
 666         variable abs_branch : std_ulogic;
 667         variable spr_val : std_ulogic_vector(63 downto 0);
 668         variable do_trace : std_ulogic;
 669         variable hold_wr_data : std_ulogic;
 670         variable fv : Execute1ToFPUType;
 671     begin
 672         is_branch := '0';
 673         is_direct_branch := '0';
 674         taken_branch := '0';
 675         abs_branch := '0';
 676         hold_wr_data := '0';
 677
 678         v := r;
 679         v.e := Execute1ToWritebackInit;
 680         v.e.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
 681                           not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
 682         v.e.xerc := xerc_in;
 683
 684         lv := Execute1ToLoadstore1Init;
 685         fv := Execute1ToFPUInit;
 686
 687         x_to_multiply.valid <= '0';
 688         x_to_divider.valid <= '0';
 689         v.mul_in_progress := '0';
 690         v.div_in_progress := '0';
 691         v.cntz_in_progress := '0';
 692         v.mul_finish := '0';
 693
 694         spr_result <= (others => '0');
 695         spr_val := (others => '0');
 696
 697         ctrl_tmp <= ctrl;
 698         -- FIXME: run at 512MHz not core freq
 699         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 700         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 701
 702         irq_valid := '0';
 703         if ctrl.msr(MSR_EE) = '1' then
 704             if ctrl.dec(63) = '1' then
 705                 v.e.intr_vec := 16#900#;
 706                 report "IRQ valid: DEC";
 707                 irq_valid := '1';
 708             elsif ext_irq_in = '1' then
 709                 v.e.intr_vec := 16#500#;
 710                 report "IRQ valid: External";
 711                 irq_valid := '1';
 712             end if;
 713         end if;
 714
 715         v.terminate := '0';
 716         icache_inval <= '0';
 717         v.busy := '0';
 718
 719         -- Next insn adder used in a couple of places
 720         next_nia <= std_ulogic_vector(unsigned(e_in.nia) + 4);
 721
 722         -- rotator control signals
 723         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 724         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 725         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 726         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 727
 728         v.e.srr1 := (others => '0');
 729         exception := '0';
 730         illegal := '0';
 731         if valid_in = '1' then
 732             v.e.last_nia := e_in.nia;
 733         else
 734             v.e.last_nia := r.e.last_nia;
 735         end if;
 736
 737         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 738         v.e.instr_tag := current.instr_tag;
 739
 740         do_trace := valid_in and ctrl.msr(MSR_SE);
 741         if valid_in = '1' then
 742             v.prev_op := e_in.insn_type;
 743         end if;
 744
 745         -- Determine if there is any exception to be taken
 746         -- before/instead of executing this instruction
 747         if valid_in = '1' and e_in.second = '0' then
 748             if HAS_FPU and r.fp_exception_next = '1' then
 749                 -- This is used for FP-type program interrupts that
 750                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 751                 exception := '1';
 752                 v.e.intr_vec := 16#700#;
 753                 v.e.srr1(47 - 43) := '1';
 754                 v.e.srr1(47 - 47) := '1';
 755             elsif r.trace_next = '1' then
 756                 -- Generate a trace interrupt rather than executing the next instruction
 757                 -- or taking any asynchronous interrupt
 758                 exception := '1';
 759                 v.e.intr_vec := 16#d00#;
 760                 v.e.srr1(47 - 33) := '1';
 761                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 762                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 763                     v.e.srr1(47 - 35) := '1';
 764                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 765                     v.e.srr1(47 - 36) := '1';
 766                 end if;
 767
 768             elsif irq_valid = '1' then
 769                 -- Don't deliver the interrupt until we have a valid instruction
 770                 -- coming in, so we have a valid NIA to put in SRR0.
 771                 exception := '1';
 772
 773             elsif ctrl.msr(MSR_PR) = '1' and instr_is_privileged(e_in.insn_type, e_in.insn) then
 774                 -- generate a program interrupt
 775                 exception := '1';
 776                 v.e.intr_vec := 16#700#;
 777                 -- set bit 45 to indicate privileged instruction type interrupt
 778                 v.e.srr1(47 - 45) := '1';
 779                 report "privileged instruction";
 780
 781             elsif not HAS_FPU and e_in.fac = FPU then
 782                 -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 783                 illegal := '1';
 784
 785             elsif HAS_FPU and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 786                 -- generate a floating-point unavailable interrupt
 787                 exception := '1';
 788                 v.e.intr_vec := 16#800#;
 789                 report "FP unavailable interrupt";
 790             end if;
 791         end if;
 792
 793         if valid_in = '1' and exception = '0' and illegal = '0' and e_in.unit = ALU then
 794             v.cur_instr := e_in;
 795             v.e.valid := '1';
 796
 797             case_0: case e_in.insn_type is
 798
 799             when OP_ILLEGAL =>
 800                 -- we need two cycles to write srr0 and 1
 801                 -- will need more when we have to write HEIR
 802                 illegal := '1';
 803             when OP_SC =>
 804                 -- check bit 1 of the instruction is 1 so we know this is sc;
 805                 -- 0 would mean scv, so generate an illegal instruction interrupt
 806                 -- we need two cycles to write srr0 and 1
 807                 if e_in.insn(1) = '1' then
 808                     exception := '1';
 809                     v.e.intr_vec := 16#C00#;
 810                     v.e.last_nia := next_nia;
 811                     report "sc";
 812                 else
 813                     illegal := '1';
 814                 end if;
 815             when OP_ATTN =>
 816                 -- check bits 1-10 of the instruction to make sure it's attn
 817                 -- if not then it is illegal
 818                 if e_in.insn(10 downto 1) = "0100000000" then
 819                     v.terminate := '1';
 820                     report "ATTN";
 821                 else
 822                     illegal := '1';
 823                 end if;
 824             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 825                 -- Do nothing
 826             when OP_ADD =>
 827                 if e_in.output_carry = '1' then
 828                     if e_in.input_carry /= OV then
 829                         set_carry(v.e, carry_32, carry_64);
 830                     else
 831                         v.e.xerc.ov := carry_64;
 832                         v.e.xerc.ov32 := carry_32;
 833                     end if;
 834                 end if;
 835                 if e_in.oe = '1' then
 836                     set_ov(v.e, overflow_64, overflow_32);
 837                 end if;
 838             when OP_CMP =>
 839             when OP_TRAP =>
 840                 -- trap instructions (tw, twi, td, tdi)
 841                 v.e.intr_vec := 16#700#;
 842                 -- set bit 46 to say trap occurred
 843                 v.e.srr1(47 - 46) := '1';
 844                 if or (trapval and insn_to(e_in.insn)) = '1' then
 845                     -- generate trap-type program interrupt
 846                     exception := '1';
 847                     report "trap";
 848                 end if;
 849             when OP_ADDG6S =>
 850             when OP_CMPRB =>
 851             when OP_CMPEQB =>
 852             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 853                     OP_BPERM | OP_BCD =>
 854
 855             when OP_B =>
 856                 is_branch := '1';
 857                 taken_branch := '1';
 858                 is_direct_branch := '1';
 859                 abs_branch := e_in.br_abs;
 860                 if ctrl.msr(MSR_BE) = '1' then
 861                     do_trace := '1';
 862                 end if;
 863             when OP_BC | OP_BCREG =>
 864                 -- read_data1 is CTR
 865                 -- for OP_BCREG, read_data2 is target register (CTR, LR or TAR)
 866                 -- If this instruction updates both CTR and LR, then it is
 867                 -- doubled; the first instruction decrements CTR and determines
 868                 -- whether the branch is taken, and the second does the
 869                 -- redirect and the LR update.
 870                 bo := insn_bo(e_in.insn);
 871                 bi := insn_bi(e_in.insn);
 872                 if e_in.second = '0' then
 873                     taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 874                 else
 875                     taken_branch := r.br_taken;
 876                 end if;
 877                 v.br_taken := taken_branch;
 878                 abs_branch := e_in.br_abs;
 879                 if e_in.repeat = '0' or e_in.second = '1' then
 880                     is_branch := '1';
 881                     if e_in.insn_type = OP_BC then
 882                         is_direct_branch := '1';
 883                     end if;
 884                     if ctrl.msr(MSR_BE) = '1' then
 885                         do_trace := '1';
 886                     end if;
 887                 end if;
 888
 889             when OP_RFID =>
 890                 v.e.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
 891                                   not a_in(MSR_LE) & not a_in(MSR_SF);
 892                 -- Can't use msr_copy here because the partial function MSR
 893                 -- bits should be left unchanged, not zeroed.
 894                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 895                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 896                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 897                 if a_in(MSR_PR) = '1' then
 898                     ctrl_tmp.msr(MSR_EE) <= '1';
 899                     ctrl_tmp.msr(MSR_IR) <= '1';
 900                     ctrl_tmp.msr(MSR_DR) <= '1';
 901                 end if;
 902                 -- mark this as a branch so CFAR gets updated
 903                 is_branch := '1';
 904                 taken_branch := '1';
 905                 abs_branch := '1';
 906                 if HAS_FPU then
 907                     v.fp_exception_next := fp_in.exception and
 908                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 909                 end if;
 910                 do_trace := '0';
 911
 912             when OP_CNTZ =>
 913                 v.e.valid := '0';
 914                 v.cntz_in_progress := '1';
 915                 v.busy := '1';
 916             when OP_ISEL =>
 917             when OP_CROP =>
 918             when OP_MCRXRX =>
 919             when OP_DARN =>
 920             when OP_MFMSR =>
 921             when OP_MFSPR =>
 922                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 923                     "=" & to_hstring(a_in);
 924                 if is_fast_spr(e_in.read_reg1) = '1' then
 925                     spr_val := a_in;
 926                     if decode_spr_num(e_in.insn) = SPR_XER then
 927                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 928                         spr_val(63 downto 32) := (others => '0');
 929                         spr_val(63-32) := xerc_in.so;
 930                         spr_val(63-33) := xerc_in.ov;
 931                         spr_val(63-34) := xerc_in.ca;
 932                         spr_val(63-35 downto 63-43) := "000000000";
 933                         spr_val(63-44) := xerc_in.ov32;
 934                         spr_val(63-45) := xerc_in.ca32;
 935                     end if;
 936                 else
 937                     spr_val := c_in;
 938                     case decode_spr_num(e_in.insn) is
 939                     when SPR_TB =>
 940                         spr_val := ctrl.tb;
 941                     when SPR_TBU =>
 942                         spr_val(63 downto 32) := (others => '0');
 943                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 944                     when SPR_DEC =>
 945                         spr_val := ctrl.dec;
 946                     when SPR_CFAR =>
 947                         spr_val := ctrl.cfar;
 948                     when SPR_PVR =>
 949                         spr_val(63 downto 32) := (others => '0');
 950                         spr_val(31 downto 0) := PVR_MICROWATT;
 951                     when 724 =>     -- LOG_ADDR SPR
 952                         spr_val := log_wr_addr & r.log_addr_spr;
 953                     when 725 =>     -- LOG_DATA SPR
 954                         spr_val := log_rd_data;
 955                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 956                     when others =>
 957                         -- mfspr from unimplemented SPRs should be a nop in
 958                         -- supervisor mode and a program interrupt for user mode
 959                         if is_fast_spr(e_in.read_reg1) = '0' and ctrl.msr(MSR_PR) = '1' then
 960                             illegal := '1';
 961                         end if;
 962                     end case;
 963                 end if;
 964                 spr_result <= spr_val;
 965
 966             when OP_MFCR =>
 967             when OP_MTCRF =>
 968             when OP_MTMSRD =>
 969                 if e_in.insn(16) = '1' then
 970                     -- just update EE and RI
 971                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 972                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 973                 else
 974                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 975                     -- and 63 (LE) (IBM bit numbering)
 976                     if e_in.is_32bit = '0' then
 977                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 978                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
 979                     end if;
 980                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
 981                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 982                     if c_in(MSR_PR) = '1' then
 983                         ctrl_tmp.msr(MSR_EE) <= '1';
 984                         ctrl_tmp.msr(MSR_IR) <= '1';
 985                         ctrl_tmp.msr(MSR_DR) <= '1';
 986                     end if;
 987                     if HAS_FPU then
 988                         v.fp_exception_next := fp_in.exception and
 989                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
 990                     end if;
 991                 end if;
 992             when OP_MTSPR =>
 993                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 994                     "=" & to_hstring(c_in);
 995                 if is_fast_spr(e_in.write_reg) then
 996                     if decode_spr_num(e_in.insn) = SPR_XER then
 997                         v.e.xerc.so := c_in(63-32);
 998                         v.e.xerc.ov := c_in(63-33);
 999                         v.e.xerc.ca := c_in(63-34);
1000                         v.e.xerc.ov32 := c_in(63-44);
1001                         v.e.xerc.ca32 := c_in(63-45);
1002                     end if;
1003                 else
1004                     -- slow spr
1005                     case decode_spr_num(e_in.insn) is
1006                     when SPR_DEC =>
1007                         ctrl_tmp.dec <= c_in;
1008                     when 724 =>     -- LOG_ADDR SPR
1009                         v.log_addr_spr := c_in(31 downto 0);
1010                     when others =>
1011                         -- mtspr to unimplemented SPRs should be a nop in
1012                         -- supervisor mode and a program interrupt for user mode
1013                         if ctrl.msr(MSR_PR) = '1' then
1014                             illegal := '1';
1015                         end if;
1016                     end case;
1017                 end if;
1018             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1019                 if e_in.output_carry = '1' then
1020                     set_carry(v.e, rotator_carry, rotator_carry);
1021                 end if;
1022             when OP_SETB =>
1023
1024             when OP_ISYNC =>
1025                 v.e.redirect := '1';
1026                 v.e.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1027
1028             when OP_ICBI =>
1029                 icache_inval <= '1';
1030
1031             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1032                 v.e.valid := '0';
1033                 v.mul_in_progress := '1';
1034                 v.busy := '1';
1035                 x_to_multiply.valid <= '1';
1036
1037             when OP_DIV | OP_DIVE | OP_MOD =>
1038                 v.e.valid := '0';
1039                 v.div_in_progress := '1';
1040                 v.busy := '1';
1041                 x_to_divider.valid <= '1';
1042
1043             when others =>
1044                 v.terminate := '1';
1045                 report "illegal";
1046             end case;
1047
1048             -- Mispredicted branches cause a redirect
1049             if is_branch = '1' then
1050                 if taken_branch = '1' then
1051                     ctrl_tmp.cfar <= e_in.nia;
1052                 end if;
1053                 if taken_branch = '1' then
1054                     v.e.br_offset := b_in;
1055                     v.e.abs_br := abs_branch;
1056                 else
1057                     v.e.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1058                 end if;
1059                 if taken_branch /= e_in.br_pred then
1060                     v.e.redirect := '1';
1061                 end if;
1062                 v.e.br_last := is_direct_branch;
1063                 v.e.br_taken := taken_branch;
1064             end if;
1065
1066         elsif valid_in = '1' and exception = '0' and illegal = '0' then
1067             -- instruction for other units, i.e. LDST
1068             if e_in.unit = LDST then
1069                 lv.valid := '1';
1070             elsif e_in.unit = NONE then
1071                 illegal := '1';
1072             elsif HAS_FPU and e_in.unit = FPU then
1073                 fv.valid := '1';
1074             end if;
1075             -- Handling an ITLB miss doesn't count as having executed an instruction
1076             if e_in.insn_type = OP_FETCH_FAILED then
1077                 do_trace := '0';
1078             end if;
1079         end if;
1080
1081         -- The following cases all occur when r.busy = 1 and therefore
1082         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1083         -- the cases above which depend on valid_in = 1.
1084         if r.cntz_in_progress = '1' then
1085             -- cnt[lt]z always takes two cycles
1086             v.e.valid := '1';
1087         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1088             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1089                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1090                 if r.mul_in_progress = '1' then
1091                     overflow := '0';
1092                 else
1093                     overflow := divider_to_x.overflow;
1094                 end if;
1095                 if r.mul_in_progress = '1' and current.oe = '1' then
1096                     -- have to wait until next cycle for overflow indication
1097                     v.mul_finish := '1';
1098                     v.busy := '1';
1099                 else
1100                     -- We must test oe because the RC update code in writeback
1101                     -- will use the xerc value to set CR0:SO so we must not clobber
1102                     -- xerc if OE wasn't set.
1103                     if current.oe = '1' then
1104                         v.e.xerc.ov := overflow;
1105                         v.e.xerc.ov32 := overflow;
1106                         if overflow = '1' then
1107                             v.e.xerc.so := '1';
1108                         end if;
1109                     end if;
1110                     v.e.valid := '1';
1111                 end if;
1112             else
1113                 v.busy := '1';
1114                 v.mul_in_progress := r.mul_in_progress;
1115                 v.div_in_progress := r.div_in_progress;
1116             end if;
1117         elsif r.mul_finish = '1' then
1118             hold_wr_data := '1';
1119             v.e.xerc.ov := multiply_to_x.overflow;
1120             v.e.xerc.ov32 := multiply_to_x.overflow;
1121             if multiply_to_x.overflow = '1' then
1122                 v.e.xerc.so := '1';
1123             end if;
1124             v.e.valid := '1';
1125         end if;
1126
1127         if illegal = '1' then
1128             exception := '1';
1129             v.e.intr_vec := 16#700#;
1130             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1131             -- set bit 44 to indicate we have an illegal
1132             v.e.srr1(47 - 44) := '1';
1133             report "illegal";
1134         end if;
1135
1136         v.e.interrupt := exception;
1137
1138         if do_trace = '1' then
1139             v.trace_next := '1';
1140         end if;
1141
1142         if interrupt_in = '1' then
1143             ctrl_tmp.msr(MSR_SF) <= '1';
1144             ctrl_tmp.msr(MSR_EE) <= '0';
1145             ctrl_tmp.msr(MSR_PR) <= '0';
1146             ctrl_tmp.msr(MSR_SE) <= '0';
1147             ctrl_tmp.msr(MSR_BE) <= '0';
1148             ctrl_tmp.msr(MSR_FP) <= '0';
1149             ctrl_tmp.msr(MSR_FE0) <= '0';
1150             ctrl_tmp.msr(MSR_FE1) <= '0';
1151             ctrl_tmp.msr(MSR_IR) <= '0';
1152             ctrl_tmp.msr(MSR_DR) <= '0';
1153             ctrl_tmp.msr(MSR_RI) <= '0';
1154             ctrl_tmp.msr(MSR_LE) <= '1';
1155             v.trace_next := '0';
1156             v.fp_exception_next := '0';
1157         end if;
1158
1159         if hold_wr_data = '0' then
1160             v.e.write_data := alu_result;
1161         else
1162             v.e.write_data := r.e.write_data;
1163         end if;
1164         v.e.write_reg := current.write_reg;
1165         v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
1166         v.e.rc := current.rc and v.e.valid and not exception;
1167         v.e.write_cr_data := write_cr_data;
1168         v.e.write_cr_mask := write_cr_mask;
1169         v.e.write_cr_enable := current.output_cr and v.e.valid and not exception;
1170         v.e.write_xerc_enable := current.output_xer and v.e.valid and not exception;
1171
1172         bypass_data.tag.valid <= current.instr_tag.valid and current.write_reg_enable and v.e.valid;
1173         bypass_data.tag.tag <= current.instr_tag.tag;
1174         bypass_data.data <= v.e.write_data;
1175
1176         bypass_cr_data.tag.valid <= current.instr_tag.valid and current.output_cr and v.e.valid;
1177         bypass_cr_data.tag.tag <= current.instr_tag.tag;
1178         for i in 0 to 7 loop
1179             if v.e.write_cr_mask(i) = '1' then
1180                 bypass_cr_data.data(i*4 + 3 downto i*4) <= v.e.write_cr_data(i*4 + 3 downto i*4);
1181             else
1182                 bypass_cr_data.data(i*4 + 3 downto i*4) <= cr_in(i*4 + 3 downto i*4);
1183             end if;
1184         end loop;
1185
1186         -- Outputs to loadstore1 (async)
1187         lv.op := e_in.insn_type;
1188         lv.nia := e_in.nia;
1189         lv.instr_tag := e_in.instr_tag;
1190         lv.addr1 := a_in;
1191         lv.addr2 := b_in;
1192         lv.data := c_in;
1193         lv.write_reg := e_in.write_reg;
1194         lv.length := e_in.data_len;
1195         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1196         lv.sign_extend := e_in.sign_extend;
1197         lv.update := e_in.update;
1198         lv.xerc := xerc_in;
1199         lv.reserve := e_in.reserve;
1200         lv.rc := e_in.rc;
1201         lv.insn := e_in.insn;
1202         -- decode l*cix and st*cix instructions here
1203         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1204             e_in.insn(5 downto 1) = "10101" then
1205             lv.ci := '1';
1206         end if;
1207         lv.virt_mode := ctrl.msr(MSR_DR);
1208         lv.priv_mode := not ctrl.msr(MSR_PR);
1209         lv.mode_32bit := not ctrl.msr(MSR_SF);
1210         lv.is_32bit := e_in.is_32bit;
1211         lv.repeat := e_in.repeat;
1212         lv.second := e_in.second;
1213
1214         -- Outputs to FPU
1215         fv.op := e_in.insn_type;
1216         fv.nia := e_in.nia;
1217         fv.insn := e_in.insn;
1218         fv.itag := e_in.instr_tag;
1219         fv.single := e_in.is_32bit;
1220         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1221         fv.fra := a_in;
1222         fv.frb := b_in;
1223         fv.frc := c_in;
1224         fv.frt := e_in.write_reg;
1225         fv.rc := e_in.rc;
1226         fv.out_cr := e_in.output_cr;
1227
1228         -- Update registers
1229         rin <= v;
1230
1231         -- update outputs
1232         l_out <= lv;
1233         e_out <= r.e;
1234         e_out.msr <= msr_copy(ctrl.msr);
1235         fp_out <= fv;
1236
1237         exception_log <= exception;
1238         irq_valid_log <= irq_valid;
1239     end process;
1240
1241     e1_log: if LOG_LENGTH > 0 generate
1242         signal log_data : std_ulogic_vector(14 downto 0);
1243     begin
1244         ex1_log : process(clk)
1245         begin
1246             if rising_edge(clk) then
1247                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1248                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1249                             exception_log &
1250                             irq_valid_log &
1251                             interrupt_in &
1252                             "000" &
1253                             r.e.write_enable &
1254                             r.e.valid &
1255                             (r.e.redirect or r.e.interrupt) &
1256                             r.busy &
1257                             flush_in;
1258             end if;
1259         end process;
1260         log_out <= log_data;
1261     end generate;
1262 end architecture behaviour;