execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40
  41         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  42
  43         icache_inval : out std_ulogic;
  44         terminate_out : out std_ulogic;
  45
  46         log_out : out std_ulogic_vector(14 downto 0);
  47         log_rd_addr : out std_ulogic_vector(31 downto 0);
  48         log_rd_data : in std_ulogic_vector(63 downto 0);
  49         log_wr_addr : in std_ulogic_vector(31 downto 0)
  50         );
  51 end entity execute1;
  52
  53 architecture behaviour of execute1 is
  54     type reg_type is record
  55         e : Execute1ToWritebackType;
  56         f : Execute1ToFetch1Type;
  57         busy: std_ulogic;
  58         terminate: std_ulogic;
  59         fp_exception_next : std_ulogic;
  60         trace_next : std_ulogic;
  61         prev_op : insn_type_t;
  62         lr_update : std_ulogic;
  63         next_lr : std_ulogic_vector(63 downto 0);
  64         mul_in_progress : std_ulogic;
  65         mul_finish : std_ulogic;
  66         div_in_progress : std_ulogic;
  67         cntz_in_progress : std_ulogic;
  68         slow_op_insn : insn_type_t;
  69         slow_op_dest : gpr_index_t;
  70         slow_op_rc : std_ulogic;
  71         slow_op_oe : std_ulogic;
  72         slow_op_xerc : xer_common_t;
  73         last_nia : std_ulogic_vector(63 downto 0);
  74         log_addr_spr : std_ulogic_vector(31 downto 0);
  75     end record;
  76     constant reg_type_init : reg_type :=
  77         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  78          busy => '0', lr_update => '0', terminate => '0',
  79          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL,
  80          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  81          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  82          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  83
  84     signal r, rin : reg_type;
  85
  86     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  87     signal cr_in : std_ulogic_vector(31 downto 0);
  88
  89     signal valid_in : std_ulogic;
  90     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  91     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  92     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  93     signal rot_sign_ext: std_ulogic;
  94     signal rotator_result: std_ulogic_vector(63 downto 0);
  95     signal rotator_carry: std_ulogic;
  96     signal logical_result: std_ulogic_vector(63 downto 0);
  97     signal countzero_result: std_ulogic_vector(63 downto 0);
  98
  99     -- multiply signals
 100     signal x_to_multiply: MultiplyInputType;
 101     signal multiply_to_x: MultiplyOutputType;
 102
 103     -- divider signals
 104     signal x_to_divider: Execute1ToDividerType;
 105     signal divider_to_x: DividerToExecute1Type;
 106
 107     -- random number generator signals
 108     signal random_raw  : std_ulogic_vector(63 downto 0);
 109     signal random_cond : std_ulogic_vector(63 downto 0);
 110     signal random_err  : std_ulogic;
 111
 112     -- signals for logging
 113     signal exception_log : std_ulogic;
 114     signal irq_valid_log : std_ulogic;
 115
 116     type privilege_level is (USER, SUPER);
 117     type op_privilege_array is array(insn_type_t) of privilege_level;
 118     constant op_privilege: op_privilege_array := (
 119         OP_ATTN => SUPER,
 120         OP_MFMSR => SUPER,
 121         OP_MTMSRD => SUPER,
 122         OP_RFID => SUPER,
 123         OP_TLBIE => SUPER,
 124         others => USER
 125         );
 126
 127     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 128         return boolean is
 129     begin
 130         if op_privilege(op) = SUPER then
 131             return true;
 132         elsif op = OP_MFSPR or op = OP_MTSPR then
 133             return insn(20) = '1';
 134         else
 135             return false;
 136         end if;
 137     end;
 138
 139     procedure set_carry(e: inout Execute1ToWritebackType;
 140                         carry32 : in std_ulogic;
 141                         carry : in std_ulogic) is
 142     begin
 143         e.xerc.ca32 := carry32;
 144         e.xerc.ca := carry;
 145         e.write_xerc_enable := '1';
 146     end;
 147
 148     procedure set_ov(e: inout Execute1ToWritebackType;
 149                      ov   : in std_ulogic;
 150                      ov32 : in std_ulogic) is
 151     begin
 152         e.xerc.ov32 := ov32;
 153         e.xerc.ov := ov;
 154         if ov = '1' then
 155             e.xerc.so := '1';
 156         end if;
 157         e.write_xerc_enable := '1';
 158     end;
 159
 160     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 161                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 162     begin
 163         return (ca xor msb_r) and not (msb_a xor msb_b);
 164     end;
 165
 166     function decode_input_carry(ic : carry_in_t;
 167                                 xerc : xer_common_t) return std_ulogic is
 168     begin
 169         case ic is
 170         when ZERO =>
 171             return '0';
 172         when CA =>
 173             return xerc.ca;
 174         when OV =>
 175             return xerc.ov;
 176         when ONE =>
 177             return '1';
 178         end case;
 179     end;
 180
 181     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 182         return std_ulogic_vector is
 183         variable msr_out: std_ulogic_vector(63 downto 0);
 184     begin
 185         -- ISA says this:
 186         --  Defined MSR bits are classified as either full func-
 187         --  tion or partial function. Full function MSR bits are
 188         --  saved in SRR1 or HSRR1 when an interrupt other
 189         --  than a System Call Vectored interrupt occurs and
 190         --  restored by rfscv, rfid, or hrfid, while partial func-
 191         --  tion MSR bits are not saved or restored.
 192         --  Full function MSR bits lie in the range 0:32, 37:41, and
 193         --  48:63, and partial function MSR bits lie in the range
 194         --  33:36 and 42:47. (Note this is IBM bit numbering).
 195         msr_out := (others => '0');
 196         msr_out(63 downto 31) := msr(63 downto 31);
 197         msr_out(26 downto 22) := msr(26 downto 22);
 198         msr_out(15 downto 0)  := msr(15 downto 0);
 199         return msr_out;
 200     end;
 201
 202     -- Tell vivado to keep the hierarchy for the random module so that the
 203     -- net names in the xdc file match.
 204     attribute keep_hierarchy : string;
 205     attribute keep_hierarchy of random_0 : label is "yes";
 206
 207 begin
 208
 209     rotator_0: entity work.rotator
 210         port map (
 211             rs => c_in,
 212             ra => a_in,
 213             shift => b_in(6 downto 0),
 214             insn => e_in.insn,
 215             is_32bit => e_in.is_32bit,
 216             right_shift => right_shift,
 217             arith => e_in.is_signed,
 218             clear_left => rot_clear_left,
 219             clear_right => rot_clear_right,
 220             sign_ext_rs => rot_sign_ext,
 221             result => rotator_result,
 222             carry_out => rotator_carry
 223             );
 224
 225     logical_0: entity work.logical
 226         port map (
 227             rs => c_in,
 228             rb => b_in,
 229             op => e_in.insn_type,
 230             invert_in => e_in.invert_a,
 231             invert_out => e_in.invert_out,
 232             result => logical_result,
 233             datalen => e_in.data_len
 234             );
 235
 236     countzero_0: entity work.zero_counter
 237         port map (
 238             clk => clk,
 239             rs => c_in,
 240             count_right => e_in.insn(10),
 241             is_32bit => e_in.is_32bit,
 242             result => countzero_result
 243             );
 244
 245     multiply_0: entity work.multiply
 246         port map (
 247             clk => clk,
 248             m_in => x_to_multiply,
 249             m_out => multiply_to_x
 250             );
 251
 252     divider_0: entity work.divider
 253         port map (
 254             clk => clk,
 255             rst => rst,
 256             d_in => x_to_divider,
 257             d_out => divider_to_x
 258             );
 259
 260     random_0: entity work.random
 261         port map (
 262             clk => clk,
 263             data => random_cond,
 264             raw => random_raw,
 265             err => random_err
 266             );
 267
 268     dbg_msr_out <= ctrl.msr;
 269     log_rd_addr <= r.log_addr_spr;
 270
 271     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 272     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 273     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 274
 275     busy_out <= l_in.busy or r.busy or fp_in.busy;
 276     valid_in <= e_in.valid and not busy_out;
 277
 278     terminate_out <= r.terminate;
 279
 280     execute1_0: process(clk)
 281     begin
 282         if rising_edge(clk) then
 283             if rst = '1' then
 284                 r <= reg_type_init;
 285                 ctrl.tb <= (others => '0');
 286                 ctrl.dec <= (others => '0');
 287                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 288                 ctrl.irq_state <= WRITE_SRR0;
 289             else
 290                 r <= rin;
 291                 ctrl <= ctrl_tmp;
 292                 assert not (r.lr_update = '1' and valid_in = '1')
 293                     report "LR update collision with valid in EX1"
 294                     severity failure;
 295                 if r.lr_update = '1' then
 296                     report "LR update to " & to_hstring(r.next_lr);
 297                 end if;
 298             end if;
 299         end if;
 300     end process;
 301
 302     execute1_1: process(all)
 303         variable v : reg_type;
 304         variable a_inv : std_ulogic_vector(63 downto 0);
 305         variable result : std_ulogic_vector(63 downto 0);
 306         variable newcrf : std_ulogic_vector(3 downto 0);
 307         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 308         variable result_en : std_ulogic;
 309         variable crnum : crnum_t;
 310         variable crbit : integer range 0 to 31;
 311         variable scrnum : crnum_t;
 312         variable lo, hi : integer;
 313         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 314         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 315         variable bo, bi : std_ulogic_vector(4 downto 0);
 316         variable bf, bfa : std_ulogic_vector(2 downto 0);
 317         variable cr_op : std_ulogic_vector(9 downto 0);
 318         variable cr_operands : std_ulogic_vector(1 downto 0);
 319         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 320         variable btnum, banum, bbnum : integer range 0 to 31;
 321         variable crresult : std_ulogic;
 322         variable l : std_ulogic;
 323         variable next_nia : std_ulogic_vector(63 downto 0);
 324         variable carry_32, carry_64 : std_ulogic;
 325         variable sign1, sign2 : std_ulogic;
 326         variable abs1, abs2 : signed(63 downto 0);
 327         variable overflow : std_ulogic;
 328         variable zerohi, zerolo : std_ulogic;
 329         variable msb_a, msb_b : std_ulogic;
 330         variable a_lt : std_ulogic;
 331         variable lv : Execute1ToLoadstore1Type;
 332         variable irq_valid : std_ulogic;
 333         variable exception : std_ulogic;
 334         variable exception_nextpc : std_ulogic;
 335         variable trapval : std_ulogic_vector(4 downto 0);
 336         variable illegal : std_ulogic;
 337         variable is_branch : std_ulogic;
 338         variable taken_branch : std_ulogic;
 339         variable abs_branch : std_ulogic;
 340         variable spr_val : std_ulogic_vector(63 downto 0);
 341         variable addend : std_ulogic_vector(127 downto 0);
 342         variable do_trace : std_ulogic;
 343         variable fv : Execute1ToFPUType;
 344     begin
 345         result := (others => '0');
 346         sum_with_carry := (others => '0');
 347         result_en := '0';
 348         newcrf := (others => '0');
 349         is_branch := '0';
 350         taken_branch := '0';
 351         abs_branch := '0';
 352
 353         v := r;
 354         v.e := Execute1ToWritebackInit;
 355         lv := Execute1ToLoadstore1Init;
 356         v.f.redirect := '0';
 357         fv := Execute1ToFPUInit;
 358
 359         -- XER forwarding. To avoid having to track XER hazards, we use
 360         -- the previously latched value.  Since the XER common bits
 361         -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 362         -- handled here, we can just forward the result being sent to
 363         -- writeback.
 364         if r.e.write_xerc_enable = '1' then
 365             v.e.xerc := r.e.xerc;
 366         else
 367             v.e.xerc := e_in.xerc;
 368         end if;
 369
 370         -- CR forwarding
 371         cr_in <= e_in.cr;
 372         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 373             for i in 0 to 7 loop
 374                 if r.e.write_cr_mask(i) = '1' then
 375                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 376                 end if;
 377             end loop;
 378         end if;
 379
 380         v.lr_update := '0';
 381         v.mul_in_progress := '0';
 382         v.div_in_progress := '0';
 383         v.cntz_in_progress := '0';
 384         v.mul_finish := '0';
 385
 386         -- Main adder
 387         if e_in.invert_a = '0' then
 388             a_inv := a_in;
 389         else
 390             a_inv := not a_in;
 391         end if;
 392         sum_with_carry := ppc_adde(a_inv, b_in,
 393                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 394
 395         -- signals to multiply and divide units
 396         sign1 := '0';
 397         sign2 := '0';
 398         if e_in.is_signed = '1' then
 399             if e_in.is_32bit = '1' then
 400                 sign1 := a_in(31);
 401                 sign2 := b_in(31);
 402             else
 403                 sign1 := a_in(63);
 404                 sign2 := b_in(63);
 405             end if;
 406         end if;
 407         -- take absolute values
 408         if sign1 = '0' then
 409             abs1 := signed(a_in);
 410         else
 411             abs1 := - signed(a_in);
 412         end if;
 413         if sign2 = '0' then
 414             abs2 := signed(b_in);
 415         else
 416             abs2 := - signed(b_in);
 417         end if;
 418
 419         x_to_multiply <= MultiplyInputInit;
 420         x_to_multiply.is_32bit <= e_in.is_32bit;
 421
 422         x_to_divider <= Execute1ToDividerInit;
 423         x_to_divider.is_signed <= e_in.is_signed;
 424         x_to_divider.is_32bit <= e_in.is_32bit;
 425         if e_in.insn_type = OP_MOD then
 426             x_to_divider.is_modulus <= '1';
 427         end if;
 428
 429         addend := (others => '0');
 430         if e_in.insn(26) = '0' then
 431             -- integer multiply-add, major op 4 (if it is a multiply)
 432             addend(63 downto 0) := c_in;
 433             if e_in.is_signed = '1' then
 434                 addend(127 downto 64) := (others => c_in(63));
 435             end if;
 436         end if;
 437         if (sign1 xor sign2) = '1' then
 438             addend := not addend;
 439         end if;
 440
 441         x_to_multiply.not_result <= sign1 xor sign2;
 442         x_to_multiply.addend <= addend;
 443         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 444         if e_in.is_32bit = '0' then
 445             -- 64-bit forms
 446             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 447             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 448             if e_in.insn_type = OP_DIVE then
 449                 x_to_divider.is_extended <= '1';
 450             end if;
 451             x_to_divider.dividend <= std_ulogic_vector(abs1);
 452             x_to_divider.divisor <= std_ulogic_vector(abs2);
 453         else
 454             -- 32-bit forms
 455             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 456             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 457             x_to_divider.is_extended <= '0';
 458             if e_in.insn_type = OP_DIVE then   -- extended forms
 459                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 460             else
 461                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 462             end if;
 463             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 464         end if;
 465
 466         ctrl_tmp <= ctrl;
 467         -- FIXME: run at 512MHz not core freq
 468         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 469         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 470
 471         irq_valid := '0';
 472         if ctrl.msr(MSR_EE) = '1' then
 473             if ctrl.dec(63) = '1' then
 474                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 475                 report "IRQ valid: DEC";
 476                 irq_valid := '1';
 477             elsif ext_irq_in = '1' then
 478                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 479                 report "IRQ valid: External";
 480                 irq_valid := '1';
 481             end if;
 482         end if;
 483
 484         v.terminate := '0';
 485         icache_inval <= '0';
 486         v.busy := '0';
 487         -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
 488         v.f.virt_mode := ctrl.msr(MSR_IR);
 489         v.f.priv_mode := not ctrl.msr(MSR_PR);
 490         v.f.big_endian := not ctrl.msr(MSR_LE);
 491         v.f.mode_32bit := not ctrl.msr(MSR_SF);
 492
 493         -- Next insn adder used in a couple of places
 494         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 495
 496         -- rotator control signals
 497         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 498         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 499         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 500         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 501
 502         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 503         ctrl_tmp.irq_state <= WRITE_SRR0;
 504         exception := '0';
 505         illegal := '0';
 506         exception_nextpc := '0';
 507         v.e.exc_write_enable := '0';
 508         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 509         if valid_in = '1' then
 510             v.e.exc_write_data := e_in.nia;
 511             v.last_nia := e_in.nia;
 512         else
 513             v.e.exc_write_data := r.last_nia;
 514         end if;
 515
 516         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 517
 518         do_trace := valid_in and ctrl.msr(MSR_SE);
 519         if valid_in = '1' then
 520             v.prev_op := e_in.insn_type;
 521         end if;
 522
 523         if ctrl.irq_state = WRITE_SRR1 then
 524             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 525             v.e.exc_write_data := ctrl.srr1;
 526             v.e.exc_write_enable := '1';
 527             ctrl_tmp.msr(MSR_SF) <= '1';
 528             ctrl_tmp.msr(MSR_EE) <= '0';
 529             ctrl_tmp.msr(MSR_PR) <= '0';
 530             ctrl_tmp.msr(MSR_SE) <= '0';
 531             ctrl_tmp.msr(MSR_BE) <= '0';
 532             ctrl_tmp.msr(MSR_FP) <= '0';
 533             ctrl_tmp.msr(MSR_FE0) <= '0';
 534             ctrl_tmp.msr(MSR_FE1) <= '0';
 535             ctrl_tmp.msr(MSR_IR) <= '0';
 536             ctrl_tmp.msr(MSR_DR) <= '0';
 537             ctrl_tmp.msr(MSR_RI) <= '0';
 538             ctrl_tmp.msr(MSR_LE) <= '1';
 539             v.e.valid := '1';
 540             v.trace_next := '0';
 541             v.fp_exception_next := '0';
 542             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 543
 544         elsif valid_in = '1' and e_in.second = '0' and
 545             ((HAS_FPU and r.fp_exception_next = '1') or r.trace_next = '1') then
 546             if HAS_FPU and r.fp_exception_next = '1' then
 547                 -- This is used for FP-type program interrupts that
 548                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 549                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 550                 ctrl_tmp.srr1(63 - 43) <= '1';
 551                 ctrl_tmp.srr1(63 - 47) <= '1';
 552             else
 553                 -- Generate a trace interrupt rather than executing the next instruction
 554                 -- or taking any asynchronous interrupt
 555                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#d00#, 64));
 556                 ctrl_tmp.srr1(63 - 33) <= '1';
 557                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 558                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 559                     ctrl_tmp.srr1(63 - 35) <= '1';
 560                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 561                     ctrl_tmp.srr1(63 - 36) <= '1';
 562                 end if;
 563             end if;
 564             exception := '1';
 565
 566         elsif irq_valid = '1' and valid_in = '1' and e_in.second = '0' then
 567             -- we need two cycles to write srr0 and 1
 568             -- will need more when we have to write HEIR
 569             -- Don't deliver the interrupt until we have a valid instruction
 570             -- coming in, so we have a valid NIA to put in SRR0.
 571             exception := '1';
 572
 573         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 574             instr_is_privileged(e_in.insn_type, e_in.insn) then
 575             -- generate a program interrupt
 576             exception := '1';
 577             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 578             -- set bit 45 to indicate privileged instruction type interrupt
 579             ctrl_tmp.srr1(63 - 45) <= '1';
 580             report "privileged instruction";
 581
 582         elsif not HAS_FPU and valid_in = '1' and e_in.fac = FPU then
 583             -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 584             illegal := '1';
 585
 586         elsif HAS_FPU and valid_in = '1' and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 587             -- generate a floating-point unavailable interrupt
 588             exception := '1';
 589             v.f.redirect_nia := std_logic_vector(to_unsigned(16#800#, 64));
 590             report "FP unavailable interrupt";
 591
 592         elsif valid_in = '1' and e_in.unit = ALU then
 593
 594             report "execute nia " & to_hstring(e_in.nia);
 595
 596             v.e.valid := '1';
 597             v.e.write_reg := e_in.write_reg;
 598             v.slow_op_insn := e_in.insn_type;
 599             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 600             v.slow_op_rc := e_in.rc;
 601             v.slow_op_oe := e_in.oe;
 602             v.slow_op_xerc := v.e.xerc;
 603
 604             case_0: case e_in.insn_type is
 605
 606             when OP_ILLEGAL =>
 607                 -- we need two cycles to write srr0 and 1
 608                 -- will need more when we have to write HEIR
 609                 illegal := '1';
 610             when OP_SC =>
 611                 -- check bit 1 of the instruction is 1 so we know this is sc;
 612                 -- 0 would mean scv, so generate an illegal instruction interrupt
 613                 -- we need two cycles to write srr0 and 1
 614                 if e_in.insn(1) = '1' then
 615                     exception := '1';
 616                     exception_nextpc := '1';
 617                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 618                     report "sc";
 619                 else
 620                     illegal := '1';
 621                 end if;
 622             when OP_ATTN =>
 623                 -- check bits 1-10 of the instruction to make sure it's attn
 624                 -- if not then it is illegal
 625                 if e_in.insn(10 downto 1) = "0100000000" then
 626                     v.terminate := '1';
 627                     report "ATTN";
 628                 else
 629                     illegal := '1';
 630                 end if;
 631             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 632                 -- Do nothing
 633             when OP_ADD | OP_CMP | OP_TRAP =>
 634                 result := sum_with_carry(63 downto 0);
 635                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 636                 carry_64 := sum_with_carry(64);
 637                 if e_in.insn_type = OP_ADD then
 638                     if e_in.output_carry = '1' then
 639                         if e_in.input_carry /= OV then
 640                             set_carry(v.e, carry_32, carry_64);
 641                         else
 642                             v.e.xerc.ov := carry_64;
 643                             v.e.xerc.ov32 := carry_32;
 644                             v.e.write_xerc_enable := '1';
 645                         end if;
 646                     end if;
 647                     if e_in.oe = '1' then
 648                         set_ov(v.e,
 649                                calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 650                                calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 651                     end if;
 652                     result_en := '1';
 653                 else
 654                     -- trap, CMP and CMPL instructions
 655                     -- Note, we have done RB - RA, not RA - RB
 656                     if e_in.insn_type = OP_CMP then
 657                         l := insn_l(e_in.insn);
 658                     else
 659                         l := not e_in.is_32bit;
 660                     end if;
 661                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 662                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 663                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 664                         -- values are equal
 665                         trapval := "00100";
 666                     else
 667                         if l = '1' then
 668                             -- 64-bit comparison
 669                             msb_a := a_in(63);
 670                             msb_b := b_in(63);
 671                         else
 672                             -- 32-bit comparison
 673                             msb_a := a_in(31);
 674                             msb_b := b_in(31);
 675                         end if;
 676                         if msb_a /= msb_b then
 677                             -- Subtraction might overflow, but
 678                             -- comparison is clear from MSB difference.
 679                             -- for signed, 0 is greater; for unsigned, 1 is greater
 680                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 681                         else
 682                             -- Subtraction cannot overflow since MSBs are equal.
 683                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 684                             a_lt := (not l and carry_32) or (l and carry_64);
 685                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 686                         end if;
 687                     end if;
 688                     if e_in.insn_type = OP_CMP then
 689                         if e_in.is_signed = '1' then
 690                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 691                         else
 692                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 693                         end if;
 694                         bf := insn_bf(e_in.insn);
 695                         crnum := to_integer(unsigned(bf));
 696                         v.e.write_cr_enable := '1';
 697                         v.e.write_cr_mask := num_to_fxm(crnum);
 698                         for i in 0 to 7 loop
 699                             lo := i*4;
 700                             hi := lo + 3;
 701                             v.e.write_cr_data(hi downto lo) := newcrf;
 702                         end loop;
 703                     else
 704                         -- trap instructions (tw, twi, td, tdi)
 705                         v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 706                         -- set bit 46 to say trap occurred
 707                         ctrl_tmp.srr1(63 - 46) <= '1';
 708                         if or (trapval and insn_to(e_in.insn)) = '1' then
 709                             -- generate trap-type program interrupt
 710                             exception := '1';
 711                             report "trap";
 712                         end if;
 713                     end if;
 714                 end if;
 715             when OP_ADDG6S =>
 716                 result := (others => '0');
 717                 for i in 0 to 14 loop
 718                     lo := i * 4;
 719                     hi := (i + 1) * 4;
 720                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 721                         result(lo + 3 downto lo) := "0110";
 722                     end if;
 723                 end loop;
 724                 if sum_with_carry(64) = '0' then
 725                     result(63 downto 60) := "0110";
 726                 end if;
 727                 result_en := '1';
 728             when OP_CMPRB =>
 729                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 730                 bf := insn_bf(e_in.insn);
 731                 crnum := to_integer(unsigned(bf));
 732                 v.e.write_cr_enable := '1';
 733                 v.e.write_cr_mask := num_to_fxm(crnum);
 734                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 735                                      newcrf & newcrf & newcrf & newcrf;
 736             when OP_CMPEQB =>
 737                 newcrf := ppc_cmpeqb(a_in, b_in);
 738                 bf := insn_bf(e_in.insn);
 739                 crnum := to_integer(unsigned(bf));
 740                 v.e.write_cr_enable := '1';
 741                 v.e.write_cr_mask := num_to_fxm(crnum);
 742                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 743                                      newcrf & newcrf & newcrf & newcrf;
 744             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 745                     OP_BPERM | OP_BCD =>
 746                 result := logical_result;
 747                 result_en := '1';
 748             when OP_B =>
 749                 is_branch := '1';
 750                 taken_branch := '1';
 751                 abs_branch := insn_aa(e_in.insn);
 752                 if ctrl.msr(MSR_BE) = '1' then
 753                     do_trace := '1';
 754                 end if;
 755             when OP_BC =>
 756                 -- read_data1 is CTR
 757                 bo := insn_bo(e_in.insn);
 758                 bi := insn_bi(e_in.insn);
 759                 if bo(4-2) = '0' then
 760                     result := std_ulogic_vector(unsigned(a_in) - 1);
 761                     result_en := '1';
 762                     v.e.write_reg := fast_spr_num(SPR_CTR);
 763                 end if;
 764                 is_branch := '1';
 765                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 766                 abs_branch := insn_aa(e_in.insn);
 767                 if ctrl.msr(MSR_BE) = '1' then
 768                     do_trace := '1';
 769                 end if;
 770             when OP_BCREG =>
 771                 -- read_data1 is CTR
 772                 -- read_data2 is target register (CTR, LR or TAR)
 773                 bo := insn_bo(e_in.insn);
 774                 bi := insn_bi(e_in.insn);
 775                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 776                     result := std_ulogic_vector(unsigned(a_in) - 1);
 777                     result_en := '1';
 778                     v.e.write_reg := fast_spr_num(SPR_CTR);
 779                 end if;
 780                 is_branch := '1';
 781                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 782                 abs_branch := '1';
 783                 if ctrl.msr(MSR_BE) = '1' then
 784                     do_trace := '1';
 785                 end if;
 786
 787             when OP_RFID =>
 788                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 789                 v.f.priv_mode := not a_in(MSR_PR);
 790                 v.f.big_endian := not a_in(MSR_LE);
 791                 v.f.mode_32bit := not a_in(MSR_SF);
 792                 -- Can't use msr_copy here because the partial function MSR
 793                 -- bits should be left unchanged, not zeroed.
 794                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 795                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 796                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 797                 if a_in(MSR_PR) = '1' then
 798                     ctrl_tmp.msr(MSR_EE) <= '1';
 799                     ctrl_tmp.msr(MSR_IR) <= '1';
 800                     ctrl_tmp.msr(MSR_DR) <= '1';
 801                 end if;
 802                 -- mark this as a branch so CFAR gets updated
 803                 is_branch := '1';
 804                 taken_branch := '1';
 805                 abs_branch := '1';
 806                 if HAS_FPU then
 807                     v.fp_exception_next := fp_in.exception and
 808                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 809                 end if;
 810                 do_trace := '0';
 811
 812             when OP_CNTZ =>
 813                 v.e.valid := '0';
 814                 v.cntz_in_progress := '1';
 815                 v.busy := '1';
 816             when OP_ISEL =>
 817                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 818                 if cr_in(31-crbit) = '1' then
 819                     result := a_in;
 820                 else
 821                     result := b_in;
 822                 end if;
 823                 result_en := '1';
 824             when OP_CROP =>
 825                 cr_op := insn_cr(e_in.insn);
 826                 report "CR OP " & to_hstring(cr_op);
 827                 if cr_op(0) = '0' then -- MCRF
 828                     bf := insn_bf(e_in.insn);
 829                     bfa := insn_bfa(e_in.insn);
 830                     v.e.write_cr_enable := '1';
 831                     crnum := to_integer(unsigned(bf));
 832                     scrnum := to_integer(unsigned(bfa));
 833                     v.e.write_cr_mask := num_to_fxm(crnum);
 834                     for i in 0 to 7 loop
 835                         lo := (7-i)*4;
 836                         hi := lo + 3;
 837                         if i = scrnum then
 838                             newcrf := cr_in(hi downto lo);
 839                         end if;
 840                     end loop;
 841                     for i in 0 to 7 loop
 842                         lo := i*4;
 843                         hi := lo + 3;
 844                         v.e.write_cr_data(hi downto lo) := newcrf;
 845                     end loop;
 846                 else
 847                     v.e.write_cr_enable := '1';
 848                     bt := insn_bt(e_in.insn);
 849                     ba := insn_ba(e_in.insn);
 850                     bb := insn_bb(e_in.insn);
 851                     btnum := 31 - to_integer(unsigned(bt));
 852                     banum := 31 - to_integer(unsigned(ba));
 853                     bbnum := 31 - to_integer(unsigned(bb));
 854                     -- Bits 5-8 of cr_op give the truth table of the requested
 855                     -- logical operation
 856                     cr_operands := cr_in(banum) & cr_in(bbnum);
 857                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 858                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 859                     for i in 0 to 31 loop
 860                         if i = btnum then
 861                             v.e.write_cr_data(i) := crresult;
 862                         else
 863                             v.e.write_cr_data(i) := cr_in(i);
 864                         end if;
 865                     end loop;
 866                 end if;
 867             when OP_MCRXRX =>
 868                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 869                 bf := insn_bf(e_in.insn);
 870                 crnum := to_integer(unsigned(bf));
 871                 v.e.write_cr_enable := '1';
 872                 v.e.write_cr_mask := num_to_fxm(crnum);
 873                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 874                                      newcrf & newcrf & newcrf & newcrf;
 875             when OP_DARN =>
 876                 if random_err = '0' then
 877                     case e_in.insn(17 downto 16) is
 878                         when "00" =>
 879                             result := x"00000000" & random_cond(31 downto 0);
 880                         when "10" =>
 881                             result := random_raw;
 882                         when others =>
 883                             result := random_cond;
 884                     end case;
 885                 else
 886                     result := (others => '1');
 887                 end if;
 888                 result_en := '1';
 889             when OP_MFMSR =>
 890                 result := ctrl.msr;
 891                 result_en := '1';
 892             when OP_MFSPR =>
 893                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 894                     "=" & to_hstring(a_in);
 895                 result_en := '1';
 896                 if is_fast_spr(e_in.read_reg1) then
 897                     result := a_in;
 898                     if decode_spr_num(e_in.insn) = SPR_XER then
 899                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 900                         result(63 downto 32) := (others => '0');
 901                         result(63-32) := v.e.xerc.so;
 902                         result(63-33) := v.e.xerc.ov;
 903                         result(63-34) := v.e.xerc.ca;
 904                         result(63-35 downto 63-43) := "000000000";
 905                         result(63-44) := v.e.xerc.ov32;
 906                         result(63-45) := v.e.xerc.ca32;
 907                     end if;
 908                 else
 909                     spr_val := c_in;
 910                     case decode_spr_num(e_in.insn) is
 911                     when SPR_TB =>
 912                         spr_val := ctrl.tb;
 913                     when SPR_TBU =>
 914                         spr_val(63 downto 32) := (others => '0');
 915                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 916                     when SPR_DEC =>
 917                         spr_val := ctrl.dec;
 918                     when SPR_CFAR =>
 919                         spr_val := ctrl.cfar;
 920                     when SPR_PVR =>
 921                         spr_val(63 downto 32) := (others => '0');
 922                         spr_val(31 downto 0) := PVR_MICROWATT;
 923                     when 724 =>     -- LOG_ADDR SPR
 924                         spr_val := log_wr_addr & r.log_addr_spr;
 925                     when 725 =>     -- LOG_DATA SPR
 926                         spr_val := log_rd_data;
 927                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 928                     when others =>
 929                         -- mfspr from unimplemented SPRs should be a nop in
 930                         -- supervisor mode and a program interrupt for user mode
 931                         if ctrl.msr(MSR_PR) = '1' then
 932                             illegal := '1';
 933                         end if;
 934                     end case;
 935                     result := spr_val;
 936                 end if;
 937             when OP_MFCR =>
 938                 if e_in.insn(20) = '0' then
 939                     -- mfcr
 940                     result := x"00000000" & cr_in;
 941                 else
 942                     -- mfocrf
 943                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 944                     result := (others => '0');
 945                     for i in 0 to 7 loop
 946                         lo := (7-i)*4;
 947                         hi := lo + 3;
 948                         if crnum = i then
 949                             result(hi downto lo) := cr_in(hi downto lo);
 950                         end if;
 951                     end loop;
 952                 end if;
 953                 result_en := '1';
 954             when OP_MTCRF =>
 955                 v.e.write_cr_enable := '1';
 956                 if e_in.insn(20) = '0' then
 957                     -- mtcrf
 958                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 959                 else
 960                     -- mtocrf: We require one hot priority encoding here
 961                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 962                     v.e.write_cr_mask := num_to_fxm(crnum);
 963                 end if;
 964                 v.e.write_cr_data := c_in(31 downto 0);
 965             when OP_MTMSRD =>
 966                 if e_in.insn(16) = '1' then
 967                     -- just update EE and RI
 968                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 969                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 970                 else
 971                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 972                     -- and 63 (LE) (IBM bit numbering)
 973                     if e_in.is_32bit = '0' then
 974                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 975                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
 976                     end if;
 977                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
 978                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 979                     if c_in(MSR_PR) = '1' then
 980                         ctrl_tmp.msr(MSR_EE) <= '1';
 981                         ctrl_tmp.msr(MSR_IR) <= '1';
 982                         ctrl_tmp.msr(MSR_DR) <= '1';
 983                     end if;
 984                     if HAS_FPU then
 985                         v.fp_exception_next := fp_in.exception and
 986                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
 987                     end if;
 988                 end if;
 989             when OP_MTSPR =>
 990                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 991                     "=" & to_hstring(c_in);
 992                 if is_fast_spr(e_in.write_reg) then
 993                     result := c_in;
 994                     result_en := '1';
 995                     if decode_spr_num(e_in.insn) = SPR_XER then
 996                         v.e.xerc.so := c_in(63-32);
 997                         v.e.xerc.ov := c_in(63-33);
 998                         v.e.xerc.ca := c_in(63-34);
 999                         v.e.xerc.ov32 := c_in(63-44);
1000                         v.e.xerc.ca32 := c_in(63-45);
1001                         v.e.write_xerc_enable := '1';
1002                     end if;
1003                 else
1004                     -- slow spr
1005                     case decode_spr_num(e_in.insn) is
1006                     when SPR_DEC =>
1007                         ctrl_tmp.dec <= c_in;
1008                     when 724 =>     -- LOG_ADDR SPR
1009                         v.log_addr_spr := c_in(31 downto 0);
1010                     when others =>
1011                         -- mtspr to unimplemented SPRs should be a nop in
1012                         -- supervisor mode and a program interrupt for user mode
1013                         if ctrl.msr(MSR_PR) = '1' then
1014                             illegal := '1';
1015                         end if;
1016                     end case;
1017                 end if;
1018             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1019                 result := rotator_result;
1020                 if e_in.output_carry = '1' then
1021                     set_carry(v.e, rotator_carry, rotator_carry);
1022                 end if;
1023                 result_en := '1';
1024             when OP_SETB =>
1025                 bfa := insn_bfa(e_in.insn);
1026                 crbit := to_integer(unsigned(bfa)) * 4;
1027                 result := (others => '0');
1028                 if cr_in(31 - crbit) = '1' then
1029                     result := (others => '1');
1030                 elsif cr_in(30 - crbit) = '1' then
1031                     result(0) := '1';
1032                 end if;
1033
1034             when OP_ISYNC =>
1035                 v.f.redirect := '1';
1036                 v.f.redirect_nia := next_nia;
1037
1038             when OP_ICBI =>
1039                 icache_inval <= '1';
1040
1041             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1042                 v.e.valid := '0';
1043                 v.mul_in_progress := '1';
1044                 v.busy := '1';
1045                 x_to_multiply.valid <= '1';
1046
1047             when OP_DIV | OP_DIVE | OP_MOD =>
1048                 v.e.valid := '0';
1049                 v.div_in_progress := '1';
1050                 v.busy := '1';
1051                 x_to_divider.valid <= '1';
1052
1053             when others =>
1054                 v.terminate := '1';
1055                 report "illegal";
1056             end case;
1057
1058             v.e.rc := e_in.rc and valid_in;
1059
1060             -- Mispredicted branches cause a redirect
1061             if is_branch = '1' then
1062                 if taken_branch = '1' then
1063                     ctrl_tmp.cfar <= e_in.nia;
1064                 end if;
1065                 if e_in.br_pred = '0' then
1066                     if abs_branch = '1' then
1067                         v.f.redirect_nia := b_in;
1068                     else
1069                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
1070                     end if;
1071                 else
1072                     v.f.redirect_nia := next_nia;
1073                 end if;
1074                 if taken_branch /= e_in.br_pred then
1075                     v.f.redirect := '1';
1076                 end if;
1077             end if;
1078
1079             -- Update LR on the next cycle after a branch link
1080             -- If we're not writing back anything else, we can write back LR
1081             -- this cycle, otherwise we take an extra cycle.  We use the
1082             -- exc_write path since next_nia is written through that path
1083             -- in other places.
1084             if e_in.lr = '1' then
1085                 if result_en = '0' then
1086                     v.e.exc_write_enable := '1';
1087                     v.e.exc_write_data := next_nia;
1088                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
1089                 else
1090                     v.lr_update := '1';
1091                     v.next_lr := next_nia;
1092                     v.e.valid := '0';
1093                     report "Delayed LR update to " & to_hstring(next_nia);
1094                     v.busy := '1';
1095                 end if;
1096             end if;
1097
1098         elsif valid_in = '1' then
1099             -- instruction for other units, i.e. LDST
1100             if e_in.unit = LDST then
1101                 lv.valid := '1';
1102             elsif e_in.unit = NONE then
1103                 illegal := '1';
1104             elsif HAS_FPU and e_in.unit = FPU then
1105                 fv.valid := '1';
1106             end if;
1107             -- Handling an ITLB miss doesn't count as having executed an instruction
1108             if e_in.insn_type = OP_FETCH_FAILED then
1109                 do_trace := '0';
1110             end if;
1111         end if;
1112
1113         -- The following cases all occur when r.busy = 1 and therefore
1114         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1115         -- the cases above which depend on valid_in = 1.
1116
1117         if r.f.redirect = '1' then
1118             v.e.valid := '1';
1119         end if;
1120         if r.lr_update = '1' then
1121             v.e.exc_write_enable := '1';
1122             v.e.exc_write_data := r.next_lr;
1123             v.e.exc_write_reg := fast_spr_num(SPR_LR);
1124             v.e.valid := '1';
1125             -- Keep r.e.write_data unchanged next cycle in case it is needed
1126             -- for a forwarded result (e.g. for CTR).
1127             result := r.e.write_data;
1128         elsif r.cntz_in_progress = '1' then
1129             -- cnt[lt]z always takes two cycles
1130             result := countzero_result;
1131             result_en := '1';
1132             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1133             v.e.rc := r.slow_op_rc;
1134             v.e.xerc := r.slow_op_xerc;
1135             v.e.valid := '1';
1136         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1137             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1138                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1139                 if r.mul_in_progress = '1' then
1140                     overflow := '0';
1141                     case r.slow_op_insn is
1142                         when OP_MUL_H32 =>
1143                             result := multiply_to_x.result(63 downto 32) &
1144                                       multiply_to_x.result(63 downto 32);
1145                         when OP_MUL_H64 =>
1146                             result := multiply_to_x.result(127 downto 64);
1147                         when others =>
1148                             -- i.e. OP_MUL_L64
1149                             result := multiply_to_x.result(63 downto 0);
1150                     end case;
1151                 else
1152                     result := divider_to_x.write_reg_data;
1153                     overflow := divider_to_x.overflow;
1154                 end if;
1155                 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1156                     -- have to wait until next cycle for overflow indication
1157                     v.mul_finish := '1';
1158                     v.busy := '1';
1159                 else
1160                     result_en := '1';
1161                     v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1162                     v.e.rc := r.slow_op_rc;
1163                     v.e.xerc := r.slow_op_xerc;
1164                     v.e.write_xerc_enable := r.slow_op_oe;
1165                     -- We must test oe because the RC update code in writeback
1166                     -- will use the xerc value to set CR0:SO so we must not clobber
1167                     -- xerc if OE wasn't set.
1168                     if r.slow_op_oe = '1' then
1169                         v.e.xerc.ov := overflow;
1170                         v.e.xerc.ov32 := overflow;
1171                         v.e.xerc.so := r.slow_op_xerc.so or overflow;
1172                     end if;
1173                     v.e.valid := '1';
1174                 end if;
1175             else
1176                 v.busy := '1';
1177                 v.mul_in_progress := r.mul_in_progress;
1178                 v.div_in_progress := r.div_in_progress;
1179             end if;
1180         elsif r.mul_finish = '1' then
1181             result := r.e.write_data;
1182             result_en := '1';
1183             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1184             v.e.rc := r.slow_op_rc;
1185             v.e.xerc := r.slow_op_xerc;
1186             v.e.write_xerc_enable := r.slow_op_oe;
1187             v.e.xerc.ov := multiply_to_x.overflow;
1188             v.e.xerc.ov32 := multiply_to_x.overflow;
1189             v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1190             v.e.valid := '1';
1191         end if;
1192
1193         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1194         -- be set during the execution of a FP instruction.
1195         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1196         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1197         if HAS_FPU and fp_in.interrupt = '1' then
1198             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1199             ctrl_tmp.srr1(63 - 43) <= '1';
1200             exception := '1';
1201         end if;
1202
1203         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1204             exception := '1';
1205             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1206             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1207             -- set bit 44 to indicate we have an illegal
1208             ctrl_tmp.srr1(63 - 44) <= '1';
1209             report "illegal";
1210         end if;
1211         if exception = '1' then
1212             v.e.exc_write_enable := '1';
1213             if exception_nextpc = '1' then
1214                 v.e.exc_write_data := next_nia;
1215             end if;
1216         end if;
1217
1218         if do_trace = '1' then
1219             v.trace_next := '1';
1220         end if;
1221
1222         v.e.write_data := result;
1223         v.e.write_enable := result_en and not exception;
1224
1225         -- generate DSI or DSegI for load/store exceptions
1226         -- or ISI or ISegI for instruction fetch exceptions
1227         if l_in.exception = '1' then
1228             if l_in.alignment = '1' then
1229                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#600#, 64));
1230             elsif l_in.instr_fault = '0' then
1231                 if l_in.segment_fault = '0' then
1232                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1233                 else
1234                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1235                 end if;
1236             else
1237                 if l_in.segment_fault = '0' then
1238                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1239                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1240                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1241                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1242                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1243                 else
1244                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1245                 end if;
1246             end if;
1247             v.e.exc_write_enable := '1';
1248             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1249             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1250         end if;
1251
1252         if exception = '1' or l_in.exception = '1' then
1253             ctrl_tmp.irq_state <= WRITE_SRR1;
1254             v.f.redirect := '1';
1255             v.f.virt_mode := '0';
1256             v.f.priv_mode := '1';
1257             -- XXX need an interrupt LE bit here, e.g. from LPCR
1258             v.f.big_endian := '0';
1259             v.f.mode_32bit := '0';
1260         end if;
1261
1262         if v.f.redirect = '1' then
1263             v.busy := '1';
1264             v.e.valid := '0';
1265         end if;
1266
1267         -- Outputs to loadstore1 (async)
1268         lv.op := e_in.insn_type;
1269         lv.nia := e_in.nia;
1270         lv.addr1 := a_in;
1271         lv.addr2 := b_in;
1272         lv.data := c_in;
1273         lv.write_reg := e_in.write_reg;
1274         lv.length := e_in.data_len;
1275         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1276         lv.sign_extend := e_in.sign_extend;
1277         lv.update := e_in.update;
1278         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1279         lv.xerc := v.e.xerc;
1280         lv.reserve := e_in.reserve;
1281         lv.rc := e_in.rc;
1282         lv.insn := e_in.insn;
1283         -- decode l*cix and st*cix instructions here
1284         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1285             e_in.insn(5 downto 1) = "10101" then
1286             lv.ci := '1';
1287         end if;
1288         lv.virt_mode := ctrl.msr(MSR_DR);
1289         lv.priv_mode := not ctrl.msr(MSR_PR);
1290         lv.mode_32bit := not ctrl.msr(MSR_SF);
1291         lv.is_32bit := e_in.is_32bit;
1292         lv.repeat := e_in.repeat;
1293         lv.second := e_in.second;
1294
1295         -- Outputs to FPU
1296         fv.op := e_in.insn_type;
1297         fv.nia := e_in.nia;
1298         fv.insn := e_in.insn;
1299         fv.single := e_in.is_32bit;
1300         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1301         fv.fra := a_in;
1302         fv.frb := b_in;
1303         fv.frc := c_in;
1304         fv.frt := e_in.write_reg;
1305         fv.rc := e_in.rc;
1306         fv.out_cr := e_in.output_cr;
1307
1308         -- Update registers
1309         rin <= v;
1310
1311         -- update outputs
1312         f_out <= r.f;
1313         l_out <= lv;
1314         e_out <= r.e;
1315         fp_out <= fv;
1316         flush_out <= f_out.redirect;
1317
1318         exception_log <= exception;
1319         irq_valid_log <= irq_valid;
1320     end process;
1321
1322     e1_log: if LOG_LENGTH > 0 generate
1323         signal log_data : std_ulogic_vector(14 downto 0);
1324     begin
1325         ex1_log : process(clk)
1326         begin
1327             if rising_edge(clk) then
1328                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1329                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1330                             exception_log &
1331                             irq_valid_log &
1332                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1333                             "000" &
1334                             r.e.write_enable &
1335                             r.e.valid &
1336                             f_out.redirect &
1337                             r.busy &
1338                             flush_out;
1339             end if;
1340         end process;
1341         log_out <= log_data;
1342     end generate;
1343 end architecture behaviour;