execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40
  41         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  42
  43         icache_inval : out std_ulogic;
  44         terminate_out : out std_ulogic;
  45
  46         log_out : out std_ulogic_vector(14 downto 0);
  47         log_rd_addr : out std_ulogic_vector(31 downto 0);
  48         log_rd_data : in std_ulogic_vector(63 downto 0);
  49         log_wr_addr : in std_ulogic_vector(31 downto 0)
  50         );
  51 end entity execute1;
  52
  53 architecture behaviour of execute1 is
  54     type reg_type is record
  55         e : Execute1ToWritebackType;
  56         busy: std_ulogic;
  57         terminate: std_ulogic;
  58         fp_exception_next : std_ulogic;
  59         trace_next : std_ulogic;
  60         prev_op : insn_type_t;
  61         lr_update : std_ulogic;
  62         next_lr : std_ulogic_vector(63 downto 0);
  63         mul_in_progress : std_ulogic;
  64         mul_finish : std_ulogic;
  65         div_in_progress : std_ulogic;
  66         cntz_in_progress : std_ulogic;
  67         slow_op_insn : insn_type_t;
  68         slow_op_dest : gpr_index_t;
  69         slow_op_rc : std_ulogic;
  70         slow_op_oe : std_ulogic;
  71         slow_op_xerc : xer_common_t;
  72         last_nia : std_ulogic_vector(63 downto 0);
  73         redirect : std_ulogic;
  74         abs_br : std_ulogic;
  75         do_intr : std_ulogic;
  76         vector : integer range 0 to 16#fff#;
  77         br_offset : std_ulogic_vector(63 downto 0);
  78         redir_mode : std_ulogic_vector(3 downto 0);
  79         log_addr_spr : std_ulogic_vector(31 downto 0);
  80     end record;
  81     constant reg_type_init : reg_type :=
  82         (e => Execute1ToWritebackInit,
  83          busy => '0', lr_update => '0', terminate => '0',
  84          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL,
  85          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  86          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  87          next_lr => (others => '0'), last_nia => (others => '0'),
  88          redirect => '0', abs_br => '0', do_intr => '0', vector => 0,
  89          br_offset => (others => '0'), redir_mode => "0000",
  90          others => (others => '0'));
  91
  92     signal r, rin : reg_type;
  93
  94     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  95     signal cr_in : std_ulogic_vector(31 downto 0);
  96
  97     signal valid_in : std_ulogic;
  98     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  99     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
 100     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
 101     signal rot_sign_ext: std_ulogic;
 102     signal rotator_result: std_ulogic_vector(63 downto 0);
 103     signal rotator_carry: std_ulogic;
 104     signal logical_result: std_ulogic_vector(63 downto 0);
 105     signal countzero_result: std_ulogic_vector(63 downto 0);
 106
 107     -- multiply signals
 108     signal x_to_multiply: MultiplyInputType;
 109     signal multiply_to_x: MultiplyOutputType;
 110
 111     -- divider signals
 112     signal x_to_divider: Execute1ToDividerType;
 113     signal divider_to_x: DividerToExecute1Type;
 114
 115     -- random number generator signals
 116     signal random_raw  : std_ulogic_vector(63 downto 0);
 117     signal random_cond : std_ulogic_vector(63 downto 0);
 118     signal random_err  : std_ulogic;
 119
 120     -- signals for logging
 121     signal exception_log : std_ulogic;
 122     signal irq_valid_log : std_ulogic;
 123
 124     type privilege_level is (USER, SUPER);
 125     type op_privilege_array is array(insn_type_t) of privilege_level;
 126     constant op_privilege: op_privilege_array := (
 127         OP_ATTN => SUPER,
 128         OP_MFMSR => SUPER,
 129         OP_MTMSRD => SUPER,
 130         OP_RFID => SUPER,
 131         OP_TLBIE => SUPER,
 132         others => USER
 133         );
 134
 135     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 136         return boolean is
 137     begin
 138         if op_privilege(op) = SUPER then
 139             return true;
 140         elsif op = OP_MFSPR or op = OP_MTSPR then
 141             return insn(20) = '1';
 142         else
 143             return false;
 144         end if;
 145     end;
 146
 147     procedure set_carry(e: inout Execute1ToWritebackType;
 148                         carry32 : in std_ulogic;
 149                         carry : in std_ulogic) is
 150     begin
 151         e.xerc.ca32 := carry32;
 152         e.xerc.ca := carry;
 153         e.write_xerc_enable := '1';
 154     end;
 155
 156     procedure set_ov(e: inout Execute1ToWritebackType;
 157                      ov   : in std_ulogic;
 158                      ov32 : in std_ulogic) is
 159     begin
 160         e.xerc.ov32 := ov32;
 161         e.xerc.ov := ov;
 162         if ov = '1' then
 163             e.xerc.so := '1';
 164         end if;
 165         e.write_xerc_enable := '1';
 166     end;
 167
 168     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 169                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 170     begin
 171         return (ca xor msb_r) and not (msb_a xor msb_b);
 172     end;
 173
 174     function decode_input_carry(ic : carry_in_t;
 175                                 xerc : xer_common_t) return std_ulogic is
 176     begin
 177         case ic is
 178         when ZERO =>
 179             return '0';
 180         when CA =>
 181             return xerc.ca;
 182         when OV =>
 183             return xerc.ov;
 184         when ONE =>
 185             return '1';
 186         end case;
 187     end;
 188
 189     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 190         return std_ulogic_vector is
 191         variable msr_out: std_ulogic_vector(63 downto 0);
 192     begin
 193         -- ISA says this:
 194         --  Defined MSR bits are classified as either full func-
 195         --  tion or partial function. Full function MSR bits are
 196         --  saved in SRR1 or HSRR1 when an interrupt other
 197         --  than a System Call Vectored interrupt occurs and
 198         --  restored by rfscv, rfid, or hrfid, while partial func-
 199         --  tion MSR bits are not saved or restored.
 200         --  Full function MSR bits lie in the range 0:32, 37:41, and
 201         --  48:63, and partial function MSR bits lie in the range
 202         --  33:36 and 42:47. (Note this is IBM bit numbering).
 203         msr_out := (others => '0');
 204         msr_out(63 downto 31) := msr(63 downto 31);
 205         msr_out(26 downto 22) := msr(26 downto 22);
 206         msr_out(15 downto 0)  := msr(15 downto 0);
 207         return msr_out;
 208     end;
 209
 210     -- Tell vivado to keep the hierarchy for the random module so that the
 211     -- net names in the xdc file match.
 212     attribute keep_hierarchy : string;
 213     attribute keep_hierarchy of random_0 : label is "yes";
 214
 215 begin
 216
 217     rotator_0: entity work.rotator
 218         port map (
 219             rs => c_in,
 220             ra => a_in,
 221             shift => b_in(6 downto 0),
 222             insn => e_in.insn,
 223             is_32bit => e_in.is_32bit,
 224             right_shift => right_shift,
 225             arith => e_in.is_signed,
 226             clear_left => rot_clear_left,
 227             clear_right => rot_clear_right,
 228             sign_ext_rs => rot_sign_ext,
 229             result => rotator_result,
 230             carry_out => rotator_carry
 231             );
 232
 233     logical_0: entity work.logical
 234         port map (
 235             rs => c_in,
 236             rb => b_in,
 237             op => e_in.insn_type,
 238             invert_in => e_in.invert_a,
 239             invert_out => e_in.invert_out,
 240             result => logical_result,
 241             datalen => e_in.data_len
 242             );
 243
 244     countzero_0: entity work.zero_counter
 245         port map (
 246             clk => clk,
 247             rs => c_in,
 248             count_right => e_in.insn(10),
 249             is_32bit => e_in.is_32bit,
 250             result => countzero_result
 251             );
 252
 253     multiply_0: entity work.multiply
 254         port map (
 255             clk => clk,
 256             m_in => x_to_multiply,
 257             m_out => multiply_to_x
 258             );
 259
 260     divider_0: entity work.divider
 261         port map (
 262             clk => clk,
 263             rst => rst,
 264             d_in => x_to_divider,
 265             d_out => divider_to_x
 266             );
 267
 268     random_0: entity work.random
 269         port map (
 270             clk => clk,
 271             data => random_cond,
 272             raw => random_raw,
 273             err => random_err
 274             );
 275
 276     dbg_msr_out <= ctrl.msr;
 277     log_rd_addr <= r.log_addr_spr;
 278
 279     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 280     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 281     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 282
 283     busy_out <= l_in.busy or r.busy or fp_in.busy;
 284     valid_in <= e_in.valid and not busy_out;
 285
 286     terminate_out <= r.terminate;
 287
 288     execute1_0: process(clk)
 289     begin
 290         if rising_edge(clk) then
 291             if rst = '1' then
 292                 r <= reg_type_init;
 293                 ctrl.tb <= (others => '0');
 294                 ctrl.dec <= (others => '0');
 295                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 296                 ctrl.irq_state <= WRITE_SRR0;
 297             else
 298                 r <= rin;
 299                 ctrl <= ctrl_tmp;
 300                 assert not (r.lr_update = '1' and valid_in = '1')
 301                     report "LR update collision with valid in EX1"
 302                     severity failure;
 303                 if r.lr_update = '1' then
 304                     report "LR update to " & to_hstring(r.next_lr);
 305                 end if;
 306             end if;
 307         end if;
 308     end process;
 309
 310     execute1_1: process(all)
 311         variable v : reg_type;
 312         variable a_inv : std_ulogic_vector(63 downto 0);
 313         variable result : std_ulogic_vector(63 downto 0);
 314         variable newcrf : std_ulogic_vector(3 downto 0);
 315         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 316         variable result_en : std_ulogic;
 317         variable crnum : crnum_t;
 318         variable crbit : integer range 0 to 31;
 319         variable scrnum : crnum_t;
 320         variable lo, hi : integer;
 321         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 322         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 323         variable bo, bi : std_ulogic_vector(4 downto 0);
 324         variable bf, bfa : std_ulogic_vector(2 downto 0);
 325         variable cr_op : std_ulogic_vector(9 downto 0);
 326         variable cr_operands : std_ulogic_vector(1 downto 0);
 327         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 328         variable btnum, banum, bbnum : integer range 0 to 31;
 329         variable crresult : std_ulogic;
 330         variable l : std_ulogic;
 331         variable next_nia : std_ulogic_vector(63 downto 0);
 332         variable carry_32, carry_64 : std_ulogic;
 333         variable sign1, sign2 : std_ulogic;
 334         variable abs1, abs2 : signed(63 downto 0);
 335         variable overflow : std_ulogic;
 336         variable zerohi, zerolo : std_ulogic;
 337         variable msb_a, msb_b : std_ulogic;
 338         variable a_lt : std_ulogic;
 339         variable lv : Execute1ToLoadstore1Type;
 340         variable irq_valid : std_ulogic;
 341         variable exception : std_ulogic;
 342         variable exception_nextpc : std_ulogic;
 343         variable trapval : std_ulogic_vector(4 downto 0);
 344         variable illegal : std_ulogic;
 345         variable is_branch : std_ulogic;
 346         variable taken_branch : std_ulogic;
 347         variable abs_branch : std_ulogic;
 348         variable spr_val : std_ulogic_vector(63 downto 0);
 349         variable addend : std_ulogic_vector(127 downto 0);
 350         variable do_trace : std_ulogic;
 351         variable f : Execute1ToFetch1Type;
 352         variable fv : Execute1ToFPUType;
 353     begin
 354         result := (others => '0');
 355         sum_with_carry := (others => '0');
 356         result_en := '0';
 357         newcrf := (others => '0');
 358         is_branch := '0';
 359         taken_branch := '0';
 360         abs_branch := '0';
 361
 362         v := r;
 363         v.e := Execute1ToWritebackInit;
 364         v.redirect := '0';
 365         v.abs_br := '0';
 366         v.do_intr := '0';
 367         v.vector := 0;
 368         v.br_offset := (others => '0');
 369         v.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
 370                         not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
 371
 372         lv := Execute1ToLoadstore1Init;
 373         fv := Execute1ToFPUInit;
 374
 375         -- XER forwarding. To avoid having to track XER hazards, we use
 376         -- the previously latched value.  Since the XER common bits
 377         -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 378         -- handled here, we can just forward the result being sent to
 379         -- writeback.
 380         if r.e.write_xerc_enable = '1' then
 381             v.e.xerc := r.e.xerc;
 382         else
 383             v.e.xerc := e_in.xerc;
 384         end if;
 385
 386         -- CR forwarding
 387         cr_in <= e_in.cr;
 388         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 389             for i in 0 to 7 loop
 390                 if r.e.write_cr_mask(i) = '1' then
 391                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 392                 end if;
 393             end loop;
 394         end if;
 395
 396         v.lr_update := '0';
 397         v.mul_in_progress := '0';
 398         v.div_in_progress := '0';
 399         v.cntz_in_progress := '0';
 400         v.mul_finish := '0';
 401
 402         -- Main adder
 403         if e_in.invert_a = '0' then
 404             a_inv := a_in;
 405         else
 406             a_inv := not a_in;
 407         end if;
 408         sum_with_carry := ppc_adde(a_inv, b_in,
 409                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 410
 411         -- signals to multiply and divide units
 412         sign1 := '0';
 413         sign2 := '0';
 414         if e_in.is_signed = '1' then
 415             if e_in.is_32bit = '1' then
 416                 sign1 := a_in(31);
 417                 sign2 := b_in(31);
 418             else
 419                 sign1 := a_in(63);
 420                 sign2 := b_in(63);
 421             end if;
 422         end if;
 423         -- take absolute values
 424         if sign1 = '0' then
 425             abs1 := signed(a_in);
 426         else
 427             abs1 := - signed(a_in);
 428         end if;
 429         if sign2 = '0' then
 430             abs2 := signed(b_in);
 431         else
 432             abs2 := - signed(b_in);
 433         end if;
 434
 435         x_to_multiply <= MultiplyInputInit;
 436         x_to_multiply.is_32bit <= e_in.is_32bit;
 437
 438         x_to_divider <= Execute1ToDividerInit;
 439         x_to_divider.is_signed <= e_in.is_signed;
 440         x_to_divider.is_32bit <= e_in.is_32bit;
 441         if e_in.insn_type = OP_MOD then
 442             x_to_divider.is_modulus <= '1';
 443         end if;
 444
 445         addend := (others => '0');
 446         if e_in.insn(26) = '0' then
 447             -- integer multiply-add, major op 4 (if it is a multiply)
 448             addend(63 downto 0) := c_in;
 449             if e_in.is_signed = '1' then
 450                 addend(127 downto 64) := (others => c_in(63));
 451             end if;
 452         end if;
 453         if (sign1 xor sign2) = '1' then
 454             addend := not addend;
 455         end if;
 456
 457         x_to_multiply.not_result <= sign1 xor sign2;
 458         x_to_multiply.addend <= addend;
 459         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 460         if e_in.is_32bit = '0' then
 461             -- 64-bit forms
 462             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 463             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 464             if e_in.insn_type = OP_DIVE then
 465                 x_to_divider.is_extended <= '1';
 466             end if;
 467             x_to_divider.dividend <= std_ulogic_vector(abs1);
 468             x_to_divider.divisor <= std_ulogic_vector(abs2);
 469         else
 470             -- 32-bit forms
 471             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 472             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 473             x_to_divider.is_extended <= '0';
 474             if e_in.insn_type = OP_DIVE then   -- extended forms
 475                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 476             else
 477                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 478             end if;
 479             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 480         end if;
 481
 482         ctrl_tmp <= ctrl;
 483         -- FIXME: run at 512MHz not core freq
 484         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 485         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 486
 487         irq_valid := '0';
 488         if ctrl.msr(MSR_EE) = '1' then
 489             if ctrl.dec(63) = '1' then
 490                 v.vector := 16#900#;
 491                 report "IRQ valid: DEC";
 492                 irq_valid := '1';
 493             elsif ext_irq_in = '1' then
 494                 v.vector := 16#500#;
 495                 report "IRQ valid: External";
 496                 irq_valid := '1';
 497             end if;
 498         end if;
 499
 500         v.terminate := '0';
 501         icache_inval <= '0';
 502         v.busy := '0';
 503
 504         -- Next insn adder used in a couple of places
 505         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 506
 507         -- rotator control signals
 508         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 509         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 510         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 511         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 512
 513         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 514         ctrl_tmp.irq_state <= WRITE_SRR0;
 515         exception := '0';
 516         illegal := '0';
 517         exception_nextpc := '0';
 518         v.e.exc_write_enable := '0';
 519         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 520         if valid_in = '1' then
 521             v.e.exc_write_data := e_in.nia;
 522             v.last_nia := e_in.nia;
 523         else
 524             v.e.exc_write_data := r.last_nia;
 525         end if;
 526
 527         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 528
 529         do_trace := valid_in and ctrl.msr(MSR_SE);
 530         if valid_in = '1' then
 531             v.prev_op := e_in.insn_type;
 532         end if;
 533
 534         if ctrl.irq_state = WRITE_SRR1 then
 535             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 536             v.e.exc_write_data := ctrl.srr1;
 537             v.e.exc_write_enable := '1';
 538             ctrl_tmp.msr(MSR_SF) <= '1';
 539             ctrl_tmp.msr(MSR_EE) <= '0';
 540             ctrl_tmp.msr(MSR_PR) <= '0';
 541             ctrl_tmp.msr(MSR_SE) <= '0';
 542             ctrl_tmp.msr(MSR_BE) <= '0';
 543             ctrl_tmp.msr(MSR_FP) <= '0';
 544             ctrl_tmp.msr(MSR_FE0) <= '0';
 545             ctrl_tmp.msr(MSR_FE1) <= '0';
 546             ctrl_tmp.msr(MSR_IR) <= '0';
 547             ctrl_tmp.msr(MSR_DR) <= '0';
 548             ctrl_tmp.msr(MSR_RI) <= '0';
 549             ctrl_tmp.msr(MSR_LE) <= '1';
 550             v.e.valid := '1';
 551             v.trace_next := '0';
 552             v.fp_exception_next := '0';
 553             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 554
 555         elsif valid_in = '1' and e_in.second = '0' and
 556             ((HAS_FPU and r.fp_exception_next = '1') or r.trace_next = '1') then
 557             if HAS_FPU and r.fp_exception_next = '1' then
 558                 -- This is used for FP-type program interrupts that
 559                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 560                 v.vector := 16#700#;
 561                 ctrl_tmp.srr1(63 - 43) <= '1';
 562                 ctrl_tmp.srr1(63 - 47) <= '1';
 563             else
 564                 -- Generate a trace interrupt rather than executing the next instruction
 565                 -- or taking any asynchronous interrupt
 566                 v.vector := 16#d00#;
 567                 ctrl_tmp.srr1(63 - 33) <= '1';
 568                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 569                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 570                     ctrl_tmp.srr1(63 - 35) <= '1';
 571                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 572                     ctrl_tmp.srr1(63 - 36) <= '1';
 573                 end if;
 574             end if;
 575             exception := '1';
 576
 577         elsif irq_valid = '1' and valid_in = '1' and e_in.second = '0' then
 578             -- we need two cycles to write srr0 and 1
 579             -- will need more when we have to write HEIR
 580             -- Don't deliver the interrupt until we have a valid instruction
 581             -- coming in, so we have a valid NIA to put in SRR0.
 582             exception := '1';
 583
 584         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 585             instr_is_privileged(e_in.insn_type, e_in.insn) then
 586             -- generate a program interrupt
 587             exception := '1';
 588             v.vector := 16#700#;
 589             -- set bit 45 to indicate privileged instruction type interrupt
 590             ctrl_tmp.srr1(63 - 45) <= '1';
 591             report "privileged instruction";
 592
 593         elsif not HAS_FPU and valid_in = '1' and e_in.fac = FPU then
 594             -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 595             illegal := '1';
 596
 597         elsif HAS_FPU and valid_in = '1' and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 598             -- generate a floating-point unavailable interrupt
 599             exception := '1';
 600             v.vector := 16#800#;
 601             report "FP unavailable interrupt";
 602
 603         elsif valid_in = '1' and e_in.unit = ALU then
 604
 605             report "execute nia " & to_hstring(e_in.nia);
 606
 607             v.e.valid := '1';
 608             v.e.write_reg := e_in.write_reg;
 609             v.slow_op_insn := e_in.insn_type;
 610             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 611             v.slow_op_rc := e_in.rc;
 612             v.slow_op_oe := e_in.oe;
 613             v.slow_op_xerc := v.e.xerc;
 614
 615             case_0: case e_in.insn_type is
 616
 617             when OP_ILLEGAL =>
 618                 -- we need two cycles to write srr0 and 1
 619                 -- will need more when we have to write HEIR
 620                 illegal := '1';
 621             when OP_SC =>
 622                 -- check bit 1 of the instruction is 1 so we know this is sc;
 623                 -- 0 would mean scv, so generate an illegal instruction interrupt
 624                 -- we need two cycles to write srr0 and 1
 625                 if e_in.insn(1) = '1' then
 626                     exception := '1';
 627                     exception_nextpc := '1';
 628                     v.vector := 16#C00#;
 629                     report "sc";
 630                 else
 631                     illegal := '1';
 632                 end if;
 633             when OP_ATTN =>
 634                 -- check bits 1-10 of the instruction to make sure it's attn
 635                 -- if not then it is illegal
 636                 if e_in.insn(10 downto 1) = "0100000000" then
 637                     v.terminate := '1';
 638                     report "ATTN";
 639                 else
 640                     illegal := '1';
 641                 end if;
 642             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 643                 -- Do nothing
 644             when OP_ADD | OP_CMP | OP_TRAP =>
 645                 result := sum_with_carry(63 downto 0);
 646                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 647                 carry_64 := sum_with_carry(64);
 648                 if e_in.insn_type = OP_ADD then
 649                     if e_in.output_carry = '1' then
 650                         if e_in.input_carry /= OV then
 651                             set_carry(v.e, carry_32, carry_64);
 652                         else
 653                             v.e.xerc.ov := carry_64;
 654                             v.e.xerc.ov32 := carry_32;
 655                             v.e.write_xerc_enable := '1';
 656                         end if;
 657                     end if;
 658                     if e_in.oe = '1' then
 659                         set_ov(v.e,
 660                                calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 661                                calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 662                     end if;
 663                     result_en := '1';
 664                 else
 665                     -- trap, CMP and CMPL instructions
 666                     -- Note, we have done RB - RA, not RA - RB
 667                     if e_in.insn_type = OP_CMP then
 668                         l := insn_l(e_in.insn);
 669                     else
 670                         l := not e_in.is_32bit;
 671                     end if;
 672                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 673                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 674                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 675                         -- values are equal
 676                         trapval := "00100";
 677                     else
 678                         if l = '1' then
 679                             -- 64-bit comparison
 680                             msb_a := a_in(63);
 681                             msb_b := b_in(63);
 682                         else
 683                             -- 32-bit comparison
 684                             msb_a := a_in(31);
 685                             msb_b := b_in(31);
 686                         end if;
 687                         if msb_a /= msb_b then
 688                             -- Subtraction might overflow, but
 689                             -- comparison is clear from MSB difference.
 690                             -- for signed, 0 is greater; for unsigned, 1 is greater
 691                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 692                         else
 693                             -- Subtraction cannot overflow since MSBs are equal.
 694                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 695                             a_lt := (not l and carry_32) or (l and carry_64);
 696                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 697                         end if;
 698                     end if;
 699                     if e_in.insn_type = OP_CMP then
 700                         if e_in.is_signed = '1' then
 701                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 702                         else
 703                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 704                         end if;
 705                         bf := insn_bf(e_in.insn);
 706                         crnum := to_integer(unsigned(bf));
 707                         v.e.write_cr_enable := '1';
 708                         v.e.write_cr_mask := num_to_fxm(crnum);
 709                         for i in 0 to 7 loop
 710                             lo := i*4;
 711                             hi := lo + 3;
 712                             v.e.write_cr_data(hi downto lo) := newcrf;
 713                         end loop;
 714                     else
 715                         -- trap instructions (tw, twi, td, tdi)
 716                         v.vector := 16#700#;
 717                         -- set bit 46 to say trap occurred
 718                         ctrl_tmp.srr1(63 - 46) <= '1';
 719                         if or (trapval and insn_to(e_in.insn)) = '1' then
 720                             -- generate trap-type program interrupt
 721                             exception := '1';
 722                             report "trap";
 723                         end if;
 724                     end if;
 725                 end if;
 726             when OP_ADDG6S =>
 727                 result := (others => '0');
 728                 for i in 0 to 14 loop
 729                     lo := i * 4;
 730                     hi := (i + 1) * 4;
 731                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 732                         result(lo + 3 downto lo) := "0110";
 733                     end if;
 734                 end loop;
 735                 if sum_with_carry(64) = '0' then
 736                     result(63 downto 60) := "0110";
 737                 end if;
 738                 result_en := '1';
 739             when OP_CMPRB =>
 740                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 741                 bf := insn_bf(e_in.insn);
 742                 crnum := to_integer(unsigned(bf));
 743                 v.e.write_cr_enable := '1';
 744                 v.e.write_cr_mask := num_to_fxm(crnum);
 745                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 746                                      newcrf & newcrf & newcrf & newcrf;
 747             when OP_CMPEQB =>
 748                 newcrf := ppc_cmpeqb(a_in, b_in);
 749                 bf := insn_bf(e_in.insn);
 750                 crnum := to_integer(unsigned(bf));
 751                 v.e.write_cr_enable := '1';
 752                 v.e.write_cr_mask := num_to_fxm(crnum);
 753                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 754                                      newcrf & newcrf & newcrf & newcrf;
 755             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 756                     OP_BPERM | OP_BCD =>
 757                 result := logical_result;
 758                 result_en := '1';
 759             when OP_B =>
 760                 is_branch := '1';
 761                 taken_branch := '1';
 762                 abs_branch := insn_aa(e_in.insn);
 763                 if ctrl.msr(MSR_BE) = '1' then
 764                     do_trace := '1';
 765                 end if;
 766             when OP_BC =>
 767                 -- read_data1 is CTR
 768                 bo := insn_bo(e_in.insn);
 769                 bi := insn_bi(e_in.insn);
 770                 if bo(4-2) = '0' then
 771                     result := std_ulogic_vector(unsigned(a_in) - 1);
 772                     result_en := '1';
 773                     v.e.write_reg := fast_spr_num(SPR_CTR);
 774                 end if;
 775                 is_branch := '1';
 776                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 777                 abs_branch := insn_aa(e_in.insn);
 778                 if ctrl.msr(MSR_BE) = '1' then
 779                     do_trace := '1';
 780                 end if;
 781             when OP_BCREG =>
 782                 -- read_data1 is CTR
 783                 -- read_data2 is target register (CTR, LR or TAR)
 784                 bo := insn_bo(e_in.insn);
 785                 bi := insn_bi(e_in.insn);
 786                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 787                     result := std_ulogic_vector(unsigned(a_in) - 1);
 788                     result_en := '1';
 789                     v.e.write_reg := fast_spr_num(SPR_CTR);
 790                 end if;
 791                 is_branch := '1';
 792                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 793                 abs_branch := '1';
 794                 if ctrl.msr(MSR_BE) = '1' then
 795                     do_trace := '1';
 796                 end if;
 797
 798             when OP_RFID =>
 799                 v.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
 800                                 not a_in(MSR_LE) & not a_in(MSR_SF);
 801                 -- Can't use msr_copy here because the partial function MSR
 802                 -- bits should be left unchanged, not zeroed.
 803                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 804                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 805                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 806                 if a_in(MSR_PR) = '1' then
 807                     ctrl_tmp.msr(MSR_EE) <= '1';
 808                     ctrl_tmp.msr(MSR_IR) <= '1';
 809                     ctrl_tmp.msr(MSR_DR) <= '1';
 810                 end if;
 811                 -- mark this as a branch so CFAR gets updated
 812                 is_branch := '1';
 813                 taken_branch := '1';
 814                 abs_branch := '1';
 815                 if HAS_FPU then
 816                     v.fp_exception_next := fp_in.exception and
 817                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 818                 end if;
 819                 do_trace := '0';
 820
 821             when OP_CNTZ =>
 822                 v.e.valid := '0';
 823                 v.cntz_in_progress := '1';
 824                 v.busy := '1';
 825             when OP_ISEL =>
 826                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 827                 if cr_in(31-crbit) = '1' then
 828                     result := a_in;
 829                 else
 830                     result := b_in;
 831                 end if;
 832                 result_en := '1';
 833             when OP_CROP =>
 834                 cr_op := insn_cr(e_in.insn);
 835                 report "CR OP " & to_hstring(cr_op);
 836                 if cr_op(0) = '0' then -- MCRF
 837                     bf := insn_bf(e_in.insn);
 838                     bfa := insn_bfa(e_in.insn);
 839                     v.e.write_cr_enable := '1';
 840                     crnum := to_integer(unsigned(bf));
 841                     scrnum := to_integer(unsigned(bfa));
 842                     v.e.write_cr_mask := num_to_fxm(crnum);
 843                     for i in 0 to 7 loop
 844                         lo := (7-i)*4;
 845                         hi := lo + 3;
 846                         if i = scrnum then
 847                             newcrf := cr_in(hi downto lo);
 848                         end if;
 849                     end loop;
 850                     for i in 0 to 7 loop
 851                         lo := i*4;
 852                         hi := lo + 3;
 853                         v.e.write_cr_data(hi downto lo) := newcrf;
 854                     end loop;
 855                 else
 856                     v.e.write_cr_enable := '1';
 857                     bt := insn_bt(e_in.insn);
 858                     ba := insn_ba(e_in.insn);
 859                     bb := insn_bb(e_in.insn);
 860                     btnum := 31 - to_integer(unsigned(bt));
 861                     banum := 31 - to_integer(unsigned(ba));
 862                     bbnum := 31 - to_integer(unsigned(bb));
 863                     -- Bits 5-8 of cr_op give the truth table of the requested
 864                     -- logical operation
 865                     cr_operands := cr_in(banum) & cr_in(bbnum);
 866                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 867                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 868                     for i in 0 to 31 loop
 869                         if i = btnum then
 870                             v.e.write_cr_data(i) := crresult;
 871                         else
 872                             v.e.write_cr_data(i) := cr_in(i);
 873                         end if;
 874                     end loop;
 875                 end if;
 876             when OP_MCRXRX =>
 877                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 878                 bf := insn_bf(e_in.insn);
 879                 crnum := to_integer(unsigned(bf));
 880                 v.e.write_cr_enable := '1';
 881                 v.e.write_cr_mask := num_to_fxm(crnum);
 882                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 883                                      newcrf & newcrf & newcrf & newcrf;
 884             when OP_DARN =>
 885                 if random_err = '0' then
 886                     case e_in.insn(17 downto 16) is
 887                         when "00" =>
 888                             result := x"00000000" & random_cond(31 downto 0);
 889                         when "10" =>
 890                             result := random_raw;
 891                         when others =>
 892                             result := random_cond;
 893                     end case;
 894                 else
 895                     result := (others => '1');
 896                 end if;
 897                 result_en := '1';
 898             when OP_MFMSR =>
 899                 result := ctrl.msr;
 900                 result_en := '1';
 901             when OP_MFSPR =>
 902                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 903                     "=" & to_hstring(a_in);
 904                 result_en := '1';
 905                 if is_fast_spr(e_in.read_reg1) then
 906                     result := a_in;
 907                     if decode_spr_num(e_in.insn) = SPR_XER then
 908                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 909                         result(63 downto 32) := (others => '0');
 910                         result(63-32) := v.e.xerc.so;
 911                         result(63-33) := v.e.xerc.ov;
 912                         result(63-34) := v.e.xerc.ca;
 913                         result(63-35 downto 63-43) := "000000000";
 914                         result(63-44) := v.e.xerc.ov32;
 915                         result(63-45) := v.e.xerc.ca32;
 916                     end if;
 917                 else
 918                     spr_val := c_in;
 919                     case decode_spr_num(e_in.insn) is
 920                     when SPR_TB =>
 921                         spr_val := ctrl.tb;
 922                     when SPR_TBU =>
 923                         spr_val(63 downto 32) := (others => '0');
 924                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 925                     when SPR_DEC =>
 926                         spr_val := ctrl.dec;
 927                     when SPR_CFAR =>
 928                         spr_val := ctrl.cfar;
 929                     when SPR_PVR =>
 930                         spr_val(63 downto 32) := (others => '0');
 931                         spr_val(31 downto 0) := PVR_MICROWATT;
 932                     when 724 =>     -- LOG_ADDR SPR
 933                         spr_val := log_wr_addr & r.log_addr_spr;
 934                     when 725 =>     -- LOG_DATA SPR
 935                         spr_val := log_rd_data;
 936                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 937                     when others =>
 938                         -- mfspr from unimplemented SPRs should be a nop in
 939                         -- supervisor mode and a program interrupt for user mode
 940                         if ctrl.msr(MSR_PR) = '1' then
 941                             illegal := '1';
 942                         end if;
 943                     end case;
 944                     result := spr_val;
 945                 end if;
 946             when OP_MFCR =>
 947                 if e_in.insn(20) = '0' then
 948                     -- mfcr
 949                     result := x"00000000" & cr_in;
 950                 else
 951                     -- mfocrf
 952                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 953                     result := (others => '0');
 954                     for i in 0 to 7 loop
 955                         lo := (7-i)*4;
 956                         hi := lo + 3;
 957                         if crnum = i then
 958                             result(hi downto lo) := cr_in(hi downto lo);
 959                         end if;
 960                     end loop;
 961                 end if;
 962                 result_en := '1';
 963             when OP_MTCRF =>
 964                 v.e.write_cr_enable := '1';
 965                 if e_in.insn(20) = '0' then
 966                     -- mtcrf
 967                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 968                 else
 969                     -- mtocrf: We require one hot priority encoding here
 970                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 971                     v.e.write_cr_mask := num_to_fxm(crnum);
 972                 end if;
 973                 v.e.write_cr_data := c_in(31 downto 0);
 974             when OP_MTMSRD =>
 975                 if e_in.insn(16) = '1' then
 976                     -- just update EE and RI
 977                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 978                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 979                 else
 980                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 981                     -- and 63 (LE) (IBM bit numbering)
 982                     if e_in.is_32bit = '0' then
 983                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 984                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
 985                     end if;
 986                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
 987                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 988                     if c_in(MSR_PR) = '1' then
 989                         ctrl_tmp.msr(MSR_EE) <= '1';
 990                         ctrl_tmp.msr(MSR_IR) <= '1';
 991                         ctrl_tmp.msr(MSR_DR) <= '1';
 992                     end if;
 993                     if HAS_FPU then
 994                         v.fp_exception_next := fp_in.exception and
 995                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
 996                     end if;
 997                 end if;
 998             when OP_MTSPR =>
 999                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1000                     "=" & to_hstring(c_in);
1001                 if is_fast_spr(e_in.write_reg) then
1002                     result := c_in;
1003                     result_en := '1';
1004                     if decode_spr_num(e_in.insn) = SPR_XER then
1005                         v.e.xerc.so := c_in(63-32);
1006                         v.e.xerc.ov := c_in(63-33);
1007                         v.e.xerc.ca := c_in(63-34);
1008                         v.e.xerc.ov32 := c_in(63-44);
1009                         v.e.xerc.ca32 := c_in(63-45);
1010                         v.e.write_xerc_enable := '1';
1011                     end if;
1012                 else
1013                     -- slow spr
1014                     case decode_spr_num(e_in.insn) is
1015                     when SPR_DEC =>
1016                         ctrl_tmp.dec <= c_in;
1017                     when 724 =>     -- LOG_ADDR SPR
1018                         v.log_addr_spr := c_in(31 downto 0);
1019                     when others =>
1020                         -- mtspr to unimplemented SPRs should be a nop in
1021                         -- supervisor mode and a program interrupt for user mode
1022                         if ctrl.msr(MSR_PR) = '1' then
1023                             illegal := '1';
1024                         end if;
1025                     end case;
1026                 end if;
1027             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1028                 result := rotator_result;
1029                 if e_in.output_carry = '1' then
1030                     set_carry(v.e, rotator_carry, rotator_carry);
1031                 end if;
1032                 result_en := '1';
1033             when OP_SETB =>
1034                 bfa := insn_bfa(e_in.insn);
1035                 crbit := to_integer(unsigned(bfa)) * 4;
1036                 result := (others => '0');
1037                 if cr_in(31 - crbit) = '1' then
1038                     result := (others => '1');
1039                 elsif cr_in(30 - crbit) = '1' then
1040                     result(0) := '1';
1041                 end if;
1042
1043             when OP_ISYNC =>
1044                 v.redirect := '1';
1045                 v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1046
1047             when OP_ICBI =>
1048                 icache_inval <= '1';
1049
1050             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1051                 v.e.valid := '0';
1052                 v.mul_in_progress := '1';
1053                 v.busy := '1';
1054                 x_to_multiply.valid <= '1';
1055
1056             when OP_DIV | OP_DIVE | OP_MOD =>
1057                 v.e.valid := '0';
1058                 v.div_in_progress := '1';
1059                 v.busy := '1';
1060                 x_to_divider.valid <= '1';
1061
1062             when others =>
1063                 v.terminate := '1';
1064                 report "illegal";
1065             end case;
1066
1067             v.e.rc := e_in.rc and valid_in;
1068
1069             -- Mispredicted branches cause a redirect
1070             if is_branch = '1' then
1071                 if taken_branch = '1' then
1072                     ctrl_tmp.cfar <= e_in.nia;
1073                 end if;
1074                 if e_in.br_pred = '0' then
1075                     v.br_offset := b_in;
1076                     v.abs_br := abs_branch;
1077                 else
1078                     v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1079                 end if;
1080                 if taken_branch /= e_in.br_pred then
1081                     v.redirect := '1';
1082                 end if;
1083             end if;
1084
1085             -- Update LR on the next cycle after a branch link
1086             -- If we're not writing back anything else, we can write back LR
1087             -- this cycle, otherwise we take an extra cycle.  We use the
1088             -- exc_write path since next_nia is written through that path
1089             -- in other places.
1090             if e_in.lr = '1' then
1091                 if result_en = '0' then
1092                     v.e.exc_write_enable := '1';
1093                     v.e.exc_write_data := next_nia;
1094                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
1095                 else
1096                     v.lr_update := '1';
1097                     v.next_lr := next_nia;
1098                     v.e.valid := '0';
1099                     report "Delayed LR update to " & to_hstring(next_nia);
1100                     v.busy := '1';
1101                 end if;
1102             end if;
1103
1104         elsif valid_in = '1' then
1105             -- instruction for other units, i.e. LDST
1106             if e_in.unit = LDST then
1107                 lv.valid := '1';
1108             elsif e_in.unit = NONE then
1109                 illegal := '1';
1110             elsif HAS_FPU and e_in.unit = FPU then
1111                 fv.valid := '1';
1112             end if;
1113             -- Handling an ITLB miss doesn't count as having executed an instruction
1114             if e_in.insn_type = OP_FETCH_FAILED then
1115                 do_trace := '0';
1116             end if;
1117         end if;
1118
1119         -- The following cases all occur when r.busy = 1 and therefore
1120         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1121         -- the cases above which depend on valid_in = 1.
1122
1123         if r.redirect = '1' then
1124             v.e.valid := '1';
1125         end if;
1126         if r.lr_update = '1' then
1127             v.e.exc_write_enable := '1';
1128             v.e.exc_write_data := r.next_lr;
1129             v.e.exc_write_reg := fast_spr_num(SPR_LR);
1130             v.e.valid := '1';
1131             -- Keep r.e.write_data unchanged next cycle in case it is needed
1132             -- for a forwarded result (e.g. for CTR).
1133             result := r.e.write_data;
1134         elsif r.cntz_in_progress = '1' then
1135             -- cnt[lt]z always takes two cycles
1136             result := countzero_result;
1137             result_en := '1';
1138             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1139             v.e.rc := r.slow_op_rc;
1140             v.e.xerc := r.slow_op_xerc;
1141             v.e.valid := '1';
1142         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1143             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1144                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1145                 if r.mul_in_progress = '1' then
1146                     overflow := '0';
1147                     case r.slow_op_insn is
1148                         when OP_MUL_H32 =>
1149                             result := multiply_to_x.result(63 downto 32) &
1150                                       multiply_to_x.result(63 downto 32);
1151                         when OP_MUL_H64 =>
1152                             result := multiply_to_x.result(127 downto 64);
1153                         when others =>
1154                             -- i.e. OP_MUL_L64
1155                             result := multiply_to_x.result(63 downto 0);
1156                     end case;
1157                 else
1158                     result := divider_to_x.write_reg_data;
1159                     overflow := divider_to_x.overflow;
1160                 end if;
1161                 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1162                     -- have to wait until next cycle for overflow indication
1163                     v.mul_finish := '1';
1164                     v.busy := '1';
1165                 else
1166                     result_en := '1';
1167                     v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1168                     v.e.rc := r.slow_op_rc;
1169                     v.e.xerc := r.slow_op_xerc;
1170                     v.e.write_xerc_enable := r.slow_op_oe;
1171                     -- We must test oe because the RC update code in writeback
1172                     -- will use the xerc value to set CR0:SO so we must not clobber
1173                     -- xerc if OE wasn't set.
1174                     if r.slow_op_oe = '1' then
1175                         v.e.xerc.ov := overflow;
1176                         v.e.xerc.ov32 := overflow;
1177                         v.e.xerc.so := r.slow_op_xerc.so or overflow;
1178                     end if;
1179                     v.e.valid := '1';
1180                 end if;
1181             else
1182                 v.busy := '1';
1183                 v.mul_in_progress := r.mul_in_progress;
1184                 v.div_in_progress := r.div_in_progress;
1185             end if;
1186         elsif r.mul_finish = '1' then
1187             result := r.e.write_data;
1188             result_en := '1';
1189             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1190             v.e.rc := r.slow_op_rc;
1191             v.e.xerc := r.slow_op_xerc;
1192             v.e.write_xerc_enable := r.slow_op_oe;
1193             v.e.xerc.ov := multiply_to_x.overflow;
1194             v.e.xerc.ov32 := multiply_to_x.overflow;
1195             v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1196             v.e.valid := '1';
1197         end if;
1198
1199         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1200         -- be set during the execution of a FP instruction.
1201         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1202         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1203         if HAS_FPU and fp_in.interrupt = '1' then
1204             v.vector := 16#700#;
1205             ctrl_tmp.srr1(63 - 43) <= '1';
1206             exception := '1';
1207         end if;
1208
1209         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1210             exception := '1';
1211             v.vector := 16#700#;
1212             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1213             -- set bit 44 to indicate we have an illegal
1214             ctrl_tmp.srr1(63 - 44) <= '1';
1215             report "illegal";
1216         end if;
1217         if exception = '1' then
1218             v.e.exc_write_enable := '1';
1219             if exception_nextpc = '1' then
1220                 v.e.exc_write_data := next_nia;
1221             end if;
1222         end if;
1223
1224         if do_trace = '1' then
1225             v.trace_next := '1';
1226         end if;
1227
1228         v.e.write_data := result;
1229         v.e.write_enable := result_en and not exception;
1230
1231         -- generate DSI or DSegI for load/store exceptions
1232         -- or ISI or ISegI for instruction fetch exceptions
1233         if l_in.exception = '1' then
1234             if l_in.alignment = '1' then
1235                 v.vector := 16#600#;
1236             elsif l_in.instr_fault = '0' then
1237                 if l_in.segment_fault = '0' then
1238                     v.vector := 16#300#;
1239                 else
1240                     v.vector := 16#380#;
1241                 end if;
1242             else
1243                 if l_in.segment_fault = '0' then
1244                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1245                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1246                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1247                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1248                     v.vector := 16#400#;
1249                 else
1250                     v.vector := 16#480#;
1251                 end if;
1252             end if;
1253             v.e.exc_write_enable := '1';
1254             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1255             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1256         end if;
1257
1258         if exception = '1' or l_in.exception = '1' then
1259             ctrl_tmp.irq_state <= WRITE_SRR1;
1260             v.redirect := '1';
1261             v.do_intr := '1';
1262         end if;
1263
1264         if v.redirect = '1' then
1265             v.busy := '1';
1266             v.e.valid := '0';
1267         end if;
1268
1269         -- Outputs to fetch1
1270         f.redirect := r.redirect;
1271         if r.do_intr = '1' then
1272             f.redirect_nia := std_ulogic_vector(to_unsigned(r.vector, 64));
1273             f.virt_mode := '0';
1274             f.priv_mode := '1';
1275             -- XXX need an interrupt LE bit here, e.g. from LPCR
1276             f.big_endian := '0';
1277             f.mode_32bit := '0';
1278         else
1279             if r.abs_br = '1' then
1280                 f.redirect_nia := r.br_offset;
1281             else
1282                 f.redirect_nia := std_ulogic_vector(unsigned(r.last_nia) + unsigned(r.br_offset));
1283             end if;
1284             -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
1285             f.virt_mode := r.redir_mode(3);
1286             f.priv_mode := r.redir_mode(2);
1287             f.big_endian := r.redir_mode(1);
1288             f.mode_32bit := r.redir_mode(0);
1289         end if;
1290
1291         -- Outputs to loadstore1 (async)
1292         lv.op := e_in.insn_type;
1293         lv.nia := e_in.nia;
1294         lv.addr1 := a_in;
1295         lv.addr2 := b_in;
1296         lv.data := c_in;
1297         lv.write_reg := e_in.write_reg;
1298         lv.length := e_in.data_len;
1299         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1300         lv.sign_extend := e_in.sign_extend;
1301         lv.update := e_in.update;
1302         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1303         lv.xerc := v.e.xerc;
1304         lv.reserve := e_in.reserve;
1305         lv.rc := e_in.rc;
1306         lv.insn := e_in.insn;
1307         -- decode l*cix and st*cix instructions here
1308         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1309             e_in.insn(5 downto 1) = "10101" then
1310             lv.ci := '1';
1311         end if;
1312         lv.virt_mode := ctrl.msr(MSR_DR);
1313         lv.priv_mode := not ctrl.msr(MSR_PR);
1314         lv.mode_32bit := not ctrl.msr(MSR_SF);
1315         lv.is_32bit := e_in.is_32bit;
1316         lv.repeat := e_in.repeat;
1317         lv.second := e_in.second;
1318
1319         -- Outputs to FPU
1320         fv.op := e_in.insn_type;
1321         fv.nia := e_in.nia;
1322         fv.insn := e_in.insn;
1323         fv.single := e_in.is_32bit;
1324         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1325         fv.fra := a_in;
1326         fv.frb := b_in;
1327         fv.frc := c_in;
1328         fv.frt := e_in.write_reg;
1329         fv.rc := e_in.rc;
1330         fv.out_cr := e_in.output_cr;
1331
1332         -- Update registers
1333         rin <= v;
1334
1335         -- update outputs
1336         f_out <= f;
1337         l_out <= lv;
1338         e_out <= r.e;
1339         fp_out <= fv;
1340         flush_out <= f_out.redirect;
1341
1342         exception_log <= exception;
1343         irq_valid_log <= irq_valid;
1344     end process;
1345
1346     e1_log: if LOG_LENGTH > 0 generate
1347         signal log_data : std_ulogic_vector(14 downto 0);
1348     begin
1349         ex1_log : process(clk)
1350         begin
1351             if rising_edge(clk) then
1352                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1353                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1354                             exception_log &
1355                             irq_valid_log &
1356                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1357                             "000" &
1358                             r.e.write_enable &
1359                             r.e.valid &
1360                             f_out.redirect &
1361                             r.busy &
1362                             flush_out;
1363             end if;
1364         end process;
1365         log_out <= log_data;
1366     end generate;
1367 end architecture behaviour;