execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40
  41         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  42
  43         icache_inval : out std_ulogic;
  44         terminate_out : out std_ulogic;
  45
  46         log_out : out std_ulogic_vector(14 downto 0);
  47         log_rd_addr : out std_ulogic_vector(31 downto 0);
  48         log_rd_data : in std_ulogic_vector(63 downto 0);
  49         log_wr_addr : in std_ulogic_vector(31 downto 0)
  50         );
  51 end entity execute1;
  52
  53 architecture behaviour of execute1 is
  54     type reg_type is record
  55         e : Execute1ToWritebackType;
  56         f : Execute1ToFetch1Type;
  57         busy: std_ulogic;
  58         terminate: std_ulogic;
  59         fp_exception_next : std_ulogic;
  60         trace_next : std_ulogic;
  61         prev_op : insn_type_t;
  62         lr_update : std_ulogic;
  63         next_lr : std_ulogic_vector(63 downto 0);
  64         mul_in_progress : std_ulogic;
  65         mul_finish : std_ulogic;
  66         div_in_progress : std_ulogic;
  67         cntz_in_progress : std_ulogic;
  68         slow_op_insn : insn_type_t;
  69         slow_op_dest : gpr_index_t;
  70         slow_op_rc : std_ulogic;
  71         slow_op_oe : std_ulogic;
  72         slow_op_xerc : xer_common_t;
  73         last_nia : std_ulogic_vector(63 downto 0);
  74         log_addr_spr : std_ulogic_vector(31 downto 0);
  75     end record;
  76     constant reg_type_init : reg_type :=
  77         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  78          busy => '0', lr_update => '0', terminate => '0',
  79          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL,
  80          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  81          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  82          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  83
  84     signal r, rin : reg_type;
  85
  86     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  87     signal cr_in : std_ulogic_vector(31 downto 0);
  88
  89     signal valid_in : std_ulogic;
  90     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  91     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  92     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  93     signal rot_sign_ext: std_ulogic;
  94     signal rotator_result: std_ulogic_vector(63 downto 0);
  95     signal rotator_carry: std_ulogic;
  96     signal logical_result: std_ulogic_vector(63 downto 0);
  97     signal countzero_result: std_ulogic_vector(63 downto 0);
  98
  99     -- multiply signals
 100     signal x_to_multiply: MultiplyInputType;
 101     signal multiply_to_x: MultiplyOutputType;
 102
 103     -- divider signals
 104     signal x_to_divider: Execute1ToDividerType;
 105     signal divider_to_x: DividerToExecute1Type;
 106
 107     -- random number generator signals
 108     signal random_raw  : std_ulogic_vector(63 downto 0);
 109     signal random_cond : std_ulogic_vector(63 downto 0);
 110     signal random_err  : std_ulogic;
 111
 112     -- signals for logging
 113     signal exception_log : std_ulogic;
 114     signal irq_valid_log : std_ulogic;
 115
 116     type privilege_level is (USER, SUPER);
 117     type op_privilege_array is array(insn_type_t) of privilege_level;
 118     constant op_privilege: op_privilege_array := (
 119         OP_ATTN => SUPER,
 120         OP_MFMSR => SUPER,
 121         OP_MTMSRD => SUPER,
 122         OP_RFID => SUPER,
 123         OP_TLBIE => SUPER,
 124         others => USER
 125         );
 126
 127     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 128         return boolean is
 129     begin
 130         if op_privilege(op) = SUPER then
 131             return true;
 132         elsif op = OP_MFSPR or op = OP_MTSPR then
 133             return insn(20) = '1';
 134         else
 135             return false;
 136         end if;
 137     end;
 138
 139     procedure set_carry(e: inout Execute1ToWritebackType;
 140                         carry32 : in std_ulogic;
 141                         carry : in std_ulogic) is
 142     begin
 143         e.xerc.ca32 := carry32;
 144         e.xerc.ca := carry;
 145         e.write_xerc_enable := '1';
 146     end;
 147
 148     procedure set_ov(e: inout Execute1ToWritebackType;
 149                      ov   : in std_ulogic;
 150                      ov32 : in std_ulogic) is
 151     begin
 152         e.xerc.ov32 := ov32;
 153         e.xerc.ov := ov;
 154         if ov = '1' then
 155             e.xerc.so := '1';
 156         end if;
 157         e.write_xerc_enable := '1';
 158     end;
 159
 160     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 161                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 162     begin
 163         return (ca xor msb_r) and not (msb_a xor msb_b);
 164     end;
 165
 166     function decode_input_carry(ic : carry_in_t;
 167                                 xerc : xer_common_t) return std_ulogic is
 168     begin
 169         case ic is
 170         when ZERO =>
 171             return '0';
 172         when CA =>
 173             return xerc.ca;
 174         when OV =>
 175             return xerc.ov;
 176         when ONE =>
 177             return '1';
 178         end case;
 179     end;
 180
 181     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 182         return std_ulogic_vector is
 183         variable msr_out: std_ulogic_vector(63 downto 0);
 184     begin
 185         -- ISA says this:
 186         --  Defined MSR bits are classified as either full func-
 187         --  tion or partial function. Full function MSR bits are
 188         --  saved in SRR1 or HSRR1 when an interrupt other
 189         --  than a System Call Vectored interrupt occurs and
 190         --  restored by rfscv, rfid, or hrfid, while partial func-
 191         --  tion MSR bits are not saved or restored.
 192         --  Full function MSR bits lie in the range 0:32, 37:41, and
 193         --  48:63, and partial function MSR bits lie in the range
 194         --  33:36 and 42:47. (Note this is IBM bit numbering).
 195         msr_out := (others => '0');
 196         msr_out(63 downto 31) := msr(63 downto 31);
 197         msr_out(26 downto 22) := msr(26 downto 22);
 198         msr_out(15 downto 0)  := msr(15 downto 0);
 199         return msr_out;
 200     end;
 201
 202     -- Tell vivado to keep the hierarchy for the random module so that the
 203     -- net names in the xdc file match.
 204     attribute keep_hierarchy : string;
 205     attribute keep_hierarchy of random_0 : label is "yes";
 206
 207 begin
 208
 209     rotator_0: entity work.rotator
 210         port map (
 211             rs => c_in,
 212             ra => a_in,
 213             shift => b_in(6 downto 0),
 214             insn => e_in.insn,
 215             is_32bit => e_in.is_32bit,
 216             right_shift => right_shift,
 217             arith => e_in.is_signed,
 218             clear_left => rot_clear_left,
 219             clear_right => rot_clear_right,
 220             sign_ext_rs => rot_sign_ext,
 221             result => rotator_result,
 222             carry_out => rotator_carry
 223             );
 224
 225     logical_0: entity work.logical
 226         port map (
 227             rs => c_in,
 228             rb => b_in,
 229             op => e_in.insn_type,
 230             invert_in => e_in.invert_a,
 231             invert_out => e_in.invert_out,
 232             result => logical_result,
 233             datalen => e_in.data_len
 234             );
 235
 236     countzero_0: entity work.zero_counter
 237         port map (
 238             clk => clk,
 239             rs => c_in,
 240             count_right => e_in.insn(10),
 241             is_32bit => e_in.is_32bit,
 242             result => countzero_result
 243             );
 244
 245     multiply_0: entity work.multiply
 246         port map (
 247             clk => clk,
 248             m_in => x_to_multiply,
 249             m_out => multiply_to_x
 250             );
 251
 252     divider_0: entity work.divider
 253         port map (
 254             clk => clk,
 255             rst => rst,
 256             d_in => x_to_divider,
 257             d_out => divider_to_x
 258             );
 259
 260     random_0: entity work.random
 261         port map (
 262             clk => clk,
 263             data => random_cond,
 264             raw => random_raw,
 265             err => random_err
 266             );
 267
 268     dbg_msr_out <= ctrl.msr;
 269     log_rd_addr <= r.log_addr_spr;
 270
 271     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 272     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 273     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 274
 275     busy_out <= l_in.busy or r.busy or fp_in.busy;
 276     valid_in <= e_in.valid and not busy_out;
 277
 278     terminate_out <= r.terminate;
 279
 280     execute1_0: process(clk)
 281     begin
 282         if rising_edge(clk) then
 283             if rst = '1' then
 284                 r <= reg_type_init;
 285                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 286                 ctrl.irq_state <= WRITE_SRR0;
 287             else
 288                 r <= rin;
 289                 ctrl <= ctrl_tmp;
 290                 assert not (r.lr_update = '1' and valid_in = '1')
 291                     report "LR update collision with valid in EX1"
 292                     severity failure;
 293                 if r.lr_update = '1' then
 294                     report "LR update to " & to_hstring(r.next_lr);
 295                 end if;
 296             end if;
 297         end if;
 298     end process;
 299
 300     execute1_1: process(all)
 301         variable v : reg_type;
 302         variable a_inv : std_ulogic_vector(63 downto 0);
 303         variable result : std_ulogic_vector(63 downto 0);
 304         variable newcrf : std_ulogic_vector(3 downto 0);
 305         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 306         variable result_en : std_ulogic;
 307         variable crnum : crnum_t;
 308         variable crbit : integer range 0 to 31;
 309         variable scrnum : crnum_t;
 310         variable lo, hi : integer;
 311         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 312         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 313         variable bo, bi : std_ulogic_vector(4 downto 0);
 314         variable bf, bfa : std_ulogic_vector(2 downto 0);
 315         variable cr_op : std_ulogic_vector(9 downto 0);
 316         variable cr_operands : std_ulogic_vector(1 downto 0);
 317         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 318         variable btnum, banum, bbnum : integer range 0 to 31;
 319         variable crresult : std_ulogic;
 320         variable l : std_ulogic;
 321         variable next_nia : std_ulogic_vector(63 downto 0);
 322         variable carry_32, carry_64 : std_ulogic;
 323         variable sign1, sign2 : std_ulogic;
 324         variable abs1, abs2 : signed(63 downto 0);
 325         variable overflow : std_ulogic;
 326         variable zerohi, zerolo : std_ulogic;
 327         variable msb_a, msb_b : std_ulogic;
 328         variable a_lt : std_ulogic;
 329         variable lv : Execute1ToLoadstore1Type;
 330         variable irq_valid : std_ulogic;
 331         variable exception : std_ulogic;
 332         variable exception_nextpc : std_ulogic;
 333         variable trapval : std_ulogic_vector(4 downto 0);
 334         variable illegal : std_ulogic;
 335         variable is_branch : std_ulogic;
 336         variable taken_branch : std_ulogic;
 337         variable abs_branch : std_ulogic;
 338         variable spr_val : std_ulogic_vector(63 downto 0);
 339         variable addend : std_ulogic_vector(127 downto 0);
 340         variable do_trace : std_ulogic;
 341         variable fv : Execute1ToFPUType;
 342     begin
 343         result := (others => '0');
 344         sum_with_carry := (others => '0');
 345         result_en := '0';
 346         newcrf := (others => '0');
 347         is_branch := '0';
 348         taken_branch := '0';
 349         abs_branch := '0';
 350
 351         v := r;
 352         v.e := Execute1ToWritebackInit;
 353         lv := Execute1ToLoadstore1Init;
 354         v.f.redirect := '0';
 355         fv := Execute1ToFPUInit;
 356
 357         -- XER forwarding. To avoid having to track XER hazards, we
 358         -- use the previously latched value.
 359         --
 360         -- If the XER was modified by a multiply or a divide, those are
 361         -- single issue, we'll get the up to date value from decode2 from
 362         -- the register file.
 363         --
 364         -- If it was modified by an instruction older than the previous
 365         -- one in EX1, it will have also hit writeback and will be up
 366         -- to date in decode2.
 367         --
 368         -- That leaves us with the case where it was updated by the previous
 369         -- instruction in EX1. In that case, we can forward it back here.
 370         --
 371         -- This will break if we allow pipelining of multiply and divide,
 372         -- but ideally, those should go via EX1 anyway and run as a state
 373         -- machine from here.
 374         --
 375         -- One additional hazard to beware of is an XER:SO modifying instruction
 376         -- in EX1 followed immediately by a store conditional. Due to our
 377         -- writeback latency, the store will go down the LSU with the previous
 378         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 379         --
 380         -- We will need to handle that if we ever make stcx. not single issue
 381         --
 382         -- We always pass a valid XER value downto writeback even when
 383         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 384         -- to work for RC instructions.
 385         --
 386         if r.e.write_xerc_enable = '1' then
 387             v.e.xerc := r.e.xerc;
 388         else
 389             v.e.xerc := e_in.xerc;
 390         end if;
 391
 392         -- CR forwarding
 393         cr_in <= e_in.cr;
 394         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 395             for i in 0 to 7 loop
 396                 if r.e.write_cr_mask(i) = '1' then
 397                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 398                 end if;
 399             end loop;
 400         end if;
 401
 402         v.lr_update := '0';
 403         v.mul_in_progress := '0';
 404         v.div_in_progress := '0';
 405         v.cntz_in_progress := '0';
 406         v.mul_finish := '0';
 407
 408         -- Main adder
 409         if e_in.invert_a = '0' then
 410             a_inv := a_in;
 411         else
 412             a_inv := not a_in;
 413         end if;
 414         sum_with_carry := ppc_adde(a_inv, b_in,
 415                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 416
 417         -- signals to multiply and divide units
 418         sign1 := '0';
 419         sign2 := '0';
 420         if e_in.is_signed = '1' then
 421             if e_in.is_32bit = '1' then
 422                 sign1 := a_in(31);
 423                 sign2 := b_in(31);
 424             else
 425                 sign1 := a_in(63);
 426                 sign2 := b_in(63);
 427             end if;
 428         end if;
 429         -- take absolute values
 430         if sign1 = '0' then
 431             abs1 := signed(a_in);
 432         else
 433             abs1 := - signed(a_in);
 434         end if;
 435         if sign2 = '0' then
 436             abs2 := signed(b_in);
 437         else
 438             abs2 := - signed(b_in);
 439         end if;
 440
 441         x_to_multiply <= MultiplyInputInit;
 442         x_to_multiply.is_32bit <= e_in.is_32bit;
 443
 444         x_to_divider <= Execute1ToDividerInit;
 445         x_to_divider.is_signed <= e_in.is_signed;
 446         x_to_divider.is_32bit <= e_in.is_32bit;
 447         if e_in.insn_type = OP_MOD then
 448             x_to_divider.is_modulus <= '1';
 449         end if;
 450
 451         addend := (others => '0');
 452         if e_in.insn(26) = '0' then
 453             -- integer multiply-add, major op 4 (if it is a multiply)
 454             addend(63 downto 0) := c_in;
 455             if e_in.is_signed = '1' then
 456                 addend(127 downto 64) := (others => c_in(63));
 457             end if;
 458         end if;
 459         if (sign1 xor sign2) = '1' then
 460             addend := not addend;
 461         end if;
 462
 463         x_to_multiply.not_result <= sign1 xor sign2;
 464         x_to_multiply.addend <= addend;
 465         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 466         if e_in.is_32bit = '0' then
 467             -- 64-bit forms
 468             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 469             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 470             if e_in.insn_type = OP_DIVE then
 471                 x_to_divider.is_extended <= '1';
 472             end if;
 473             x_to_divider.dividend <= std_ulogic_vector(abs1);
 474             x_to_divider.divisor <= std_ulogic_vector(abs2);
 475         else
 476             -- 32-bit forms
 477             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 478             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 479             x_to_divider.is_extended <= '0';
 480             if e_in.insn_type = OP_DIVE then   -- extended forms
 481                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 482             else
 483                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 484             end if;
 485             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 486         end if;
 487
 488         ctrl_tmp <= ctrl;
 489         -- FIXME: run at 512MHz not core freq
 490         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 491         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 492
 493         irq_valid := '0';
 494         if ctrl.msr(MSR_EE) = '1' then
 495             if ctrl.dec(63) = '1' then
 496                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 497                 report "IRQ valid: DEC";
 498                 irq_valid := '1';
 499             elsif ext_irq_in = '1' then
 500                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 501                 report "IRQ valid: External";
 502                 irq_valid := '1';
 503             end if;
 504         end if;
 505
 506         v.terminate := '0';
 507         icache_inval <= '0';
 508         v.busy := '0';
 509         -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
 510         v.f.virt_mode := ctrl.msr(MSR_IR);
 511         v.f.priv_mode := not ctrl.msr(MSR_PR);
 512         v.f.big_endian := not ctrl.msr(MSR_LE);
 513         v.f.mode_32bit := not ctrl.msr(MSR_SF);
 514
 515         -- Next insn adder used in a couple of places
 516         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 517
 518         -- rotator control signals
 519         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 520         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 521         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 522         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 523
 524         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 525         ctrl_tmp.irq_state <= WRITE_SRR0;
 526         exception := '0';
 527         illegal := '0';
 528         exception_nextpc := '0';
 529         v.e.exc_write_enable := '0';
 530         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 531         if valid_in = '1' then
 532             v.e.exc_write_data := e_in.nia;
 533             v.last_nia := e_in.nia;
 534         else
 535             v.e.exc_write_data := r.last_nia;
 536         end if;
 537
 538         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 539
 540         do_trace := valid_in and ctrl.msr(MSR_SE);
 541         if valid_in = '1' then
 542             v.prev_op := e_in.insn_type;
 543         end if;
 544
 545         if ctrl.irq_state = WRITE_SRR1 then
 546             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 547             v.e.exc_write_data := ctrl.srr1;
 548             v.e.exc_write_enable := '1';
 549             ctrl_tmp.msr(MSR_SF) <= '1';
 550             ctrl_tmp.msr(MSR_EE) <= '0';
 551             ctrl_tmp.msr(MSR_PR) <= '0';
 552             ctrl_tmp.msr(MSR_SE) <= '0';
 553             ctrl_tmp.msr(MSR_BE) <= '0';
 554             ctrl_tmp.msr(MSR_FP) <= '0';
 555             ctrl_tmp.msr(MSR_FE0) <= '0';
 556             ctrl_tmp.msr(MSR_FE1) <= '0';
 557             ctrl_tmp.msr(MSR_IR) <= '0';
 558             ctrl_tmp.msr(MSR_DR) <= '0';
 559             ctrl_tmp.msr(MSR_RI) <= '0';
 560             ctrl_tmp.msr(MSR_LE) <= '1';
 561             v.e.valid := '1';
 562             v.trace_next := '0';
 563             v.fp_exception_next := '0';
 564             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 565
 566         elsif valid_in = '1' and ((HAS_FPU and r.fp_exception_next = '1') or r.trace_next = '1') then
 567             if HAS_FPU and r.fp_exception_next = '1' then
 568                 -- This is used for FP-type program interrupts that
 569                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 570                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 571                 ctrl_tmp.srr1(63 - 43) <= '1';
 572                 ctrl_tmp.srr1(63 - 47) <= '1';
 573             else
 574                 -- Generate a trace interrupt rather than executing the next instruction
 575                 -- or taking any asynchronous interrupt
 576                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#d00#, 64));
 577                 ctrl_tmp.srr1(63 - 33) <= '1';
 578                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 579                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 580                     ctrl_tmp.srr1(63 - 35) <= '1';
 581                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 582                     ctrl_tmp.srr1(63 - 36) <= '1';
 583                 end if;
 584             end if;
 585             exception := '1';
 586
 587         elsif irq_valid = '1' and valid_in = '1' then
 588             -- we need two cycles to write srr0 and 1
 589             -- will need more when we have to write HEIR
 590             -- Don't deliver the interrupt until we have a valid instruction
 591             -- coming in, so we have a valid NIA to put in SRR0.
 592             exception := '1';
 593
 594         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 595             instr_is_privileged(e_in.insn_type, e_in.insn) then
 596             -- generate a program interrupt
 597             exception := '1';
 598             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 599             -- set bit 45 to indicate privileged instruction type interrupt
 600             ctrl_tmp.srr1(63 - 45) <= '1';
 601             report "privileged instruction";
 602
 603         elsif not HAS_FPU and valid_in = '1' and
 604             (e_in.insn_type = OP_FPLOAD or e_in.insn_type = OP_FPSTORE) then
 605             -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 606             illegal := '1';
 607
 608         elsif HAS_FPU and valid_in = '1' and ctrl.msr(MSR_FP) = '0' and
 609             (e_in.unit = FPU or e_in.insn_type = OP_FPLOAD or e_in.insn_type = OP_FPSTORE) then
 610             -- generate a floating-point unavailable interrupt
 611             exception := '1';
 612             v.f.redirect_nia := std_logic_vector(to_unsigned(16#800#, 64));
 613             report "FP unavailable interrupt";
 614
 615         elsif valid_in = '1' and e_in.unit = ALU then
 616
 617             report "execute nia " & to_hstring(e_in.nia);
 618
 619             v.e.valid := '1';
 620             v.e.write_reg := e_in.write_reg;
 621             v.slow_op_insn := e_in.insn_type;
 622             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 623             v.slow_op_rc := e_in.rc;
 624             v.slow_op_oe := e_in.oe;
 625             v.slow_op_xerc := v.e.xerc;
 626
 627             case_0: case e_in.insn_type is
 628
 629             when OP_ILLEGAL =>
 630                 -- we need two cycles to write srr0 and 1
 631                 -- will need more when we have to write HEIR
 632                 illegal := '1';
 633             when OP_SC =>
 634                 -- check bit 1 of the instruction is 1 so we know this is sc;
 635                 -- 0 would mean scv, so generate an illegal instruction interrupt
 636                 -- we need two cycles to write srr0 and 1
 637                 if e_in.insn(1) = '1' then
 638                     exception := '1';
 639                     exception_nextpc := '1';
 640                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 641                     report "sc";
 642                 else
 643                     illegal := '1';
 644                 end if;
 645             when OP_ATTN =>
 646                 -- check bits 1-10 of the instruction to make sure it's attn
 647                 -- if not then it is illegal
 648                 if e_in.insn(10 downto 1) = "0100000000" then
 649                     v.terminate := '1';
 650                     report "ATTN";
 651                 else
 652                     illegal := '1';
 653                 end if;
 654             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 655                 -- Do nothing
 656             when OP_ADD | OP_CMP | OP_TRAP =>
 657                 result := sum_with_carry(63 downto 0);
 658                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 659                 carry_64 := sum_with_carry(64);
 660                 if e_in.insn_type = OP_ADD then
 661                     if e_in.output_carry = '1' then
 662                         if e_in.input_carry /= OV then
 663                             set_carry(v.e, carry_32, carry_64);
 664                         else
 665                             v.e.xerc.ov := carry_64;
 666                             v.e.xerc.ov32 := carry_32;
 667                             v.e.write_xerc_enable := '1';
 668                         end if;
 669                     end if;
 670                     if e_in.oe = '1' then
 671                         set_ov(v.e,
 672                                calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 673                                calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 674                     end if;
 675                     result_en := '1';
 676                 else
 677                     -- trap, CMP and CMPL instructions
 678                     -- Note, we have done RB - RA, not RA - RB
 679                     if e_in.insn_type = OP_CMP then
 680                         l := insn_l(e_in.insn);
 681                     else
 682                         l := not e_in.is_32bit;
 683                     end if;
 684                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 685                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 686                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 687                         -- values are equal
 688                         trapval := "00100";
 689                     else
 690                         if l = '1' then
 691                             -- 64-bit comparison
 692                             msb_a := a_in(63);
 693                             msb_b := b_in(63);
 694                         else
 695                             -- 32-bit comparison
 696                             msb_a := a_in(31);
 697                             msb_b := b_in(31);
 698                         end if;
 699                         if msb_a /= msb_b then
 700                             -- Subtraction might overflow, but
 701                             -- comparison is clear from MSB difference.
 702                             -- for signed, 0 is greater; for unsigned, 1 is greater
 703                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 704                         else
 705                             -- Subtraction cannot overflow since MSBs are equal.
 706                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 707                             a_lt := (not l and carry_32) or (l and carry_64);
 708                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 709                         end if;
 710                     end if;
 711                     if e_in.insn_type = OP_CMP then
 712                         if e_in.is_signed = '1' then
 713                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 714                         else
 715                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 716                         end if;
 717                         bf := insn_bf(e_in.insn);
 718                         crnum := to_integer(unsigned(bf));
 719                         v.e.write_cr_enable := '1';
 720                         v.e.write_cr_mask := num_to_fxm(crnum);
 721                         for i in 0 to 7 loop
 722                             lo := i*4;
 723                             hi := lo + 3;
 724                             v.e.write_cr_data(hi downto lo) := newcrf;
 725                         end loop;
 726                     else
 727                         -- trap instructions (tw, twi, td, tdi)
 728                         v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 729                         -- set bit 46 to say trap occurred
 730                         ctrl_tmp.srr1(63 - 46) <= '1';
 731                         if or (trapval and insn_to(e_in.insn)) = '1' then
 732                             -- generate trap-type program interrupt
 733                             exception := '1';
 734                             report "trap";
 735                         end if;
 736                     end if;
 737                 end if;
 738             when OP_ADDG6S =>
 739                 result := (others => '0');
 740                 for i in 0 to 14 loop
 741                     lo := i * 4;
 742                     hi := (i + 1) * 4;
 743                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 744                         result(lo + 3 downto lo) := "0110";
 745                     end if;
 746                 end loop;
 747                 if sum_with_carry(64) = '0' then
 748                     result(63 downto 60) := "0110";
 749                 end if;
 750                 result_en := '1';
 751             when OP_CMPRB =>
 752                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 753                 bf := insn_bf(e_in.insn);
 754                 crnum := to_integer(unsigned(bf));
 755                 v.e.write_cr_enable := '1';
 756                 v.e.write_cr_mask := num_to_fxm(crnum);
 757                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 758                                      newcrf & newcrf & newcrf & newcrf;
 759             when OP_CMPEQB =>
 760                 newcrf := ppc_cmpeqb(a_in, b_in);
 761                 bf := insn_bf(e_in.insn);
 762                 crnum := to_integer(unsigned(bf));
 763                 v.e.write_cr_enable := '1';
 764                 v.e.write_cr_mask := num_to_fxm(crnum);
 765                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 766                                      newcrf & newcrf & newcrf & newcrf;
 767             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 768                     OP_BPERM | OP_BCD =>
 769                 result := logical_result;
 770                 result_en := '1';
 771             when OP_B =>
 772                 is_branch := '1';
 773                 taken_branch := '1';
 774                 abs_branch := insn_aa(e_in.insn);
 775                 if ctrl.msr(MSR_BE) = '1' then
 776                     do_trace := '1';
 777                 end if;
 778             when OP_BC =>
 779                 -- read_data1 is CTR
 780                 bo := insn_bo(e_in.insn);
 781                 bi := insn_bi(e_in.insn);
 782                 if bo(4-2) = '0' then
 783                     result := std_ulogic_vector(unsigned(a_in) - 1);
 784                     result_en := '1';
 785                     v.e.write_reg := fast_spr_num(SPR_CTR);
 786                 end if;
 787                 is_branch := '1';
 788                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 789                 abs_branch := insn_aa(e_in.insn);
 790                 if ctrl.msr(MSR_BE) = '1' then
 791                     do_trace := '1';
 792                 end if;
 793             when OP_BCREG =>
 794                 -- read_data1 is CTR
 795                 -- read_data2 is target register (CTR, LR or TAR)
 796                 bo := insn_bo(e_in.insn);
 797                 bi := insn_bi(e_in.insn);
 798                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 799                     result := std_ulogic_vector(unsigned(a_in) - 1);
 800                     result_en := '1';
 801                     v.e.write_reg := fast_spr_num(SPR_CTR);
 802                 end if;
 803                 is_branch := '1';
 804                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 805                 abs_branch := '1';
 806                 if ctrl.msr(MSR_BE) = '1' then
 807                     do_trace := '1';
 808                 end if;
 809
 810             when OP_RFID =>
 811                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 812                 v.f.priv_mode := not a_in(MSR_PR);
 813                 v.f.big_endian := not a_in(MSR_LE);
 814                 v.f.mode_32bit := not a_in(MSR_SF);
 815                 -- Can't use msr_copy here because the partial function MSR
 816                 -- bits should be left unchanged, not zeroed.
 817                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 818                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 819                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 820                 if a_in(MSR_PR) = '1' then
 821                     ctrl_tmp.msr(MSR_EE) <= '1';
 822                     ctrl_tmp.msr(MSR_IR) <= '1';
 823                     ctrl_tmp.msr(MSR_DR) <= '1';
 824                 end if;
 825                 -- mark this as a branch so CFAR gets updated
 826                 is_branch := '1';
 827                 taken_branch := '1';
 828                 abs_branch := '1';
 829                 if HAS_FPU then
 830                     v.fp_exception_next := fp_in.exception and
 831                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 832                 end if;
 833                 do_trace := '0';
 834
 835             when OP_CNTZ =>
 836                 v.e.valid := '0';
 837                 v.cntz_in_progress := '1';
 838                 v.busy := '1';
 839             when OP_ISEL =>
 840                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 841                 if cr_in(31-crbit) = '1' then
 842                     result := a_in;
 843                 else
 844                     result := b_in;
 845                 end if;
 846                 result_en := '1';
 847             when OP_CROP =>
 848                 cr_op := insn_cr(e_in.insn);
 849                 report "CR OP " & to_hstring(cr_op);
 850                 if cr_op(0) = '0' then -- MCRF
 851                     bf := insn_bf(e_in.insn);
 852                     bfa := insn_bfa(e_in.insn);
 853                     v.e.write_cr_enable := '1';
 854                     crnum := to_integer(unsigned(bf));
 855                     scrnum := to_integer(unsigned(bfa));
 856                     v.e.write_cr_mask := num_to_fxm(crnum);
 857                     for i in 0 to 7 loop
 858                         lo := (7-i)*4;
 859                         hi := lo + 3;
 860                         if i = scrnum then
 861                             newcrf := cr_in(hi downto lo);
 862                         end if;
 863                     end loop;
 864                     for i in 0 to 7 loop
 865                         lo := i*4;
 866                         hi := lo + 3;
 867                         v.e.write_cr_data(hi downto lo) := newcrf;
 868                     end loop;
 869                 else
 870                     v.e.write_cr_enable := '1';
 871                     bt := insn_bt(e_in.insn);
 872                     ba := insn_ba(e_in.insn);
 873                     bb := insn_bb(e_in.insn);
 874                     btnum := 31 - to_integer(unsigned(bt));
 875                     banum := 31 - to_integer(unsigned(ba));
 876                     bbnum := 31 - to_integer(unsigned(bb));
 877                     -- Bits 5-8 of cr_op give the truth table of the requested
 878                     -- logical operation
 879                     cr_operands := cr_in(banum) & cr_in(bbnum);
 880                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 881                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 882                     for i in 0 to 31 loop
 883                         if i = btnum then
 884                             v.e.write_cr_data(i) := crresult;
 885                         else
 886                             v.e.write_cr_data(i) := cr_in(i);
 887                         end if;
 888                     end loop;
 889                 end if;
 890             when OP_MCRXRX =>
 891                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 892                 bf := insn_bf(e_in.insn);
 893                 crnum := to_integer(unsigned(bf));
 894                 v.e.write_cr_enable := '1';
 895                 v.e.write_cr_mask := num_to_fxm(crnum);
 896                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 897                                      newcrf & newcrf & newcrf & newcrf;
 898             when OP_DARN =>
 899                 if random_err = '0' then
 900                     case e_in.insn(17 downto 16) is
 901                         when "00" =>
 902                             result := x"00000000" & random_cond(31 downto 0);
 903                         when "10" =>
 904                             result := random_raw;
 905                         when others =>
 906                             result := random_cond;
 907                     end case;
 908                 else
 909                     result := (others => '1');
 910                 end if;
 911                 result_en := '1';
 912             when OP_MFMSR =>
 913                 result := ctrl.msr;
 914                 result_en := '1';
 915             when OP_MFSPR =>
 916                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 917                     "=" & to_hstring(a_in);
 918                 result_en := '1';
 919                 if is_fast_spr(e_in.read_reg1) then
 920                     result := a_in;
 921                     if decode_spr_num(e_in.insn) = SPR_XER then
 922                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 923                         result(63 downto 32) := (others => '0');
 924                         result(63-32) := v.e.xerc.so;
 925                         result(63-33) := v.e.xerc.ov;
 926                         result(63-34) := v.e.xerc.ca;
 927                         result(63-35 downto 63-43) := "000000000";
 928                         result(63-44) := v.e.xerc.ov32;
 929                         result(63-45) := v.e.xerc.ca32;
 930                     end if;
 931                 else
 932                     spr_val := c_in;
 933                     case decode_spr_num(e_in.insn) is
 934                     when SPR_TB =>
 935                         spr_val := ctrl.tb;
 936                     when SPR_TBU =>
 937                         spr_val(63 downto 32) := (others => '0');
 938                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 939                     when SPR_DEC =>
 940                         spr_val := ctrl.dec;
 941                     when SPR_CFAR =>
 942                         spr_val := ctrl.cfar;
 943                     when SPR_PVR =>
 944                         spr_val(63 downto 32) := (others => '0');
 945                         spr_val(31 downto 0) := PVR_MICROWATT;
 946                     when 724 =>     -- LOG_ADDR SPR
 947                         spr_val := log_wr_addr & r.log_addr_spr;
 948                     when 725 =>     -- LOG_DATA SPR
 949                         spr_val := log_rd_data;
 950                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 951                     when others =>
 952                         -- mfspr from unimplemented SPRs should be a nop in
 953                         -- supervisor mode and a program interrupt for user mode
 954                         if ctrl.msr(MSR_PR) = '1' then
 955                             illegal := '1';
 956                         end if;
 957                     end case;
 958                     result := spr_val;
 959                 end if;
 960             when OP_MFCR =>
 961                 if e_in.insn(20) = '0' then
 962                     -- mfcr
 963                     result := x"00000000" & cr_in;
 964                 else
 965                     -- mfocrf
 966                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 967                     result := (others => '0');
 968                     for i in 0 to 7 loop
 969                         lo := (7-i)*4;
 970                         hi := lo + 3;
 971                         if crnum = i then
 972                             result(hi downto lo) := cr_in(hi downto lo);
 973                         end if;
 974                     end loop;
 975                 end if;
 976                 result_en := '1';
 977             when OP_MTCRF =>
 978                 v.e.write_cr_enable := '1';
 979                 if e_in.insn(20) = '0' then
 980                     -- mtcrf
 981                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 982                 else
 983                     -- mtocrf: We require one hot priority encoding here
 984                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 985                     v.e.write_cr_mask := num_to_fxm(crnum);
 986                 end if;
 987                 v.e.write_cr_data := c_in(31 downto 0);
 988             when OP_MTMSRD =>
 989                 if e_in.insn(16) = '1' then
 990                     -- just update EE and RI
 991                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 992                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 993                 else
 994                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 995                     -- and 63 (LE) (IBM bit numbering)
 996                     if e_in.is_32bit = '0' then
 997                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 998                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
 999                     end if;
1000                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1001                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
1002                     if c_in(MSR_PR) = '1' then
1003                         ctrl_tmp.msr(MSR_EE) <= '1';
1004                         ctrl_tmp.msr(MSR_IR) <= '1';
1005                         ctrl_tmp.msr(MSR_DR) <= '1';
1006                     end if;
1007                     if HAS_FPU then
1008                         v.fp_exception_next := fp_in.exception and
1009                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
1010                     end if;
1011                 end if;
1012             when OP_MTSPR =>
1013                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1014                     "=" & to_hstring(c_in);
1015                 if is_fast_spr(e_in.write_reg) then
1016                     result := c_in;
1017                     result_en := '1';
1018                     if decode_spr_num(e_in.insn) = SPR_XER then
1019                         v.e.xerc.so := c_in(63-32);
1020                         v.e.xerc.ov := c_in(63-33);
1021                         v.e.xerc.ca := c_in(63-34);
1022                         v.e.xerc.ov32 := c_in(63-44);
1023                         v.e.xerc.ca32 := c_in(63-45);
1024                         v.e.write_xerc_enable := '1';
1025                     end if;
1026                 else
1027                     -- slow spr
1028                     case decode_spr_num(e_in.insn) is
1029                     when SPR_DEC =>
1030                         ctrl_tmp.dec <= c_in;
1031                     when 724 =>     -- LOG_ADDR SPR
1032                         v.log_addr_spr := c_in(31 downto 0);
1033                     when others =>
1034                         -- mtspr to unimplemented SPRs should be a nop in
1035                         -- supervisor mode and a program interrupt for user mode
1036                         if ctrl.msr(MSR_PR) = '1' then
1037                             illegal := '1';
1038                         end if;
1039                     end case;
1040                 end if;
1041             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1042                 result := rotator_result;
1043                 if e_in.output_carry = '1' then
1044                     set_carry(v.e, rotator_carry, rotator_carry);
1045                 end if;
1046                 result_en := '1';
1047             when OP_SETB =>
1048                 bfa := insn_bfa(e_in.insn);
1049                 crbit := to_integer(unsigned(bfa)) * 4;
1050                 result := (others => '0');
1051                 if cr_in(31 - crbit) = '1' then
1052                     result := (others => '1');
1053                 elsif cr_in(30 - crbit) = '1' then
1054                     result(0) := '1';
1055                 end if;
1056
1057             when OP_ISYNC =>
1058                 v.f.redirect := '1';
1059                 v.f.redirect_nia := next_nia;
1060
1061             when OP_ICBI =>
1062                 icache_inval <= '1';
1063
1064             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1065                 v.e.valid := '0';
1066                 v.mul_in_progress := '1';
1067                 v.busy := '1';
1068                 x_to_multiply.valid <= '1';
1069
1070             when OP_DIV | OP_DIVE | OP_MOD =>
1071                 v.e.valid := '0';
1072                 v.div_in_progress := '1';
1073                 v.busy := '1';
1074                 x_to_divider.valid <= '1';
1075
1076             when others =>
1077                 v.terminate := '1';
1078                 report "illegal";
1079             end case;
1080
1081             v.e.rc := e_in.rc and valid_in;
1082
1083             -- Mispredicted branches cause a redirect
1084             if is_branch = '1' then
1085                 if taken_branch = '1' then
1086                     ctrl_tmp.cfar <= e_in.nia;
1087                 end if;
1088                 if e_in.br_pred = '0' then
1089                     if abs_branch = '1' then
1090                         v.f.redirect_nia := b_in;
1091                     else
1092                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
1093                     end if;
1094                 else
1095                     v.f.redirect_nia := next_nia;
1096                 end if;
1097                 if taken_branch /= e_in.br_pred then
1098                     v.f.redirect := '1';
1099                 end if;
1100             end if;
1101
1102             -- Update LR on the next cycle after a branch link
1103             -- If we're not writing back anything else, we can write back LR
1104             -- this cycle, otherwise we take an extra cycle.  We use the
1105             -- exc_write path since next_nia is written through that path
1106             -- in other places.
1107             if e_in.lr = '1' then
1108                 if result_en = '0' then
1109                     v.e.exc_write_enable := '1';
1110                     v.e.exc_write_data := next_nia;
1111                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
1112                 else
1113                     v.lr_update := '1';
1114                     v.next_lr := next_nia;
1115                     v.e.valid := '0';
1116                     report "Delayed LR update to " & to_hstring(next_nia);
1117                     v.busy := '1';
1118                 end if;
1119             end if;
1120
1121         elsif valid_in = '1' then
1122             -- instruction for other units, i.e. LDST
1123             if e_in.unit = LDST then
1124                 lv.valid := '1';
1125             elsif e_in.unit = NONE then
1126                 illegal := '1';
1127             elsif HAS_FPU and e_in.unit = FPU then
1128                 fv.valid := '1';
1129             end if;
1130             -- Handling an ITLB miss doesn't count as having executed an instruction
1131             if e_in.insn_type = OP_FETCH_FAILED then
1132                 do_trace := '0';
1133             end if;
1134         end if;
1135
1136         -- The following cases all occur when r.busy = 1 and therefore
1137         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1138         -- the cases above which depend on valid_in = 1.
1139
1140         if r.f.redirect = '1' then
1141             v.e.valid := '1';
1142         end if;
1143         if r.lr_update = '1' then
1144             v.e.exc_write_enable := '1';
1145             v.e.exc_write_data := r.next_lr;
1146             v.e.exc_write_reg := fast_spr_num(SPR_LR);
1147             v.e.valid := '1';
1148             -- Keep r.e.write_data unchanged next cycle in case it is needed
1149             -- for a forwarded result (e.g. for CTR).
1150             result := r.e.write_data;
1151         elsif r.cntz_in_progress = '1' then
1152             -- cnt[lt]z always takes two cycles
1153             result := countzero_result;
1154             result_en := '1';
1155             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1156             v.e.rc := r.slow_op_rc;
1157             v.e.xerc := r.slow_op_xerc;
1158             v.e.valid := '1';
1159         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1160             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1161                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1162                 if r.mul_in_progress = '1' then
1163                     overflow := '0';
1164                     case r.slow_op_insn is
1165                         when OP_MUL_H32 =>
1166                             result := multiply_to_x.result(63 downto 32) &
1167                                       multiply_to_x.result(63 downto 32);
1168                         when OP_MUL_H64 =>
1169                             result := multiply_to_x.result(127 downto 64);
1170                         when others =>
1171                             -- i.e. OP_MUL_L64
1172                             result := multiply_to_x.result(63 downto 0);
1173                     end case;
1174                 else
1175                     result := divider_to_x.write_reg_data;
1176                     overflow := divider_to_x.overflow;
1177                 end if;
1178                 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1179                     -- have to wait until next cycle for overflow indication
1180                     v.mul_finish := '1';
1181                     v.busy := '1';
1182                 else
1183                     result_en := '1';
1184                     v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1185                     v.e.rc := r.slow_op_rc;
1186                     v.e.xerc := r.slow_op_xerc;
1187                     v.e.write_xerc_enable := r.slow_op_oe;
1188                     -- We must test oe because the RC update code in writeback
1189                     -- will use the xerc value to set CR0:SO so we must not clobber
1190                     -- xerc if OE wasn't set.
1191                     if r.slow_op_oe = '1' then
1192                         v.e.xerc.ov := overflow;
1193                         v.e.xerc.ov32 := overflow;
1194                         v.e.xerc.so := r.slow_op_xerc.so or overflow;
1195                     end if;
1196                     v.e.valid := '1';
1197                 end if;
1198             else
1199                 v.busy := '1';
1200                 v.mul_in_progress := r.mul_in_progress;
1201                 v.div_in_progress := r.div_in_progress;
1202             end if;
1203         elsif r.mul_finish = '1' then
1204             result := r.e.write_data;
1205             result_en := '1';
1206             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1207             v.e.rc := r.slow_op_rc;
1208             v.e.xerc := r.slow_op_xerc;
1209             v.e.write_xerc_enable := r.slow_op_oe;
1210             v.e.xerc.ov := multiply_to_x.overflow;
1211             v.e.xerc.ov32 := multiply_to_x.overflow;
1212             v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1213             v.e.valid := '1';
1214         end if;
1215
1216         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1217         -- be set during the execution of a FP instruction.
1218         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1219         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1220         if HAS_FPU and fp_in.interrupt = '1' then
1221             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1222             ctrl_tmp.srr1(63 - 43) <= '1';
1223             exception := '1';
1224         end if;
1225
1226         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1227             exception := '1';
1228             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1229             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1230             -- set bit 44 to indicate we have an illegal
1231             ctrl_tmp.srr1(63 - 44) <= '1';
1232             report "illegal";
1233         end if;
1234         if exception = '1' then
1235             v.e.exc_write_enable := '1';
1236             if exception_nextpc = '1' then
1237                 v.e.exc_write_data := next_nia;
1238             end if;
1239         end if;
1240
1241         if do_trace = '1' then
1242             v.trace_next := '1';
1243         end if;
1244
1245         v.e.write_data := result;
1246         v.e.write_enable := result_en and not exception;
1247
1248         -- generate DSI or DSegI for load/store exceptions
1249         -- or ISI or ISegI for instruction fetch exceptions
1250         if l_in.exception = '1' then
1251             if l_in.alignment = '1' then
1252                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#600#, 64));
1253             elsif l_in.instr_fault = '0' then
1254                 if l_in.segment_fault = '0' then
1255                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1256                 else
1257                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1258                 end if;
1259             else
1260                 if l_in.segment_fault = '0' then
1261                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1262                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1263                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1264                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1265                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1266                 else
1267                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1268                 end if;
1269             end if;
1270             v.e.exc_write_enable := '1';
1271             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1272             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1273         end if;
1274
1275         if exception = '1' or l_in.exception = '1' then
1276             ctrl_tmp.irq_state <= WRITE_SRR1;
1277             v.f.redirect := '1';
1278             v.f.virt_mode := '0';
1279             v.f.priv_mode := '1';
1280             -- XXX need an interrupt LE bit here, e.g. from LPCR
1281             v.f.big_endian := '0';
1282             v.f.mode_32bit := '0';
1283         end if;
1284
1285         if v.f.redirect = '1' then
1286             v.busy := '1';
1287             v.e.valid := '0';
1288         end if;
1289
1290         -- Outputs to loadstore1 (async)
1291         lv.op := e_in.insn_type;
1292         lv.nia := e_in.nia;
1293         lv.addr1 := a_in;
1294         lv.addr2 := b_in;
1295         lv.data := c_in;
1296         lv.write_reg := e_in.write_reg;
1297         lv.length := e_in.data_len;
1298         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1299         lv.sign_extend := e_in.sign_extend;
1300         lv.update := e_in.update;
1301         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1302         lv.xerc := v.e.xerc;
1303         lv.reserve := e_in.reserve;
1304         lv.rc := e_in.rc;
1305         lv.insn := e_in.insn;
1306         -- decode l*cix and st*cix instructions here
1307         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1308             e_in.insn(5 downto 1) = "10101" then
1309             lv.ci := '1';
1310         end if;
1311         lv.virt_mode := ctrl.msr(MSR_DR);
1312         lv.priv_mode := not ctrl.msr(MSR_PR);
1313         lv.mode_32bit := not ctrl.msr(MSR_SF);
1314         lv.is_32bit := e_in.is_32bit;
1315
1316         -- Outputs to FPU
1317         fv.op := e_in.insn_type;
1318         fv.nia := e_in.nia;
1319         fv.insn := e_in.insn;
1320         fv.single := e_in.is_32bit;
1321         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1322         fv.fra := a_in;
1323         fv.frb := b_in;
1324         fv.frc := c_in;
1325         fv.frt := e_in.write_reg;
1326         fv.rc := e_in.rc;
1327         fv.out_cr := e_in.output_cr;
1328
1329         -- Update registers
1330         rin <= v;
1331
1332         -- update outputs
1333         f_out <= r.f;
1334         l_out <= lv;
1335         e_out <= r.e;
1336         fp_out <= fv;
1337         flush_out <= f_out.redirect;
1338
1339         exception_log <= exception;
1340         irq_valid_log <= irq_valid;
1341     end process;
1342
1343     e1_log: if LOG_LENGTH > 0 generate
1344         signal log_data : std_ulogic_vector(14 downto 0);
1345     begin
1346         ex1_log : process(clk)
1347         begin
1348             if rising_edge(clk) then
1349                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1350                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1351                             exception_log &
1352                             irq_valid_log &
1353                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1354                             "000" &
1355                             r.e.write_enable &
1356                             r.e.valid &
1357                             f_out.redirect &
1358                             r.busy &
1359                             flush_out;
1360             end if;
1361         end process;
1362         log_out <= log_data;
1363     end generate;
1364 end architecture behaviour;