execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40
  41         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  42
  43         icache_inval : out std_ulogic;
  44         terminate_out : out std_ulogic;
  45
  46         log_out : out std_ulogic_vector(14 downto 0);
  47         log_rd_addr : out std_ulogic_vector(31 downto 0);
  48         log_rd_data : in std_ulogic_vector(63 downto 0);
  49         log_wr_addr : in std_ulogic_vector(31 downto 0)
  50         );
  51 end entity execute1;
  52
  53 architecture behaviour of execute1 is
  54     type reg_type is record
  55         e : Execute1ToWritebackType;
  56         cur_instr : Decode2ToExecute1Type;
  57         busy: std_ulogic;
  58         terminate: std_ulogic;
  59         fp_exception_next : std_ulogic;
  60         trace_next : std_ulogic;
  61         prev_op : insn_type_t;
  62         lr_update : std_ulogic;
  63         next_lr : std_ulogic_vector(63 downto 0);
  64         mul_in_progress : std_ulogic;
  65         mul_finish : std_ulogic;
  66         div_in_progress : std_ulogic;
  67         cntz_in_progress : std_ulogic;
  68         last_nia : std_ulogic_vector(63 downto 0);
  69         redirect : std_ulogic;
  70         abs_br : std_ulogic;
  71         do_intr : std_ulogic;
  72         vector : integer range 0 to 16#fff#;
  73         br_offset : std_ulogic_vector(63 downto 0);
  74         redir_mode : std_ulogic_vector(3 downto 0);
  75         log_addr_spr : std_ulogic_vector(31 downto 0);
  76     end record;
  77     constant reg_type_init : reg_type :=
  78         (e => Execute1ToWritebackInit,
  79          cur_instr => Decode2ToExecute1Init,
  80          busy => '0', lr_update => '0', terminate => '0',
  81          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL,
  82          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  83          next_lr => (others => '0'), last_nia => (others => '0'),
  84          redirect => '0', abs_br => '0', do_intr => '0', vector => 0,
  85          br_offset => (others => '0'), redir_mode => "0000",
  86          others => (others => '0'));
  87
  88     signal r, rin : reg_type;
  89
  90     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  91     signal cr_in : std_ulogic_vector(31 downto 0);
  92
  93     signal valid_in : std_ulogic;
  94     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  95     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  96     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  97     signal rot_sign_ext: std_ulogic;
  98     signal rotator_result: std_ulogic_vector(63 downto 0);
  99     signal rotator_carry: std_ulogic;
 100     signal logical_result: std_ulogic_vector(63 downto 0);
 101     signal countzero_result: std_ulogic_vector(63 downto 0);
 102     signal alu_result: std_ulogic_vector(63 downto 0);
 103     signal adder_result: std_ulogic_vector(63 downto 0);
 104     signal misc_result: std_ulogic_vector(63 downto 0);
 105     signal muldiv_result: std_ulogic_vector(63 downto 0);
 106     signal spr_result: std_ulogic_vector(63 downto 0);
 107     signal result_mux_sel: std_ulogic_vector(2 downto 0);
 108     signal sub_mux_sel: std_ulogic_vector(2 downto 0);
 109     signal current: Decode2ToExecute1Type;
 110
 111     -- multiply signals
 112     signal x_to_multiply: MultiplyInputType;
 113     signal multiply_to_x: MultiplyOutputType;
 114
 115     -- divider signals
 116     signal x_to_divider: Execute1ToDividerType;
 117     signal divider_to_x: DividerToExecute1Type;
 118
 119     -- random number generator signals
 120     signal random_raw  : std_ulogic_vector(63 downto 0);
 121     signal random_cond : std_ulogic_vector(63 downto 0);
 122     signal random_err  : std_ulogic;
 123
 124     -- signals for logging
 125     signal exception_log : std_ulogic;
 126     signal irq_valid_log : std_ulogic;
 127
 128     type privilege_level is (USER, SUPER);
 129     type op_privilege_array is array(insn_type_t) of privilege_level;
 130     constant op_privilege: op_privilege_array := (
 131         OP_ATTN => SUPER,
 132         OP_MFMSR => SUPER,
 133         OP_MTMSRD => SUPER,
 134         OP_RFID => SUPER,
 135         OP_TLBIE => SUPER,
 136         others => USER
 137         );
 138
 139     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 140         return boolean is
 141     begin
 142         if op_privilege(op) = SUPER then
 143             return true;
 144         elsif op = OP_MFSPR or op = OP_MTSPR then
 145             return insn(20) = '1';
 146         else
 147             return false;
 148         end if;
 149     end;
 150
 151     procedure set_carry(e: inout Execute1ToWritebackType;
 152                         carry32 : in std_ulogic;
 153                         carry : in std_ulogic) is
 154     begin
 155         e.xerc.ca32 := carry32;
 156         e.xerc.ca := carry;
 157         e.write_xerc_enable := '1';
 158     end;
 159
 160     procedure set_ov(e: inout Execute1ToWritebackType;
 161                      ov   : in std_ulogic;
 162                      ov32 : in std_ulogic) is
 163     begin
 164         e.xerc.ov32 := ov32;
 165         e.xerc.ov := ov;
 166         if ov = '1' then
 167             e.xerc.so := '1';
 168         end if;
 169         e.write_xerc_enable := '1';
 170     end;
 171
 172     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 173                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 174     begin
 175         return (ca xor msb_r) and not (msb_a xor msb_b);
 176     end;
 177
 178     function decode_input_carry(ic : carry_in_t;
 179                                 xerc : xer_common_t) return std_ulogic is
 180     begin
 181         case ic is
 182         when ZERO =>
 183             return '0';
 184         when CA =>
 185             return xerc.ca;
 186         when OV =>
 187             return xerc.ov;
 188         when ONE =>
 189             return '1';
 190         end case;
 191     end;
 192
 193     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 194         return std_ulogic_vector is
 195         variable msr_out: std_ulogic_vector(63 downto 0);
 196     begin
 197         -- ISA says this:
 198         --  Defined MSR bits are classified as either full func-
 199         --  tion or partial function. Full function MSR bits are
 200         --  saved in SRR1 or HSRR1 when an interrupt other
 201         --  than a System Call Vectored interrupt occurs and
 202         --  restored by rfscv, rfid, or hrfid, while partial func-
 203         --  tion MSR bits are not saved or restored.
 204         --  Full function MSR bits lie in the range 0:32, 37:41, and
 205         --  48:63, and partial function MSR bits lie in the range
 206         --  33:36 and 42:47. (Note this is IBM bit numbering).
 207         msr_out := (others => '0');
 208         msr_out(63 downto 31) := msr(63 downto 31);
 209         msr_out(26 downto 22) := msr(26 downto 22);
 210         msr_out(15 downto 0)  := msr(15 downto 0);
 211         return msr_out;
 212     end;
 213
 214     -- Tell vivado to keep the hierarchy for the random module so that the
 215     -- net names in the xdc file match.
 216     attribute keep_hierarchy : string;
 217     attribute keep_hierarchy of random_0 : label is "yes";
 218
 219 begin
 220
 221     rotator_0: entity work.rotator
 222         port map (
 223             rs => c_in,
 224             ra => a_in,
 225             shift => b_in(6 downto 0),
 226             insn => e_in.insn,
 227             is_32bit => e_in.is_32bit,
 228             right_shift => right_shift,
 229             arith => e_in.is_signed,
 230             clear_left => rot_clear_left,
 231             clear_right => rot_clear_right,
 232             sign_ext_rs => rot_sign_ext,
 233             result => rotator_result,
 234             carry_out => rotator_carry
 235             );
 236
 237     logical_0: entity work.logical
 238         port map (
 239             rs => c_in,
 240             rb => b_in,
 241             op => e_in.insn_type,
 242             invert_in => e_in.invert_a,
 243             invert_out => e_in.invert_out,
 244             result => logical_result,
 245             datalen => e_in.data_len
 246             );
 247
 248     countzero_0: entity work.zero_counter
 249         port map (
 250             clk => clk,
 251             rs => c_in,
 252             count_right => e_in.insn(10),
 253             is_32bit => e_in.is_32bit,
 254             result => countzero_result
 255             );
 256
 257     multiply_0: entity work.multiply
 258         port map (
 259             clk => clk,
 260             m_in => x_to_multiply,
 261             m_out => multiply_to_x
 262             );
 263
 264     divider_0: entity work.divider
 265         port map (
 266             clk => clk,
 267             rst => rst,
 268             d_in => x_to_divider,
 269             d_out => divider_to_x
 270             );
 271
 272     random_0: entity work.random
 273         port map (
 274             clk => clk,
 275             data => random_cond,
 276             raw => random_raw,
 277             err => random_err
 278             );
 279
 280     dbg_msr_out <= ctrl.msr;
 281     log_rd_addr <= r.log_addr_spr;
 282
 283     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 284     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 285     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 286
 287     busy_out <= l_in.busy or r.busy or fp_in.busy;
 288     valid_in <= e_in.valid and not busy_out;
 289
 290     terminate_out <= r.terminate;
 291
 292     current <= e_in when r.busy = '0' else r.cur_instr;
 293
 294     -- Result mux
 295     with current.result_sel select alu_result <=
 296         adder_result       when "000",
 297         logical_result     when "001",
 298         rotator_result     when "010",
 299         muldiv_result      when "011",
 300         countzero_result   when "100",
 301         spr_result         when "101",
 302         misc_result        when others;
 303
 304     execute1_0: process(clk)
 305     begin
 306         if rising_edge(clk) then
 307             if rst = '1' then
 308                 r <= reg_type_init;
 309                 ctrl.tb <= (others => '0');
 310                 ctrl.dec <= (others => '0');
 311                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 312                 ctrl.irq_state <= WRITE_SRR0;
 313             else
 314                 r <= rin;
 315                 ctrl <= ctrl_tmp;
 316                 assert not (r.lr_update = '1' and valid_in = '1')
 317                     report "LR update collision with valid in EX1"
 318                     severity failure;
 319                 if r.lr_update = '1' then
 320                     report "LR update to " & to_hstring(r.next_lr);
 321                 end if;
 322             end if;
 323         end if;
 324     end process;
 325
 326     execute1_1: process(all)
 327         variable v : reg_type;
 328         variable a_inv : std_ulogic_vector(63 downto 0);
 329         variable b_or_m1 : std_ulogic_vector(63 downto 0);
 330         variable addg6s : std_ulogic_vector(63 downto 0);
 331         variable isel_result : std_ulogic_vector(63 downto 0);
 332         variable darn : std_ulogic_vector(63 downto 0);
 333         variable mfcr_result : std_ulogic_vector(63 downto 0);
 334         variable setb_result : std_ulogic_vector(63 downto 0);
 335         variable newcrf : std_ulogic_vector(3 downto 0);
 336         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 337         variable crnum : crnum_t;
 338         variable crbit : integer range 0 to 31;
 339         variable scrnum : crnum_t;
 340         variable lo, hi : integer;
 341         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 342         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 343         variable bo, bi : std_ulogic_vector(4 downto 0);
 344         variable bf, bfa : std_ulogic_vector(2 downto 0);
 345         variable cr_op : std_ulogic_vector(9 downto 0);
 346         variable cr_operands : std_ulogic_vector(1 downto 0);
 347         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 348         variable btnum, banum, bbnum : integer range 0 to 31;
 349         variable crresult : std_ulogic;
 350         variable l : std_ulogic;
 351         variable next_nia : std_ulogic_vector(63 downto 0);
 352         variable carry_32, carry_64 : std_ulogic;
 353         variable sign1, sign2 : std_ulogic;
 354         variable abs1, abs2 : signed(63 downto 0);
 355         variable overflow : std_ulogic;
 356         variable zerohi, zerolo : std_ulogic;
 357         variable msb_a, msb_b : std_ulogic;
 358         variable a_lt : std_ulogic;
 359         variable lv : Execute1ToLoadstore1Type;
 360         variable irq_valid : std_ulogic;
 361         variable exception : std_ulogic;
 362         variable exception_nextpc : std_ulogic;
 363         variable trapval : std_ulogic_vector(4 downto 0);
 364         variable illegal : std_ulogic;
 365         variable is_branch : std_ulogic;
 366         variable taken_branch : std_ulogic;
 367         variable abs_branch : std_ulogic;
 368         variable spr_val : std_ulogic_vector(63 downto 0);
 369         variable addend : std_ulogic_vector(127 downto 0);
 370         variable do_trace : std_ulogic;
 371         variable hold_wr_data : std_ulogic;
 372         variable f : Execute1ToFetch1Type;
 373         variable fv : Execute1ToFPUType;
 374     begin
 375         sum_with_carry := (others => '0');
 376         newcrf := (others => '0');
 377         is_branch := '0';
 378         taken_branch := '0';
 379         abs_branch := '0';
 380         hold_wr_data := '0';
 381
 382         v := r;
 383         v.e := Execute1ToWritebackInit;
 384         v.redirect := '0';
 385         v.abs_br := '0';
 386         v.do_intr := '0';
 387         v.vector := 0;
 388         v.br_offset := (others => '0');
 389         v.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
 390                         not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
 391
 392         lv := Execute1ToLoadstore1Init;
 393         fv := Execute1ToFPUInit;
 394
 395         -- XER forwarding. To avoid having to track XER hazards, we use
 396         -- the previously latched value.  Since the XER common bits
 397         -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 398         -- handled here, we can just forward the result being sent to
 399         -- writeback.
 400         if r.e.write_xerc_enable = '1' or r.busy = '1' then
 401             v.e.xerc := r.e.xerc;
 402         else
 403             v.e.xerc := e_in.xerc;
 404         end if;
 405
 406         -- CR forwarding
 407         cr_in <= e_in.cr;
 408         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 409             for i in 0 to 7 loop
 410                 if r.e.write_cr_mask(i) = '1' then
 411                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 412                 end if;
 413             end loop;
 414         end if;
 415
 416         v.lr_update := '0';
 417         v.mul_in_progress := '0';
 418         v.div_in_progress := '0';
 419         v.cntz_in_progress := '0';
 420         v.mul_finish := '0';
 421
 422         spr_result <= (others => '0');
 423         spr_val := (others => '0');
 424
 425         -- Main adder
 426         if e_in.invert_a = '0' then
 427             a_inv := a_in;
 428         else
 429             a_inv := not a_in;
 430         end if;
 431         if e_in.addm1 = '0' then
 432             b_or_m1 := b_in;
 433         else
 434             b_or_m1 := (others => '1');
 435         end if;
 436         sum_with_carry := ppc_adde(a_inv, b_or_m1,
 437                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 438         adder_result <= sum_with_carry(63 downto 0);
 439         carry_32 := sum_with_carry(32) xor a_inv(32) xor b_in(32);
 440         carry_64 := sum_with_carry(64);
 441
 442         -- signals to multiply and divide units
 443         sign1 := '0';
 444         sign2 := '0';
 445         if e_in.is_signed = '1' then
 446             if e_in.is_32bit = '1' then
 447                 sign1 := a_in(31);
 448                 sign2 := b_in(31);
 449             else
 450                 sign1 := a_in(63);
 451                 sign2 := b_in(63);
 452             end if;
 453         end if;
 454         -- take absolute values
 455         if sign1 = '0' then
 456             abs1 := signed(a_in);
 457         else
 458             abs1 := - signed(a_in);
 459         end if;
 460         if sign2 = '0' then
 461             abs2 := signed(b_in);
 462         else
 463             abs2 := - signed(b_in);
 464         end if;
 465
 466         -- Interface to multiply and divide units
 467         x_to_multiply <= MultiplyInputInit;
 468         x_to_multiply.is_32bit <= e_in.is_32bit;
 469
 470         x_to_divider <= Execute1ToDividerInit;
 471         x_to_divider.is_signed <= e_in.is_signed;
 472         x_to_divider.is_32bit <= e_in.is_32bit;
 473         if e_in.insn_type = OP_MOD then
 474             x_to_divider.is_modulus <= '1';
 475         end if;
 476
 477         addend := (others => '0');
 478         if e_in.insn(26) = '0' then
 479             -- integer multiply-add, major op 4 (if it is a multiply)
 480             addend(63 downto 0) := c_in;
 481             if e_in.is_signed = '1' then
 482                 addend(127 downto 64) := (others => c_in(63));
 483             end if;
 484         end if;
 485         if (sign1 xor sign2) = '1' then
 486             addend := not addend;
 487         end if;
 488
 489         x_to_multiply.not_result <= sign1 xor sign2;
 490         x_to_multiply.addend <= addend;
 491         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 492         if e_in.is_32bit = '0' then
 493             -- 64-bit forms
 494             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 495             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 496             if e_in.insn_type = OP_DIVE then
 497                 x_to_divider.is_extended <= '1';
 498             end if;
 499             x_to_divider.dividend <= std_ulogic_vector(abs1);
 500             x_to_divider.divisor <= std_ulogic_vector(abs2);
 501         else
 502             -- 32-bit forms
 503             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 504             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 505             x_to_divider.is_extended <= '0';
 506             if e_in.insn_type = OP_DIVE then   -- extended forms
 507                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 508             else
 509                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 510             end if;
 511             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 512         end if;
 513
 514         case current.sub_select(1 downto 0) is
 515             when "00" =>
 516                 muldiv_result <= multiply_to_x.result(63 downto 0);
 517             when "01" =>
 518                 muldiv_result <= multiply_to_x.result(127 downto 64);
 519             when "10" =>
 520                 muldiv_result <= multiply_to_x.result(63 downto 32) &
 521                                  multiply_to_x.result(63 downto 32);
 522             when others =>
 523                 muldiv_result <= divider_to_x.write_reg_data;
 524         end case;
 525
 526         -- Compute misc_result
 527         case current.sub_select is
 528             when "000" =>
 529                 misc_result <= (others => '0');
 530             when "001" =>
 531                 -- addg6s
 532                 addg6s := (others => '0');
 533                 for i in 0 to 14 loop
 534                     lo := i * 4;
 535                     hi := (i + 1) * 4;
 536                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 537                         addg6s(lo + 3 downto lo) := "0110";
 538                     end if;
 539                 end loop;
 540                 if sum_with_carry(64) = '0' then
 541                     addg6s(63 downto 60) := "0110";
 542                 end if;
 543                 misc_result <= addg6s;
 544             when "010" =>
 545                 -- isel
 546                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 547                 if cr_in(31-crbit) = '1' then
 548                     isel_result := a_in;
 549                 else
 550                     isel_result := b_in;
 551                 end if;
 552                 misc_result <= isel_result;
 553             when "011" =>
 554                 -- darn
 555                 darn := (others => '1');
 556                 if random_err = '0' then
 557                     case e_in.insn(17 downto 16) is
 558                         when "00" =>
 559                             darn := x"00000000" & random_cond(31 downto 0);
 560                         when "10" =>
 561                             darn := random_raw;
 562                         when others =>
 563                             darn := random_cond;
 564                     end case;
 565                 end if;
 566                 misc_result <= darn;
 567             when "100" =>
 568                 -- mfmsr
 569                 misc_result <= ctrl.msr;
 570             when "101" =>
 571                 if e_in.insn(20) = '0' then
 572                     -- mfcr
 573                     mfcr_result := x"00000000" & cr_in;
 574                 else
 575                     -- mfocrf
 576                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 577                     mfcr_result := (others => '0');
 578                     for i in 0 to 7 loop
 579                         lo := (7-i)*4;
 580                         hi := lo + 3;
 581                         if crnum = i then
 582                             mfcr_result(hi downto lo) := cr_in(hi downto lo);
 583                         end if;
 584                     end loop;
 585                 end if;
 586                 misc_result <= mfcr_result;
 587             when "110" =>
 588                 -- setb
 589                 bfa := insn_bfa(e_in.insn);
 590                 crbit := to_integer(unsigned(bfa)) * 4;
 591                 setb_result := (others => '0');
 592                 if cr_in(31 - crbit) = '1' then
 593                     setb_result := (others => '1');
 594                 elsif cr_in(30 - crbit) = '1' then
 595                     setb_result(0) := '1';
 596                 end if;
 597                 misc_result <= setb_result;
 598             when others =>
 599                 misc_result <= (others => '0');
 600         end case;
 601
 602         -- compute comparison results
 603         -- Note, we have done RB - RA, not RA - RB
 604         if e_in.insn_type = OP_CMP then
 605             l := insn_l(e_in.insn);
 606         else
 607             l := not e_in.is_32bit;
 608         end if;
 609         zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 610         zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 611         if zerolo = '1' and (l = '0' or zerohi = '1') then
 612             -- values are equal
 613             trapval := "00100";
 614         else
 615             if l = '1' then
 616                 -- 64-bit comparison
 617                 msb_a := a_in(63);
 618                 msb_b := b_in(63);
 619             else
 620                 -- 32-bit comparison
 621                 msb_a := a_in(31);
 622                 msb_b := b_in(31);
 623             end if;
 624             if msb_a /= msb_b then
 625                 -- Subtraction might overflow, but
 626                 -- comparison is clear from MSB difference.
 627                 -- for signed, 0 is greater; for unsigned, 1 is greater
 628                 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 629             else
 630                 -- Subtraction cannot overflow since MSBs are equal.
 631                 -- carry = 1 indicates RA is smaller (signed or unsigned)
 632                 a_lt := (not l and carry_32) or (l and carry_64);
 633                 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 634             end if;
 635         end if;
 636
 637         ctrl_tmp <= ctrl;
 638         -- FIXME: run at 512MHz not core freq
 639         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 640         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 641
 642         irq_valid := '0';
 643         if ctrl.msr(MSR_EE) = '1' then
 644             if ctrl.dec(63) = '1' then
 645                 v.vector := 16#900#;
 646                 report "IRQ valid: DEC";
 647                 irq_valid := '1';
 648             elsif ext_irq_in = '1' then
 649                 v.vector := 16#500#;
 650                 report "IRQ valid: External";
 651                 irq_valid := '1';
 652             end if;
 653         end if;
 654
 655         v.terminate := '0';
 656         icache_inval <= '0';
 657         v.busy := '0';
 658
 659         -- Next insn adder used in a couple of places
 660         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 661
 662         -- rotator control signals
 663         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 664         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 665         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 666         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 667
 668         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 669         ctrl_tmp.irq_state <= WRITE_SRR0;
 670         exception := '0';
 671         illegal := '0';
 672         exception_nextpc := '0';
 673         v.e.exc_write_enable := '0';
 674         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 675         if valid_in = '1' then
 676             v.e.exc_write_data := e_in.nia;
 677             v.last_nia := e_in.nia;
 678         else
 679             v.e.exc_write_data := r.last_nia;
 680         end if;
 681
 682         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 683
 684         do_trace := valid_in and ctrl.msr(MSR_SE);
 685         if valid_in = '1' then
 686             v.prev_op := e_in.insn_type;
 687         end if;
 688
 689         -- Determine if there is any exception to be taken
 690         -- before/instead of executing this instruction
 691         if valid_in = '1' and e_in.second = '0' then
 692             if HAS_FPU and r.fp_exception_next = '1' then
 693                 -- This is used for FP-type program interrupts that
 694                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 695                 exception := '1';
 696                 v.vector := 16#700#;
 697                 ctrl_tmp.srr1(63 - 43) <= '1';
 698                 ctrl_tmp.srr1(63 - 47) <= '1';
 699             elsif r.trace_next = '1' then
 700                 -- Generate a trace interrupt rather than executing the next instruction
 701                 -- or taking any asynchronous interrupt
 702                 exception := '1';
 703                 v.vector := 16#d00#;
 704                 ctrl_tmp.srr1(63 - 33) <= '1';
 705                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 706                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 707                     ctrl_tmp.srr1(63 - 35) <= '1';
 708                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 709                     ctrl_tmp.srr1(63 - 36) <= '1';
 710                 end if;
 711
 712             elsif irq_valid = '1' then
 713                 -- Don't deliver the interrupt until we have a valid instruction
 714                 -- coming in, so we have a valid NIA to put in SRR0.
 715                 exception := '1';
 716
 717             elsif ctrl.msr(MSR_PR) = '1' and instr_is_privileged(e_in.insn_type, e_in.insn) then
 718                 -- generate a program interrupt
 719                 exception := '1';
 720                 v.vector := 16#700#;
 721                 -- set bit 45 to indicate privileged instruction type interrupt
 722                 ctrl_tmp.srr1(63 - 45) <= '1';
 723                 report "privileged instruction";
 724
 725             elsif not HAS_FPU and e_in.fac = FPU then
 726                 -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 727                 illegal := '1';
 728
 729             elsif HAS_FPU and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 730                 -- generate a floating-point unavailable interrupt
 731                 exception := '1';
 732                 v.vector := 16#800#;
 733                 report "FP unavailable interrupt";
 734             end if;
 735         end if;
 736
 737         if valid_in = '1' and exception = '0' and illegal = '0' and e_in.unit = ALU then
 738             report "execute nia " & to_hstring(e_in.nia);
 739
 740             v.cur_instr := e_in;
 741             v.next_lr := next_nia;
 742             v.e.valid := '1';
 743
 744             case_0: case e_in.insn_type is
 745
 746             when OP_ILLEGAL =>
 747                 -- we need two cycles to write srr0 and 1
 748                 -- will need more when we have to write HEIR
 749                 illegal := '1';
 750             when OP_SC =>
 751                 -- check bit 1 of the instruction is 1 so we know this is sc;
 752                 -- 0 would mean scv, so generate an illegal instruction interrupt
 753                 -- we need two cycles to write srr0 and 1
 754                 if e_in.insn(1) = '1' then
 755                     exception := '1';
 756                     exception_nextpc := '1';
 757                     v.vector := 16#C00#;
 758                     report "sc";
 759                 else
 760                     illegal := '1';
 761                 end if;
 762             when OP_ATTN =>
 763                 -- check bits 1-10 of the instruction to make sure it's attn
 764                 -- if not then it is illegal
 765                 if e_in.insn(10 downto 1) = "0100000000" then
 766                     v.terminate := '1';
 767                     report "ATTN";
 768                 else
 769                     illegal := '1';
 770                 end if;
 771             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 772                 -- Do nothing
 773             when OP_ADD =>
 774                 if e_in.output_carry = '1' then
 775                     if e_in.input_carry /= OV then
 776                         set_carry(v.e, carry_32, carry_64);
 777                     else
 778                         v.e.xerc.ov := carry_64;
 779                         v.e.xerc.ov32 := carry_32;
 780                         v.e.write_xerc_enable := '1';
 781                     end if;
 782                 end if;
 783                 if e_in.oe = '1' then
 784                     set_ov(v.e,
 785                            calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 786                            calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 787                 end if;
 788             when OP_CMP =>
 789                 -- CMP and CMPL instructions
 790                 if e_in.is_signed = '1' then
 791                     newcrf := trapval(4 downto 2) & v.e.xerc.so;
 792                 else
 793                     newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 794                 end if;
 795                 bf := insn_bf(e_in.insn);
 796                 crnum := to_integer(unsigned(bf));
 797                 v.e.write_cr_enable := '1';
 798                 v.e.write_cr_mask := num_to_fxm(crnum);
 799                 for i in 0 to 7 loop
 800                     lo := i*4;
 801                     hi := lo + 3;
 802                     v.e.write_cr_data(hi downto lo) := newcrf;
 803                 end loop;
 804             when OP_TRAP =>
 805                 -- trap instructions (tw, twi, td, tdi)
 806                 v.vector := 16#700#;
 807                 -- set bit 46 to say trap occurred
 808                 ctrl_tmp.srr1(63 - 46) <= '1';
 809                 if or (trapval and insn_to(e_in.insn)) = '1' then
 810                     -- generate trap-type program interrupt
 811                     exception := '1';
 812                     report "trap";
 813                 end if;
 814             when OP_ADDG6S =>
 815             when OP_CMPRB =>
 816                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 817                 bf := insn_bf(e_in.insn);
 818                 crnum := to_integer(unsigned(bf));
 819                 v.e.write_cr_enable := '1';
 820                 v.e.write_cr_mask := num_to_fxm(crnum);
 821                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 822                                      newcrf & newcrf & newcrf & newcrf;
 823             when OP_CMPEQB =>
 824                 newcrf := ppc_cmpeqb(a_in, b_in);
 825                 bf := insn_bf(e_in.insn);
 826                 crnum := to_integer(unsigned(bf));
 827                 v.e.write_cr_enable := '1';
 828                 v.e.write_cr_mask := num_to_fxm(crnum);
 829                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 830                                      newcrf & newcrf & newcrf & newcrf;
 831             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 832                     OP_BPERM | OP_BCD =>
 833             when OP_B =>
 834                 is_branch := '1';
 835                 taken_branch := '1';
 836                 abs_branch := insn_aa(e_in.insn);
 837                 if ctrl.msr(MSR_BE) = '1' then
 838                     do_trace := '1';
 839                 end if;
 840             when OP_BC =>
 841                 -- read_data1 is CTR
 842                 bo := insn_bo(e_in.insn);
 843                 bi := insn_bi(e_in.insn);
 844                 is_branch := '1';
 845                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 846                 abs_branch := insn_aa(e_in.insn);
 847                 if ctrl.msr(MSR_BE) = '1' then
 848                     do_trace := '1';
 849                 end if;
 850             when OP_BCREG =>
 851                 -- read_data1 is CTR
 852                 -- read_data2 is target register (CTR, LR or TAR)
 853                 bo := insn_bo(e_in.insn);
 854                 bi := insn_bi(e_in.insn);
 855                 is_branch := '1';
 856                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 857                 abs_branch := '1';
 858                 if ctrl.msr(MSR_BE) = '1' then
 859                     do_trace := '1';
 860                 end if;
 861
 862             when OP_RFID =>
 863                 v.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
 864                                 not a_in(MSR_LE) & not a_in(MSR_SF);
 865                 -- Can't use msr_copy here because the partial function MSR
 866                 -- bits should be left unchanged, not zeroed.
 867                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 868                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 869                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 870                 if a_in(MSR_PR) = '1' then
 871                     ctrl_tmp.msr(MSR_EE) <= '1';
 872                     ctrl_tmp.msr(MSR_IR) <= '1';
 873                     ctrl_tmp.msr(MSR_DR) <= '1';
 874                 end if;
 875                 -- mark this as a branch so CFAR gets updated
 876                 is_branch := '1';
 877                 taken_branch := '1';
 878                 abs_branch := '1';
 879                 if HAS_FPU then
 880                     v.fp_exception_next := fp_in.exception and
 881                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 882                 end if;
 883                 do_trace := '0';
 884
 885             when OP_CNTZ =>
 886                 v.e.valid := '0';
 887                 v.cntz_in_progress := '1';
 888                 v.busy := '1';
 889             when OP_ISEL =>
 890             when OP_CROP =>
 891                 cr_op := insn_cr(e_in.insn);
 892                 report "CR OP " & to_hstring(cr_op);
 893                 if cr_op(0) = '0' then -- MCRF
 894                     bf := insn_bf(e_in.insn);
 895                     bfa := insn_bfa(e_in.insn);
 896                     v.e.write_cr_enable := '1';
 897                     crnum := to_integer(unsigned(bf));
 898                     scrnum := to_integer(unsigned(bfa));
 899                     v.e.write_cr_mask := num_to_fxm(crnum);
 900                     for i in 0 to 7 loop
 901                         lo := (7-i)*4;
 902                         hi := lo + 3;
 903                         if i = scrnum then
 904                             newcrf := cr_in(hi downto lo);
 905                         end if;
 906                     end loop;
 907                     for i in 0 to 7 loop
 908                         lo := i*4;
 909                         hi := lo + 3;
 910                         v.e.write_cr_data(hi downto lo) := newcrf;
 911                     end loop;
 912                 else
 913                     v.e.write_cr_enable := '1';
 914                     bt := insn_bt(e_in.insn);
 915                     ba := insn_ba(e_in.insn);
 916                     bb := insn_bb(e_in.insn);
 917                     btnum := 31 - to_integer(unsigned(bt));
 918                     banum := 31 - to_integer(unsigned(ba));
 919                     bbnum := 31 - to_integer(unsigned(bb));
 920                     -- Bits 5-8 of cr_op give the truth table of the requested
 921                     -- logical operation
 922                     cr_operands := cr_in(banum) & cr_in(bbnum);
 923                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 924                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 925                     for i in 0 to 31 loop
 926                         if i = btnum then
 927                             v.e.write_cr_data(i) := crresult;
 928                         else
 929                             v.e.write_cr_data(i) := cr_in(i);
 930                         end if;
 931                     end loop;
 932                 end if;
 933             when OP_MCRXRX =>
 934                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 935                 bf := insn_bf(e_in.insn);
 936                 crnum := to_integer(unsigned(bf));
 937                 v.e.write_cr_enable := '1';
 938                 v.e.write_cr_mask := num_to_fxm(crnum);
 939                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 940                                      newcrf & newcrf & newcrf & newcrf;
 941             when OP_DARN =>
 942             when OP_MFMSR =>
 943             when OP_MFSPR =>
 944                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 945                     "=" & to_hstring(a_in);
 946                 if is_fast_spr(e_in.read_reg1) = '1' then
 947                     spr_val := a_in;
 948                     if decode_spr_num(e_in.insn) = SPR_XER then
 949                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 950                         spr_val(63 downto 32) := (others => '0');
 951                         spr_val(63-32) := v.e.xerc.so;
 952                         spr_val(63-33) := v.e.xerc.ov;
 953                         spr_val(63-34) := v.e.xerc.ca;
 954                         spr_val(63-35 downto 63-43) := "000000000";
 955                         spr_val(63-44) := v.e.xerc.ov32;
 956                         spr_val(63-45) := v.e.xerc.ca32;
 957                     end if;
 958                 else
 959                     spr_val := c_in;
 960                     case decode_spr_num(e_in.insn) is
 961                     when SPR_TB =>
 962                         spr_val := ctrl.tb;
 963                     when SPR_TBU =>
 964                         spr_val(63 downto 32) := (others => '0');
 965                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 966                     when SPR_DEC =>
 967                         spr_val := ctrl.dec;
 968                     when SPR_CFAR =>
 969                         spr_val := ctrl.cfar;
 970                     when SPR_PVR =>
 971                         spr_val(63 downto 32) := (others => '0');
 972                         spr_val(31 downto 0) := PVR_MICROWATT;
 973                     when 724 =>     -- LOG_ADDR SPR
 974                         spr_val := log_wr_addr & r.log_addr_spr;
 975                     when 725 =>     -- LOG_DATA SPR
 976                         spr_val := log_rd_data;
 977                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 978                     when others =>
 979                         -- mfspr from unimplemented SPRs should be a nop in
 980                         -- supervisor mode and a program interrupt for user mode
 981                         if is_fast_spr(e_in.read_reg1) = '0' and ctrl.msr(MSR_PR) = '1' then
 982                             illegal := '1';
 983                         end if;
 984                     end case;
 985                 end if;
 986                 spr_result <= spr_val;
 987
 988             when OP_MFCR =>
 989             when OP_MTCRF =>
 990                 v.e.write_cr_enable := '1';
 991                 if e_in.insn(20) = '0' then
 992                     -- mtcrf
 993                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 994                 else
 995                     -- mtocrf: We require one hot priority encoding here
 996                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 997                     v.e.write_cr_mask := num_to_fxm(crnum);
 998                 end if;
 999                 v.e.write_cr_data := c_in(31 downto 0);
1000             when OP_MTMSRD =>
1001                 if e_in.insn(16) = '1' then
1002                     -- just update EE and RI
1003                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
1004                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
1005                 else
1006                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
1007                     -- and 63 (LE) (IBM bit numbering)
1008                     if e_in.is_32bit = '0' then
1009                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
1010                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
1011                     end if;
1012                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1013                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
1014                     if c_in(MSR_PR) = '1' then
1015                         ctrl_tmp.msr(MSR_EE) <= '1';
1016                         ctrl_tmp.msr(MSR_IR) <= '1';
1017                         ctrl_tmp.msr(MSR_DR) <= '1';
1018                     end if;
1019                     if HAS_FPU then
1020                         v.fp_exception_next := fp_in.exception and
1021                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
1022                     end if;
1023                 end if;
1024             when OP_MTSPR =>
1025                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1026                     "=" & to_hstring(c_in);
1027                 if is_fast_spr(e_in.write_reg) then
1028                     if decode_spr_num(e_in.insn) = SPR_XER then
1029                         v.e.xerc.so := c_in(63-32);
1030                         v.e.xerc.ov := c_in(63-33);
1031                         v.e.xerc.ca := c_in(63-34);
1032                         v.e.xerc.ov32 := c_in(63-44);
1033                         v.e.xerc.ca32 := c_in(63-45);
1034                         v.e.write_xerc_enable := '1';
1035                     end if;
1036                 else
1037                     -- slow spr
1038                     case decode_spr_num(e_in.insn) is
1039                     when SPR_DEC =>
1040                         ctrl_tmp.dec <= c_in;
1041                     when 724 =>     -- LOG_ADDR SPR
1042                         v.log_addr_spr := c_in(31 downto 0);
1043                     when others =>
1044                         -- mtspr to unimplemented SPRs should be a nop in
1045                         -- supervisor mode and a program interrupt for user mode
1046                         if ctrl.msr(MSR_PR) = '1' then
1047                             illegal := '1';
1048                         end if;
1049                     end case;
1050                 end if;
1051             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1052                 if e_in.output_carry = '1' then
1053                     set_carry(v.e, rotator_carry, rotator_carry);
1054                 end if;
1055             when OP_SETB =>
1056
1057             when OP_ISYNC =>
1058                 v.redirect := '1';
1059                 v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1060
1061             when OP_ICBI =>
1062                 icache_inval <= '1';
1063
1064             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1065                 v.e.valid := '0';
1066                 v.mul_in_progress := '1';
1067                 v.busy := '1';
1068                 x_to_multiply.valid <= '1';
1069
1070             when OP_DIV | OP_DIVE | OP_MOD =>
1071                 v.e.valid := '0';
1072                 v.div_in_progress := '1';
1073                 v.busy := '1';
1074                 x_to_divider.valid <= '1';
1075
1076             when others =>
1077                 v.terminate := '1';
1078                 report "illegal";
1079             end case;
1080
1081             -- Mispredicted branches cause a redirect
1082             if is_branch = '1' then
1083                 if taken_branch = '1' then
1084                     ctrl_tmp.cfar <= e_in.nia;
1085                 end if;
1086                 if e_in.br_pred = '0' then
1087                     v.br_offset := b_in;
1088                     v.abs_br := abs_branch;
1089                 else
1090                     v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1091                 end if;
1092                 if taken_branch /= e_in.br_pred then
1093                     v.redirect := '1';
1094                 end if;
1095             end if;
1096
1097         elsif valid_in = '1' and exception = '0' and illegal = '0' then
1098             -- instruction for other units, i.e. LDST
1099             if e_in.unit = LDST then
1100                 lv.valid := '1';
1101             elsif e_in.unit = NONE then
1102                 illegal := '1';
1103             elsif HAS_FPU and e_in.unit = FPU then
1104                 fv.valid := '1';
1105             end if;
1106             -- Handling an ITLB miss doesn't count as having executed an instruction
1107             if e_in.insn_type = OP_FETCH_FAILED then
1108                 do_trace := '0';
1109             end if;
1110         end if;
1111
1112         -- The following cases all occur when r.busy = 1 and therefore
1113         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1114         -- the cases above which depend on valid_in = 1.
1115
1116         if ctrl.irq_state = WRITE_SRR1 then
1117             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
1118             v.e.exc_write_data := ctrl.srr1;
1119             v.e.exc_write_enable := '1';
1120             ctrl_tmp.msr(MSR_SF) <= '1';
1121             ctrl_tmp.msr(MSR_EE) <= '0';
1122             ctrl_tmp.msr(MSR_PR) <= '0';
1123             ctrl_tmp.msr(MSR_SE) <= '0';
1124             ctrl_tmp.msr(MSR_BE) <= '0';
1125             ctrl_tmp.msr(MSR_FP) <= '0';
1126             ctrl_tmp.msr(MSR_FE0) <= '0';
1127             ctrl_tmp.msr(MSR_FE1) <= '0';
1128             ctrl_tmp.msr(MSR_IR) <= '0';
1129             ctrl_tmp.msr(MSR_DR) <= '0';
1130             ctrl_tmp.msr(MSR_RI) <= '0';
1131             ctrl_tmp.msr(MSR_LE) <= '1';
1132             v.trace_next := '0';
1133             v.fp_exception_next := '0';
1134             report "Writing SRR1: " & to_hstring(ctrl.srr1);
1135
1136         elsif r.cntz_in_progress = '1' then
1137             -- cnt[lt]z always takes two cycles
1138             v.e.valid := '1';
1139         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1140             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1141                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1142                 if r.mul_in_progress = '1' then
1143                     overflow := '0';
1144                 else
1145                     overflow := divider_to_x.overflow;
1146                 end if;
1147                 if r.mul_in_progress = '1' and current.oe = '1' then
1148                     -- have to wait until next cycle for overflow indication
1149                     v.mul_finish := '1';
1150                     v.busy := '1';
1151                 else
1152                     v.e.write_xerc_enable := current.oe;
1153                     -- We must test oe because the RC update code in writeback
1154                     -- will use the xerc value to set CR0:SO so we must not clobber
1155                     -- xerc if OE wasn't set.
1156                     if current.oe = '1' then
1157                         v.e.xerc.ov := overflow;
1158                         v.e.xerc.ov32 := overflow;
1159                         if overflow = '1' then
1160                             v.e.xerc.so := '1';
1161                         end if;
1162                     end if;
1163                     v.e.valid := '1';
1164                 end if;
1165             else
1166                 v.busy := '1';
1167                 v.mul_in_progress := r.mul_in_progress;
1168                 v.div_in_progress := r.div_in_progress;
1169             end if;
1170         elsif r.mul_finish = '1' then
1171             hold_wr_data := '1';
1172             v.e.write_xerc_enable := current.oe;
1173             v.e.xerc.ov := multiply_to_x.overflow;
1174             v.e.xerc.ov32 := multiply_to_x.overflow;
1175             if multiply_to_x.overflow = '1' then
1176                 v.e.xerc.so := '1';
1177             end if;
1178             v.e.valid := '1';
1179         end if;
1180         -- When doing delayed LR update, keep r.e.write_data unchanged
1181         -- next cycle in case it is needed for a forwarded result (e.g. CTR).
1182         if r.lr_update = '1' then
1183             hold_wr_data := '1';
1184         end if;
1185
1186         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1187         -- be set during the execution of a FP instruction.
1188         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1189         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1190         if HAS_FPU and fp_in.interrupt = '1' then
1191             v.vector := 16#700#;
1192             ctrl_tmp.srr1(63 - 43) <= '1';
1193             exception := '1';
1194         end if;
1195
1196         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1197             exception := '1';
1198             v.vector := 16#700#;
1199             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1200             -- set bit 44 to indicate we have an illegal
1201             ctrl_tmp.srr1(63 - 44) <= '1';
1202             report "illegal";
1203         end if;
1204         if exception = '1' then
1205             v.e.exc_write_enable := '1';
1206             if exception_nextpc = '1' then
1207                 v.e.exc_write_data := next_nia;
1208             end if;
1209         end if;
1210
1211         -- generate DSI or DSegI for load/store exceptions
1212         -- or ISI or ISegI for instruction fetch exceptions
1213         if l_in.exception = '1' then
1214             if l_in.alignment = '1' then
1215                 v.vector := 16#600#;
1216             elsif l_in.instr_fault = '0' then
1217                 if l_in.segment_fault = '0' then
1218                     v.vector := 16#300#;
1219                 else
1220                     v.vector := 16#380#;
1221                 end if;
1222             else
1223                 if l_in.segment_fault = '0' then
1224                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1225                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1226                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1227                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1228                     v.vector := 16#400#;
1229                 else
1230                     v.vector := 16#480#;
1231                 end if;
1232             end if;
1233             v.e.exc_write_enable := '1';
1234             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1235             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1236         end if;
1237
1238         if exception = '1' or l_in.exception = '1' then
1239             ctrl_tmp.irq_state <= WRITE_SRR1;
1240             v.redirect := '1';
1241             v.do_intr := '1';
1242         end if;
1243
1244         if do_trace = '1' then
1245             v.trace_next := '1';
1246         end if;
1247
1248         if hold_wr_data = '0' then
1249             v.e.write_data := alu_result;
1250         else
1251             v.e.write_data := r.e.write_data;
1252         end if;
1253         v.e.write_reg := current.write_reg;
1254         v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
1255         v.e.rc := current.rc and v.e.valid and not exception;
1256
1257         -- Update LR on the next cycle after a branch link
1258         -- If we're not writing back anything else, we can write back LR
1259         -- this cycle, otherwise we take an extra cycle.  We use the
1260         -- exc_write path since next_nia is written through that path
1261         -- in other places.
1262         if v.e.valid = '1' and exception = '0' and current.lr = '1' then
1263             if current.write_reg_enable = '0' then
1264                 v.e.exc_write_enable := '1';
1265                 v.e.exc_write_data := next_nia;
1266                 v.e.exc_write_reg := fast_spr_num(SPR_LR);
1267             else
1268                 v.lr_update := '1';
1269                 v.e.valid := '0';
1270                 report "Delayed LR update to " & to_hstring(next_nia);
1271                 v.busy := '1';
1272             end if;
1273         end if;
1274         if r.lr_update = '1' then
1275             v.e.exc_write_enable := '1';
1276             v.e.exc_write_data := r.next_lr;
1277             v.e.exc_write_reg := fast_spr_num(SPR_LR);
1278             v.e.valid := '1';
1279         end if;
1280
1281         -- Defer completion for one cycle when redirecting.
1282         -- This also ensures r.busy = 1 when ctrl.irq_state = WRITE_SRR1
1283         if v.redirect = '1' then
1284             v.busy := '1';
1285             v.e.valid := '0';
1286         end if;
1287         if r.redirect = '1' then
1288             v.e.valid := '1';
1289         end if;
1290
1291         -- Outputs to fetch1
1292         f.redirect := r.redirect;
1293         if r.do_intr = '1' then
1294             f.redirect_nia := std_ulogic_vector(to_unsigned(r.vector, 64));
1295             f.virt_mode := '0';
1296             f.priv_mode := '1';
1297             -- XXX need an interrupt LE bit here, e.g. from LPCR
1298             f.big_endian := '0';
1299             f.mode_32bit := '0';
1300         else
1301             if r.abs_br = '1' then
1302                 f.redirect_nia := r.br_offset;
1303             else
1304                 f.redirect_nia := std_ulogic_vector(unsigned(r.last_nia) + unsigned(r.br_offset));
1305             end if;
1306             -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
1307             f.virt_mode := r.redir_mode(3);
1308             f.priv_mode := r.redir_mode(2);
1309             f.big_endian := r.redir_mode(1);
1310             f.mode_32bit := r.redir_mode(0);
1311         end if;
1312
1313         -- Outputs to loadstore1 (async)
1314         lv.op := e_in.insn_type;
1315         lv.nia := e_in.nia;
1316         lv.addr1 := a_in;
1317         lv.addr2 := b_in;
1318         lv.data := c_in;
1319         lv.write_reg := e_in.write_reg;
1320         lv.length := e_in.data_len;
1321         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1322         lv.sign_extend := e_in.sign_extend;
1323         lv.update := e_in.update;
1324         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1325         lv.xerc := v.e.xerc;
1326         lv.reserve := e_in.reserve;
1327         lv.rc := e_in.rc;
1328         lv.insn := e_in.insn;
1329         -- decode l*cix and st*cix instructions here
1330         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1331             e_in.insn(5 downto 1) = "10101" then
1332             lv.ci := '1';
1333         end if;
1334         lv.virt_mode := ctrl.msr(MSR_DR);
1335         lv.priv_mode := not ctrl.msr(MSR_PR);
1336         lv.mode_32bit := not ctrl.msr(MSR_SF);
1337         lv.is_32bit := e_in.is_32bit;
1338         lv.repeat := e_in.repeat;
1339         lv.second := e_in.second;
1340
1341         -- Outputs to FPU
1342         fv.op := e_in.insn_type;
1343         fv.nia := e_in.nia;
1344         fv.insn := e_in.insn;
1345         fv.single := e_in.is_32bit;
1346         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1347         fv.fra := a_in;
1348         fv.frb := b_in;
1349         fv.frc := c_in;
1350         fv.frt := e_in.write_reg;
1351         fv.rc := e_in.rc;
1352         fv.out_cr := e_in.output_cr;
1353
1354         -- Update registers
1355         rin <= v;
1356
1357         -- update outputs
1358         f_out <= f;
1359         l_out <= lv;
1360         e_out <= r.e;
1361         fp_out <= fv;
1362         flush_out <= f_out.redirect;
1363
1364         exception_log <= exception;
1365         irq_valid_log <= irq_valid;
1366     end process;
1367
1368     e1_log: if LOG_LENGTH > 0 generate
1369         signal log_data : std_ulogic_vector(14 downto 0);
1370     begin
1371         ex1_log : process(clk)
1372         begin
1373             if rising_edge(clk) then
1374                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1375                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1376                             exception_log &
1377                             irq_valid_log &
1378                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1379                             "000" &
1380                             r.e.write_enable &
1381                             r.e.valid &
1382                             f_out.redirect &
1383                             r.busy &
1384                             flush_out;
1385             end if;
1386         end process;
1387         log_out <= log_data;
1388     end generate;
1389 end architecture behaviour;