execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40
  41         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  42
  43         icache_inval : out std_ulogic;
  44         terminate_out : out std_ulogic;
  45
  46         log_out : out std_ulogic_vector(14 downto 0);
  47         log_rd_addr : out std_ulogic_vector(31 downto 0);
  48         log_rd_data : in std_ulogic_vector(63 downto 0);
  49         log_wr_addr : in std_ulogic_vector(31 downto 0)
  50         );
  51 end entity execute1;
  52
  53 architecture behaviour of execute1 is
  54     type reg_type is record
  55         e : Execute1ToWritebackType;
  56         cur_instr : Decode2ToExecute1Type;
  57         busy: std_ulogic;
  58         terminate: std_ulogic;
  59         fp_exception_next : std_ulogic;
  60         trace_next : std_ulogic;
  61         prev_op : insn_type_t;
  62         next_lr : std_ulogic_vector(63 downto 0);
  63         br_taken : std_ulogic;
  64         mul_in_progress : std_ulogic;
  65         mul_finish : std_ulogic;
  66         div_in_progress : std_ulogic;
  67         cntz_in_progress : std_ulogic;
  68         last_nia : std_ulogic_vector(63 downto 0);
  69         redirect : std_ulogic;
  70         abs_br : std_ulogic;
  71         taken_br : std_ulogic;
  72         br_last : std_ulogic;
  73         do_intr : std_ulogic;
  74         vector : integer range 0 to 16#fff#;
  75         br_offset : std_ulogic_vector(63 downto 0);
  76         redir_mode : std_ulogic_vector(3 downto 0);
  77         log_addr_spr : std_ulogic_vector(31 downto 0);
  78     end record;
  79     constant reg_type_init : reg_type :=
  80         (e => Execute1ToWritebackInit,
  81          cur_instr => Decode2ToExecute1Init,
  82          busy => '0', terminate => '0',
  83          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL, br_taken => '0',
  84          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  85          next_lr => (others => '0'), last_nia => (others => '0'),
  86          redirect => '0', abs_br => '0', taken_br => '0', br_last => '0', do_intr => '0', vector => 0,
  87          br_offset => (others => '0'), redir_mode => "0000",
  88          others => (others => '0'));
  89
  90     signal r, rin : reg_type;
  91
  92     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  93     signal cr_in : std_ulogic_vector(31 downto 0);
  94
  95     signal valid_in : std_ulogic;
  96     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  97     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  98     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  99     signal rot_sign_ext: std_ulogic;
 100     signal rotator_result: std_ulogic_vector(63 downto 0);
 101     signal rotator_carry: std_ulogic;
 102     signal logical_result: std_ulogic_vector(63 downto 0);
 103     signal countzero_result: std_ulogic_vector(63 downto 0);
 104     signal alu_result: std_ulogic_vector(63 downto 0);
 105     signal adder_result: std_ulogic_vector(63 downto 0);
 106     signal misc_result: std_ulogic_vector(63 downto 0);
 107     signal muldiv_result: std_ulogic_vector(63 downto 0);
 108     signal spr_result: std_ulogic_vector(63 downto 0);
 109     signal result_mux_sel: std_ulogic_vector(2 downto 0);
 110     signal sub_mux_sel: std_ulogic_vector(2 downto 0);
 111     signal next_nia : std_ulogic_vector(63 downto 0);
 112     signal current: Decode2ToExecute1Type;
 113
 114     -- multiply signals
 115     signal x_to_multiply: MultiplyInputType;
 116     signal multiply_to_x: MultiplyOutputType;
 117
 118     -- divider signals
 119     signal x_to_divider: Execute1ToDividerType;
 120     signal divider_to_x: DividerToExecute1Type;
 121
 122     -- random number generator signals
 123     signal random_raw  : std_ulogic_vector(63 downto 0);
 124     signal random_cond : std_ulogic_vector(63 downto 0);
 125     signal random_err  : std_ulogic;
 126
 127     -- signals for logging
 128     signal exception_log : std_ulogic;
 129     signal irq_valid_log : std_ulogic;
 130
 131     type privilege_level is (USER, SUPER);
 132     type op_privilege_array is array(insn_type_t) of privilege_level;
 133     constant op_privilege: op_privilege_array := (
 134         OP_ATTN => SUPER,
 135         OP_MFMSR => SUPER,
 136         OP_MTMSRD => SUPER,
 137         OP_RFID => SUPER,
 138         OP_TLBIE => SUPER,
 139         others => USER
 140         );
 141
 142     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 143         return boolean is
 144     begin
 145         if op_privilege(op) = SUPER then
 146             return true;
 147         elsif op = OP_MFSPR or op = OP_MTSPR then
 148             return insn(20) = '1';
 149         else
 150             return false;
 151         end if;
 152     end;
 153
 154     procedure set_carry(e: inout Execute1ToWritebackType;
 155                         carry32 : in std_ulogic;
 156                         carry : in std_ulogic) is
 157     begin
 158         e.xerc.ca32 := carry32;
 159         e.xerc.ca := carry;
 160         e.write_xerc_enable := '1';
 161     end;
 162
 163     procedure set_ov(e: inout Execute1ToWritebackType;
 164                      ov   : in std_ulogic;
 165                      ov32 : in std_ulogic) is
 166     begin
 167         e.xerc.ov32 := ov32;
 168         e.xerc.ov := ov;
 169         if ov = '1' then
 170             e.xerc.so := '1';
 171         end if;
 172         e.write_xerc_enable := '1';
 173     end;
 174
 175     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 176                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 177     begin
 178         return (ca xor msb_r) and not (msb_a xor msb_b);
 179     end;
 180
 181     function decode_input_carry(ic : carry_in_t;
 182                                 xerc : xer_common_t) return std_ulogic is
 183     begin
 184         case ic is
 185         when ZERO =>
 186             return '0';
 187         when CA =>
 188             return xerc.ca;
 189         when OV =>
 190             return xerc.ov;
 191         when ONE =>
 192             return '1';
 193         end case;
 194     end;
 195
 196     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 197         return std_ulogic_vector is
 198         variable msr_out: std_ulogic_vector(63 downto 0);
 199     begin
 200         -- ISA says this:
 201         --  Defined MSR bits are classified as either full func-
 202         --  tion or partial function. Full function MSR bits are
 203         --  saved in SRR1 or HSRR1 when an interrupt other
 204         --  than a System Call Vectored interrupt occurs and
 205         --  restored by rfscv, rfid, or hrfid, while partial func-
 206         --  tion MSR bits are not saved or restored.
 207         --  Full function MSR bits lie in the range 0:32, 37:41, and
 208         --  48:63, and partial function MSR bits lie in the range
 209         --  33:36 and 42:47. (Note this is IBM bit numbering).
 210         msr_out := (others => '0');
 211         msr_out(63 downto 31) := msr(63 downto 31);
 212         msr_out(26 downto 22) := msr(26 downto 22);
 213         msr_out(15 downto 0)  := msr(15 downto 0);
 214         return msr_out;
 215     end;
 216
 217     -- Tell vivado to keep the hierarchy for the random module so that the
 218     -- net names in the xdc file match.
 219     attribute keep_hierarchy : string;
 220     attribute keep_hierarchy of random_0 : label is "yes";
 221
 222 begin
 223
 224     rotator_0: entity work.rotator
 225         port map (
 226             rs => c_in,
 227             ra => a_in,
 228             shift => b_in(6 downto 0),
 229             insn => e_in.insn,
 230             is_32bit => e_in.is_32bit,
 231             right_shift => right_shift,
 232             arith => e_in.is_signed,
 233             clear_left => rot_clear_left,
 234             clear_right => rot_clear_right,
 235             sign_ext_rs => rot_sign_ext,
 236             result => rotator_result,
 237             carry_out => rotator_carry
 238             );
 239
 240     logical_0: entity work.logical
 241         port map (
 242             rs => c_in,
 243             rb => b_in,
 244             op => e_in.insn_type,
 245             invert_in => e_in.invert_a,
 246             invert_out => e_in.invert_out,
 247             result => logical_result,
 248             datalen => e_in.data_len
 249             );
 250
 251     countzero_0: entity work.zero_counter
 252         port map (
 253             clk => clk,
 254             rs => c_in,
 255             count_right => e_in.insn(10),
 256             is_32bit => e_in.is_32bit,
 257             result => countzero_result
 258             );
 259
 260     multiply_0: entity work.multiply
 261         port map (
 262             clk => clk,
 263             m_in => x_to_multiply,
 264             m_out => multiply_to_x
 265             );
 266
 267     divider_0: entity work.divider
 268         port map (
 269             clk => clk,
 270             rst => rst,
 271             d_in => x_to_divider,
 272             d_out => divider_to_x
 273             );
 274
 275     random_0: entity work.random
 276         port map (
 277             clk => clk,
 278             data => random_cond,
 279             raw => random_raw,
 280             err => random_err
 281             );
 282
 283     dbg_msr_out <= ctrl.msr;
 284     log_rd_addr <= r.log_addr_spr;
 285
 286     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 287     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 288     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 289
 290     busy_out <= l_in.busy or r.busy or fp_in.busy;
 291     valid_in <= e_in.valid and not busy_out;
 292
 293     terminate_out <= r.terminate;
 294
 295     current <= e_in when r.busy = '0' else r.cur_instr;
 296
 297     -- Result mux
 298     with current.result_sel select alu_result <=
 299         adder_result       when "000",
 300         logical_result     when "001",
 301         rotator_result     when "010",
 302         muldiv_result      when "011",
 303         countzero_result   when "100",
 304         spr_result         when "101",
 305         next_nia           when "110",
 306         misc_result        when others;
 307
 308     execute1_0: process(clk)
 309     begin
 310         if rising_edge(clk) then
 311             if rst = '1' then
 312                 r <= reg_type_init;
 313                 ctrl.tb <= (others => '0');
 314                 ctrl.dec <= (others => '0');
 315                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 316                 ctrl.irq_state <= WRITE_SRR0;
 317             else
 318                 r <= rin;
 319                 ctrl <= ctrl_tmp;
 320                 if valid_in = '1' then
 321                     report "execute " & to_hstring(e_in.nia) & " op=" & insn_type_t'image(e_in.insn_type) &
 322                         " wr=" & to_hstring(rin.e.write_reg) & " we=" & std_ulogic'image(rin.e.write_enable) &
 323                         " tag=" & integer'image(rin.e.instr_tag.tag) & std_ulogic'image(rin.e.instr_tag.valid);
 324                 end if;
 325             end if;
 326         end if;
 327     end process;
 328
 329     execute1_1: process(all)
 330         variable v : reg_type;
 331         variable a_inv : std_ulogic_vector(63 downto 0);
 332         variable b_or_m1 : std_ulogic_vector(63 downto 0);
 333         variable addg6s : std_ulogic_vector(63 downto 0);
 334         variable isel_result : std_ulogic_vector(63 downto 0);
 335         variable darn : std_ulogic_vector(63 downto 0);
 336         variable mfcr_result : std_ulogic_vector(63 downto 0);
 337         variable setb_result : std_ulogic_vector(63 downto 0);
 338         variable newcrf : std_ulogic_vector(3 downto 0);
 339         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 340         variable crnum : crnum_t;
 341         variable crbit : integer range 0 to 31;
 342         variable scrnum : crnum_t;
 343         variable lo, hi : integer;
 344         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 345         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 346         variable bo, bi : std_ulogic_vector(4 downto 0);
 347         variable bf, bfa : std_ulogic_vector(2 downto 0);
 348         variable cr_op : std_ulogic_vector(9 downto 0);
 349         variable cr_operands : std_ulogic_vector(1 downto 0);
 350         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 351         variable btnum, banum, bbnum : integer range 0 to 31;
 352         variable crresult : std_ulogic;
 353         variable l : std_ulogic;
 354         variable carry_32, carry_64 : std_ulogic;
 355         variable sign1, sign2 : std_ulogic;
 356         variable abs1, abs2 : signed(63 downto 0);
 357         variable overflow : std_ulogic;
 358         variable zerohi, zerolo : std_ulogic;
 359         variable msb_a, msb_b : std_ulogic;
 360         variable a_lt : std_ulogic;
 361         variable a_lt_lo : std_ulogic;
 362         variable a_lt_hi : std_ulogic;
 363         variable lv : Execute1ToLoadstore1Type;
 364         variable irq_valid : std_ulogic;
 365         variable exception : std_ulogic;
 366         variable exception_nextpc : std_ulogic;
 367         variable trapval : std_ulogic_vector(4 downto 0);
 368         variable illegal : std_ulogic;
 369         variable is_branch : std_ulogic;
 370         variable is_direct_branch : std_ulogic;
 371         variable taken_branch : std_ulogic;
 372         variable abs_branch : std_ulogic;
 373         variable spr_val : std_ulogic_vector(63 downto 0);
 374         variable addend : std_ulogic_vector(127 downto 0);
 375         variable do_trace : std_ulogic;
 376         variable hold_wr_data : std_ulogic;
 377         variable f : Execute1ToFetch1Type;
 378         variable fv : Execute1ToFPUType;
 379     begin
 380         sum_with_carry := (others => '0');
 381         newcrf := (others => '0');
 382         is_branch := '0';
 383         is_direct_branch := '0';
 384         taken_branch := '0';
 385         abs_branch := '0';
 386         hold_wr_data := '0';
 387
 388         v := r;
 389         v.e := Execute1ToWritebackInit;
 390         v.redirect := '0';
 391         v.abs_br := '0';
 392         v.do_intr := '0';
 393         v.vector := 0;
 394         v.br_offset := (others => '0');
 395         v.redir_mode := ctrl.msr(MSR_IR) & not ctrl.msr(MSR_PR) &
 396                         not ctrl.msr(MSR_LE) & not ctrl.msr(MSR_SF);
 397         v.taken_br := '0';
 398         v.br_last := '0';
 399
 400         lv := Execute1ToLoadstore1Init;
 401         fv := Execute1ToFPUInit;
 402
 403         -- XER forwarding. To avoid having to track XER hazards, we use
 404         -- the previously latched value.  Since the XER common bits
 405         -- (SO, OV[32] and CA[32]) are only modified by instructions that are
 406         -- handled here, we can just forward the result being sent to
 407         -- writeback.
 408         if r.e.write_xerc_enable = '1' or r.busy = '1' then
 409             v.e.xerc := r.e.xerc;
 410         else
 411             v.e.xerc := e_in.xerc;
 412         end if;
 413
 414         -- CR forwarding
 415         cr_in <= e_in.cr;
 416         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 417             for i in 0 to 7 loop
 418                 if r.e.write_cr_mask(i) = '1' then
 419                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 420                 end if;
 421             end loop;
 422         end if;
 423
 424         v.mul_in_progress := '0';
 425         v.div_in_progress := '0';
 426         v.cntz_in_progress := '0';
 427         v.mul_finish := '0';
 428
 429         spr_result <= (others => '0');
 430         spr_val := (others => '0');
 431
 432         -- Main adder
 433         if e_in.invert_a = '0' then
 434             a_inv := a_in;
 435         else
 436             a_inv := not a_in;
 437         end if;
 438         if e_in.addm1 = '0' then
 439             b_or_m1 := b_in;
 440         else
 441             b_or_m1 := (others => '1');
 442         end if;
 443         sum_with_carry := ppc_adde(a_inv, b_or_m1,
 444                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 445         adder_result <= sum_with_carry(63 downto 0);
 446         carry_32 := sum_with_carry(32) xor a_inv(32) xor b_in(32);
 447         carry_64 := sum_with_carry(64);
 448
 449         -- signals to multiply and divide units
 450         sign1 := '0';
 451         sign2 := '0';
 452         if e_in.is_signed = '1' then
 453             if e_in.is_32bit = '1' then
 454                 sign1 := a_in(31);
 455                 sign2 := b_in(31);
 456             else
 457                 sign1 := a_in(63);
 458                 sign2 := b_in(63);
 459             end if;
 460         end if;
 461         -- take absolute values
 462         if sign1 = '0' then
 463             abs1 := signed(a_in);
 464         else
 465             abs1 := - signed(a_in);
 466         end if;
 467         if sign2 = '0' then
 468             abs2 := signed(b_in);
 469         else
 470             abs2 := - signed(b_in);
 471         end if;
 472
 473         -- Interface to multiply and divide units
 474         x_to_multiply <= MultiplyInputInit;
 475         x_to_multiply.is_32bit <= e_in.is_32bit;
 476
 477         x_to_divider <= Execute1ToDividerInit;
 478         x_to_divider.is_signed <= e_in.is_signed;
 479         x_to_divider.is_32bit <= e_in.is_32bit;
 480         if e_in.insn_type = OP_MOD then
 481             x_to_divider.is_modulus <= '1';
 482         end if;
 483
 484         addend := (others => '0');
 485         if e_in.insn(26) = '0' then
 486             -- integer multiply-add, major op 4 (if it is a multiply)
 487             addend(63 downto 0) := c_in;
 488             if e_in.is_signed = '1' then
 489                 addend(127 downto 64) := (others => c_in(63));
 490             end if;
 491         end if;
 492         if (sign1 xor sign2) = '1' then
 493             addend := not addend;
 494         end if;
 495
 496         x_to_multiply.not_result <= sign1 xor sign2;
 497         x_to_multiply.addend <= addend;
 498         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 499         if e_in.is_32bit = '0' then
 500             -- 64-bit forms
 501             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 502             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 503             if e_in.insn_type = OP_DIVE then
 504                 x_to_divider.is_extended <= '1';
 505             end if;
 506             x_to_divider.dividend <= std_ulogic_vector(abs1);
 507             x_to_divider.divisor <= std_ulogic_vector(abs2);
 508         else
 509             -- 32-bit forms
 510             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 511             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 512             x_to_divider.is_extended <= '0';
 513             if e_in.insn_type = OP_DIVE then   -- extended forms
 514                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 515             else
 516                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 517             end if;
 518             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 519         end if;
 520
 521         case current.sub_select(1 downto 0) is
 522             when "00" =>
 523                 muldiv_result <= multiply_to_x.result(63 downto 0);
 524             when "01" =>
 525                 muldiv_result <= multiply_to_x.result(127 downto 64);
 526             when "10" =>
 527                 muldiv_result <= multiply_to_x.result(63 downto 32) &
 528                                  multiply_to_x.result(63 downto 32);
 529             when others =>
 530                 muldiv_result <= divider_to_x.write_reg_data;
 531         end case;
 532
 533         -- Compute misc_result
 534         case current.sub_select is
 535             when "000" =>
 536                 misc_result <= (others => '0');
 537             when "001" =>
 538                 -- addg6s
 539                 addg6s := (others => '0');
 540                 for i in 0 to 14 loop
 541                     lo := i * 4;
 542                     hi := (i + 1) * 4;
 543                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 544                         addg6s(lo + 3 downto lo) := "0110";
 545                     end if;
 546                 end loop;
 547                 if sum_with_carry(64) = '0' then
 548                     addg6s(63 downto 60) := "0110";
 549                 end if;
 550                 misc_result <= addg6s;
 551             when "010" =>
 552                 -- isel
 553                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 554                 if cr_in(31-crbit) = '1' then
 555                     isel_result := a_in;
 556                 else
 557                     isel_result := b_in;
 558                 end if;
 559                 misc_result <= isel_result;
 560             when "011" =>
 561                 -- darn
 562                 darn := (others => '1');
 563                 if random_err = '0' then
 564                     case e_in.insn(17 downto 16) is
 565                         when "00" =>
 566                             darn := x"00000000" & random_cond(31 downto 0);
 567                         when "10" =>
 568                             darn := random_raw;
 569                         when others =>
 570                             darn := random_cond;
 571                     end case;
 572                 end if;
 573                 misc_result <= darn;
 574             when "100" =>
 575                 -- mfmsr
 576                 misc_result <= ctrl.msr;
 577             when "101" =>
 578                 if e_in.insn(20) = '0' then
 579                     -- mfcr
 580                     mfcr_result := x"00000000" & cr_in;
 581                 else
 582                     -- mfocrf
 583                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 584                     mfcr_result := (others => '0');
 585                     for i in 0 to 7 loop
 586                         lo := (7-i)*4;
 587                         hi := lo + 3;
 588                         if crnum = i then
 589                             mfcr_result(hi downto lo) := cr_in(hi downto lo);
 590                         end if;
 591                     end loop;
 592                 end if;
 593                 misc_result <= mfcr_result;
 594             when "110" =>
 595                 -- setb
 596                 bfa := insn_bfa(e_in.insn);
 597                 crbit := to_integer(unsigned(bfa)) * 4;
 598                 setb_result := (others => '0');
 599                 if cr_in(31 - crbit) = '1' then
 600                     setb_result := (others => '1');
 601                 elsif cr_in(30 - crbit) = '1' then
 602                     setb_result(0) := '1';
 603                 end if;
 604                 misc_result <= setb_result;
 605             when others =>
 606                 misc_result <= (others => '0');
 607         end case;
 608
 609         -- compute comparison results
 610         -- Note, we have done RB - RA, not RA - RB
 611         if e_in.insn_type = OP_CMP then
 612             l := insn_l(e_in.insn);
 613         else
 614             l := not e_in.is_32bit;
 615         end if;
 616         zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 617         zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 618         if zerolo = '1' and (l = '0' or zerohi = '1') then
 619             -- values are equal
 620             trapval := "00100";
 621         else
 622             a_lt_lo := '0';
 623             a_lt_hi := '0';
 624             if unsigned(a_in(30 downto 0)) < unsigned(b_in(30 downto 0)) then
 625                 a_lt_lo := '1';
 626             end if;
 627             if unsigned(a_in(62 downto 31)) < unsigned(b_in(62 downto 31)) then
 628                 a_lt_hi := '1';
 629             end if;
 630             if l = '1' then
 631                 -- 64-bit comparison
 632                 msb_a := a_in(63);
 633                 msb_b := b_in(63);
 634                 a_lt := a_lt_hi or (zerohi and (a_in(31) xnor b_in(31)) and a_lt_lo);
 635             else
 636                 -- 32-bit comparison
 637                 msb_a := a_in(31);
 638                 msb_b := b_in(31);
 639                 a_lt := a_lt_lo;
 640             end if;
 641             if msb_a /= msb_b then
 642                 -- Comparison is clear from MSB difference.
 643                 -- for signed, 0 is greater; for unsigned, 1 is greater
 644                 trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 645             else
 646                 -- MSBs are equal, so signed and unsigned comparisons give the
 647                 -- same answer.
 648                 trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 649             end if;
 650         end if;
 651
 652         ctrl_tmp <= ctrl;
 653         -- FIXME: run at 512MHz not core freq
 654         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 655         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 656
 657         irq_valid := '0';
 658         if ctrl.msr(MSR_EE) = '1' then
 659             if ctrl.dec(63) = '1' then
 660                 v.vector := 16#900#;
 661                 report "IRQ valid: DEC";
 662                 irq_valid := '1';
 663             elsif ext_irq_in = '1' then
 664                 v.vector := 16#500#;
 665                 report "IRQ valid: External";
 666                 irq_valid := '1';
 667             end if;
 668         end if;
 669
 670         v.terminate := '0';
 671         icache_inval <= '0';
 672         v.busy := '0';
 673
 674         -- Next insn adder used in a couple of places
 675         next_nia <= std_ulogic_vector(unsigned(e_in.nia) + 4);
 676
 677         -- rotator control signals
 678         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 679         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 680         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 681         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 682
 683         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 684         ctrl_tmp.irq_state <= WRITE_SRR0;
 685         exception := '0';
 686         illegal := '0';
 687         exception_nextpc := '0';
 688         v.e.exc_write_enable := '0';
 689         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 690         if valid_in = '1' then
 691             v.e.exc_write_data := e_in.nia;
 692             v.last_nia := e_in.nia;
 693         else
 694             v.e.exc_write_data := r.last_nia;
 695         end if;
 696
 697         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 698         v.e.instr_tag := current.instr_tag;
 699
 700         do_trace := valid_in and ctrl.msr(MSR_SE);
 701         if valid_in = '1' then
 702             v.prev_op := e_in.insn_type;
 703         end if;
 704
 705         -- Determine if there is any exception to be taken
 706         -- before/instead of executing this instruction
 707         if valid_in = '1' and e_in.second = '0' then
 708             if HAS_FPU and r.fp_exception_next = '1' then
 709                 -- This is used for FP-type program interrupts that
 710                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 711                 exception := '1';
 712                 v.vector := 16#700#;
 713                 ctrl_tmp.srr1(63 - 43) <= '1';
 714                 ctrl_tmp.srr1(63 - 47) <= '1';
 715             elsif r.trace_next = '1' then
 716                 -- Generate a trace interrupt rather than executing the next instruction
 717                 -- or taking any asynchronous interrupt
 718                 exception := '1';
 719                 v.vector := 16#d00#;
 720                 ctrl_tmp.srr1(63 - 33) <= '1';
 721                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 722                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 723                     ctrl_tmp.srr1(63 - 35) <= '1';
 724                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 725                     ctrl_tmp.srr1(63 - 36) <= '1';
 726                 end if;
 727
 728             elsif irq_valid = '1' then
 729                 -- Don't deliver the interrupt until we have a valid instruction
 730                 -- coming in, so we have a valid NIA to put in SRR0.
 731                 exception := '1';
 732
 733             elsif ctrl.msr(MSR_PR) = '1' and instr_is_privileged(e_in.insn_type, e_in.insn) then
 734                 -- generate a program interrupt
 735                 exception := '1';
 736                 v.vector := 16#700#;
 737                 -- set bit 45 to indicate privileged instruction type interrupt
 738                 ctrl_tmp.srr1(63 - 45) <= '1';
 739                 report "privileged instruction";
 740
 741             elsif not HAS_FPU and e_in.fac = FPU then
 742                 -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 743                 illegal := '1';
 744
 745             elsif HAS_FPU and ctrl.msr(MSR_FP) = '0' and e_in.fac = FPU then
 746                 -- generate a floating-point unavailable interrupt
 747                 exception := '1';
 748                 v.vector := 16#800#;
 749                 report "FP unavailable interrupt";
 750             end if;
 751         end if;
 752
 753         if valid_in = '1' and exception = '0' and illegal = '0' and e_in.unit = ALU then
 754             v.cur_instr := e_in;
 755             v.next_lr := next_nia;
 756             v.e.valid := '1';
 757
 758             case_0: case e_in.insn_type is
 759
 760             when OP_ILLEGAL =>
 761                 -- we need two cycles to write srr0 and 1
 762                 -- will need more when we have to write HEIR
 763                 illegal := '1';
 764             when OP_SC =>
 765                 -- check bit 1 of the instruction is 1 so we know this is sc;
 766                 -- 0 would mean scv, so generate an illegal instruction interrupt
 767                 -- we need two cycles to write srr0 and 1
 768                 if e_in.insn(1) = '1' then
 769                     exception := '1';
 770                     exception_nextpc := '1';
 771                     v.vector := 16#C00#;
 772                     report "sc";
 773                 else
 774                     illegal := '1';
 775                 end if;
 776             when OP_ATTN =>
 777                 -- check bits 1-10 of the instruction to make sure it's attn
 778                 -- if not then it is illegal
 779                 if e_in.insn(10 downto 1) = "0100000000" then
 780                     v.terminate := '1';
 781                     report "ATTN";
 782                 else
 783                     illegal := '1';
 784                 end if;
 785             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 786                 -- Do nothing
 787             when OP_ADD =>
 788                 if e_in.output_carry = '1' then
 789                     if e_in.input_carry /= OV then
 790                         set_carry(v.e, carry_32, carry_64);
 791                     else
 792                         v.e.xerc.ov := carry_64;
 793                         v.e.xerc.ov32 := carry_32;
 794                         v.e.write_xerc_enable := '1';
 795                     end if;
 796                 end if;
 797                 if e_in.oe = '1' then
 798                     set_ov(v.e,
 799                            calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 800                            calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 801                 end if;
 802             when OP_CMP =>
 803                 -- CMP and CMPL instructions
 804                 if e_in.is_signed = '1' then
 805                     newcrf := trapval(4 downto 2) & v.e.xerc.so;
 806                 else
 807                     newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 808                 end if;
 809                 bf := insn_bf(e_in.insn);
 810                 crnum := to_integer(unsigned(bf));
 811                 v.e.write_cr_enable := '1';
 812                 v.e.write_cr_mask := num_to_fxm(crnum);
 813                 for i in 0 to 7 loop
 814                     lo := i*4;
 815                     hi := lo + 3;
 816                     v.e.write_cr_data(hi downto lo) := newcrf;
 817                 end loop;
 818             when OP_TRAP =>
 819                 -- trap instructions (tw, twi, td, tdi)
 820                 v.vector := 16#700#;
 821                 -- set bit 46 to say trap occurred
 822                 ctrl_tmp.srr1(63 - 46) <= '1';
 823                 if or (trapval and insn_to(e_in.insn)) = '1' then
 824                     -- generate trap-type program interrupt
 825                     exception := '1';
 826                     report "trap";
 827                 end if;
 828             when OP_ADDG6S =>
 829             when OP_CMPRB =>
 830                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 831                 bf := insn_bf(e_in.insn);
 832                 crnum := to_integer(unsigned(bf));
 833                 v.e.write_cr_enable := '1';
 834                 v.e.write_cr_mask := num_to_fxm(crnum);
 835                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 836                                      newcrf & newcrf & newcrf & newcrf;
 837             when OP_CMPEQB =>
 838                 newcrf := ppc_cmpeqb(a_in, b_in);
 839                 bf := insn_bf(e_in.insn);
 840                 crnum := to_integer(unsigned(bf));
 841                 v.e.write_cr_enable := '1';
 842                 v.e.write_cr_mask := num_to_fxm(crnum);
 843                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 844                                      newcrf & newcrf & newcrf & newcrf;
 845             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 846                     OP_BPERM | OP_BCD =>
 847
 848             when OP_B =>
 849                 is_branch := '1';
 850                 taken_branch := '1';
 851                 is_direct_branch := '1';
 852                 abs_branch := e_in.br_abs;
 853                 if ctrl.msr(MSR_BE) = '1' then
 854                     do_trace := '1';
 855                 end if;
 856             when OP_BC | OP_BCREG =>
 857                 -- read_data1 is CTR
 858                 -- for OP_BCREG, read_data2 is target register (CTR, LR or TAR)
 859                 -- If this instruction updates both CTR and LR, then it is
 860                 -- doubled; the first instruction decrements CTR and determines
 861                 -- whether the branch is taken, and the second does the
 862                 -- redirect and the LR update.
 863                 bo := insn_bo(e_in.insn);
 864                 bi := insn_bi(e_in.insn);
 865                 if e_in.second = '0' then
 866                     taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 867                 else
 868                     taken_branch := r.br_taken;
 869                 end if;
 870                 v.br_taken := taken_branch;
 871                 abs_branch := e_in.br_abs;
 872                 if e_in.repeat = '0' or e_in.second = '1' then
 873                     is_branch := '1';
 874                     if e_in.insn_type = OP_BC then
 875                         is_direct_branch := '1';
 876                     end if;
 877                     if ctrl.msr(MSR_BE) = '1' then
 878                         do_trace := '1';
 879                     end if;
 880                 end if;
 881
 882             when OP_RFID =>
 883                 v.redir_mode := (a_in(MSR_IR) or a_in(MSR_PR)) & not a_in(MSR_PR) &
 884                                 not a_in(MSR_LE) & not a_in(MSR_SF);
 885                 -- Can't use msr_copy here because the partial function MSR
 886                 -- bits should be left unchanged, not zeroed.
 887                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 888                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 889                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 890                 if a_in(MSR_PR) = '1' then
 891                     ctrl_tmp.msr(MSR_EE) <= '1';
 892                     ctrl_tmp.msr(MSR_IR) <= '1';
 893                     ctrl_tmp.msr(MSR_DR) <= '1';
 894                 end if;
 895                 -- mark this as a branch so CFAR gets updated
 896                 is_branch := '1';
 897                 taken_branch := '1';
 898                 abs_branch := '1';
 899                 if HAS_FPU then
 900                     v.fp_exception_next := fp_in.exception and
 901                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 902                 end if;
 903                 do_trace := '0';
 904
 905             when OP_CNTZ =>
 906                 v.e.valid := '0';
 907                 v.cntz_in_progress := '1';
 908                 v.busy := '1';
 909             when OP_ISEL =>
 910             when OP_CROP =>
 911                 cr_op := insn_cr(e_in.insn);
 912                 if cr_op(0) = '0' then -- MCRF
 913                     bf := insn_bf(e_in.insn);
 914                     bfa := insn_bfa(e_in.insn);
 915                     v.e.write_cr_enable := '1';
 916                     crnum := to_integer(unsigned(bf));
 917                     scrnum := to_integer(unsigned(bfa));
 918                     v.e.write_cr_mask := num_to_fxm(crnum);
 919                     for i in 0 to 7 loop
 920                         lo := (7-i)*4;
 921                         hi := lo + 3;
 922                         if i = scrnum then
 923                             newcrf := cr_in(hi downto lo);
 924                         end if;
 925                     end loop;
 926                     for i in 0 to 7 loop
 927                         lo := i*4;
 928                         hi := lo + 3;
 929                         v.e.write_cr_data(hi downto lo) := newcrf;
 930                     end loop;
 931                 else
 932                     v.e.write_cr_enable := '1';
 933                     bt := insn_bt(e_in.insn);
 934                     ba := insn_ba(e_in.insn);
 935                     bb := insn_bb(e_in.insn);
 936                     btnum := 31 - to_integer(unsigned(bt));
 937                     banum := 31 - to_integer(unsigned(ba));
 938                     bbnum := 31 - to_integer(unsigned(bb));
 939                     -- Bits 5-8 of cr_op give the truth table of the requested
 940                     -- logical operation
 941                     cr_operands := cr_in(banum) & cr_in(bbnum);
 942                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 943                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 944                     for i in 0 to 31 loop
 945                         if i = btnum then
 946                             v.e.write_cr_data(i) := crresult;
 947                         else
 948                             v.e.write_cr_data(i) := cr_in(i);
 949                         end if;
 950                     end loop;
 951                 end if;
 952             when OP_MCRXRX =>
 953                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 954                 bf := insn_bf(e_in.insn);
 955                 crnum := to_integer(unsigned(bf));
 956                 v.e.write_cr_enable := '1';
 957                 v.e.write_cr_mask := num_to_fxm(crnum);
 958                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 959                                      newcrf & newcrf & newcrf & newcrf;
 960             when OP_DARN =>
 961             when OP_MFMSR =>
 962             when OP_MFSPR =>
 963                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 964                     "=" & to_hstring(a_in);
 965                 if is_fast_spr(e_in.read_reg1) = '1' then
 966                     spr_val := a_in;
 967                     if decode_spr_num(e_in.insn) = SPR_XER then
 968                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 969                         spr_val(63 downto 32) := (others => '0');
 970                         spr_val(63-32) := v.e.xerc.so;
 971                         spr_val(63-33) := v.e.xerc.ov;
 972                         spr_val(63-34) := v.e.xerc.ca;
 973                         spr_val(63-35 downto 63-43) := "000000000";
 974                         spr_val(63-44) := v.e.xerc.ov32;
 975                         spr_val(63-45) := v.e.xerc.ca32;
 976                     end if;
 977                 else
 978                     spr_val := c_in;
 979                     case decode_spr_num(e_in.insn) is
 980                     when SPR_TB =>
 981                         spr_val := ctrl.tb;
 982                     when SPR_TBU =>
 983                         spr_val(63 downto 32) := (others => '0');
 984                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 985                     when SPR_DEC =>
 986                         spr_val := ctrl.dec;
 987                     when SPR_CFAR =>
 988                         spr_val := ctrl.cfar;
 989                     when SPR_PVR =>
 990                         spr_val(63 downto 32) := (others => '0');
 991                         spr_val(31 downto 0) := PVR_MICROWATT;
 992                     when 724 =>     -- LOG_ADDR SPR
 993                         spr_val := log_wr_addr & r.log_addr_spr;
 994                     when 725 =>     -- LOG_DATA SPR
 995                         spr_val := log_rd_data;
 996                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 997                     when others =>
 998                         -- mfspr from unimplemented SPRs should be a nop in
 999                         -- supervisor mode and a program interrupt for user mode
1000                         if is_fast_spr(e_in.read_reg1) = '0' and ctrl.msr(MSR_PR) = '1' then
1001                             illegal := '1';
1002                         end if;
1003                     end case;
1004                 end if;
1005                 spr_result <= spr_val;
1006
1007             when OP_MFCR =>
1008             when OP_MTCRF =>
1009                 v.e.write_cr_enable := '1';
1010                 if e_in.insn(20) = '0' then
1011                     -- mtcrf
1012                     v.e.write_cr_mask := insn_fxm(e_in.insn);
1013                 else
1014                     -- mtocrf: We require one hot priority encoding here
1015                     crnum := fxm_to_num(insn_fxm(e_in.insn));
1016                     v.e.write_cr_mask := num_to_fxm(crnum);
1017                 end if;
1018                 v.e.write_cr_data := c_in(31 downto 0);
1019             when OP_MTMSRD =>
1020                 if e_in.insn(16) = '1' then
1021                     -- just update EE and RI
1022                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
1023                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
1024                 else
1025                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
1026                     -- and 63 (LE) (IBM bit numbering)
1027                     if e_in.is_32bit = '0' then
1028                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
1029                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
1030                     end if;
1031                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1032                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
1033                     if c_in(MSR_PR) = '1' then
1034                         ctrl_tmp.msr(MSR_EE) <= '1';
1035                         ctrl_tmp.msr(MSR_IR) <= '1';
1036                         ctrl_tmp.msr(MSR_DR) <= '1';
1037                     end if;
1038                     if HAS_FPU then
1039                         v.fp_exception_next := fp_in.exception and
1040                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
1041                     end if;
1042                 end if;
1043             when OP_MTSPR =>
1044                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1045                     "=" & to_hstring(c_in);
1046                 if is_fast_spr(e_in.write_reg) then
1047                     if decode_spr_num(e_in.insn) = SPR_XER then
1048                         v.e.xerc.so := c_in(63-32);
1049                         v.e.xerc.ov := c_in(63-33);
1050                         v.e.xerc.ca := c_in(63-34);
1051                         v.e.xerc.ov32 := c_in(63-44);
1052                         v.e.xerc.ca32 := c_in(63-45);
1053                         v.e.write_xerc_enable := '1';
1054                     end if;
1055                 else
1056                     -- slow spr
1057                     case decode_spr_num(e_in.insn) is
1058                     when SPR_DEC =>
1059                         ctrl_tmp.dec <= c_in;
1060                     when 724 =>     -- LOG_ADDR SPR
1061                         v.log_addr_spr := c_in(31 downto 0);
1062                     when others =>
1063                         -- mtspr to unimplemented SPRs should be a nop in
1064                         -- supervisor mode and a program interrupt for user mode
1065                         if ctrl.msr(MSR_PR) = '1' then
1066                             illegal := '1';
1067                         end if;
1068                     end case;
1069                 end if;
1070             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1071                 if e_in.output_carry = '1' then
1072                     set_carry(v.e, rotator_carry, rotator_carry);
1073                 end if;
1074             when OP_SETB =>
1075
1076             when OP_ISYNC =>
1077                 v.redirect := '1';
1078                 v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1079
1080             when OP_ICBI =>
1081                 icache_inval <= '1';
1082
1083             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1084                 v.e.valid := '0';
1085                 v.mul_in_progress := '1';
1086                 v.busy := '1';
1087                 x_to_multiply.valid <= '1';
1088
1089             when OP_DIV | OP_DIVE | OP_MOD =>
1090                 v.e.valid := '0';
1091                 v.div_in_progress := '1';
1092                 v.busy := '1';
1093                 x_to_divider.valid <= '1';
1094
1095             when others =>
1096                 v.terminate := '1';
1097                 report "illegal";
1098             end case;
1099
1100             -- Mispredicted branches cause a redirect
1101             if is_branch = '1' then
1102                 if taken_branch = '1' then
1103                     ctrl_tmp.cfar <= e_in.nia;
1104                 end if;
1105                 if taken_branch = '1' then
1106                     v.br_offset := b_in;
1107                     v.abs_br := abs_branch;
1108                 else
1109                     v.br_offset := std_ulogic_vector(to_unsigned(4, 64));
1110                 end if;
1111                 if taken_branch /= e_in.br_pred then
1112                     v.redirect := '1';
1113                 end if;
1114                 v.br_last := is_direct_branch;
1115                 v.taken_br := taken_branch;
1116             end if;
1117
1118         elsif valid_in = '1' and exception = '0' and illegal = '0' then
1119             -- instruction for other units, i.e. LDST
1120             if e_in.unit = LDST then
1121                 lv.valid := '1';
1122             elsif e_in.unit = NONE then
1123                 illegal := '1';
1124             elsif HAS_FPU and e_in.unit = FPU then
1125                 fv.valid := '1';
1126             end if;
1127             -- Handling an ITLB miss doesn't count as having executed an instruction
1128             if e_in.insn_type = OP_FETCH_FAILED then
1129                 do_trace := '0';
1130             end if;
1131         end if;
1132
1133         -- The following cases all occur when r.busy = 1 and therefore
1134         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1135         -- the cases above which depend on valid_in = 1.
1136
1137         if ctrl.irq_state = WRITE_SRR1 then
1138             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
1139             v.e.exc_write_data := ctrl.srr1;
1140             v.e.exc_write_enable := '1';
1141             ctrl_tmp.msr(MSR_SF) <= '1';
1142             ctrl_tmp.msr(MSR_EE) <= '0';
1143             ctrl_tmp.msr(MSR_PR) <= '0';
1144             ctrl_tmp.msr(MSR_SE) <= '0';
1145             ctrl_tmp.msr(MSR_BE) <= '0';
1146             ctrl_tmp.msr(MSR_FP) <= '0';
1147             ctrl_tmp.msr(MSR_FE0) <= '0';
1148             ctrl_tmp.msr(MSR_FE1) <= '0';
1149             ctrl_tmp.msr(MSR_IR) <= '0';
1150             ctrl_tmp.msr(MSR_DR) <= '0';
1151             ctrl_tmp.msr(MSR_RI) <= '0';
1152             ctrl_tmp.msr(MSR_LE) <= '1';
1153             v.trace_next := '0';
1154             v.fp_exception_next := '0';
1155             report "Writing SRR1: " & to_hstring(ctrl.srr1);
1156
1157         elsif r.cntz_in_progress = '1' then
1158             -- cnt[lt]z always takes two cycles
1159             v.e.valid := '1';
1160         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1161             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1162                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1163                 if r.mul_in_progress = '1' then
1164                     overflow := '0';
1165                 else
1166                     overflow := divider_to_x.overflow;
1167                 end if;
1168                 if r.mul_in_progress = '1' and current.oe = '1' then
1169                     -- have to wait until next cycle for overflow indication
1170                     v.mul_finish := '1';
1171                     v.busy := '1';
1172                 else
1173                     v.e.write_xerc_enable := current.oe;
1174                     -- We must test oe because the RC update code in writeback
1175                     -- will use the xerc value to set CR0:SO so we must not clobber
1176                     -- xerc if OE wasn't set.
1177                     if current.oe = '1' then
1178                         v.e.xerc.ov := overflow;
1179                         v.e.xerc.ov32 := overflow;
1180                         if overflow = '1' then
1181                             v.e.xerc.so := '1';
1182                         end if;
1183                     end if;
1184                     v.e.valid := '1';
1185                 end if;
1186             else
1187                 v.busy := '1';
1188                 v.mul_in_progress := r.mul_in_progress;
1189                 v.div_in_progress := r.div_in_progress;
1190             end if;
1191         elsif r.mul_finish = '1' then
1192             hold_wr_data := '1';
1193             v.e.write_xerc_enable := current.oe;
1194             v.e.xerc.ov := multiply_to_x.overflow;
1195             v.e.xerc.ov32 := multiply_to_x.overflow;
1196             if multiply_to_x.overflow = '1' then
1197                 v.e.xerc.so := '1';
1198             end if;
1199             v.e.valid := '1';
1200         end if;
1201
1202         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1203         -- be set during the execution of a FP instruction.
1204         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1205         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1206         if HAS_FPU and fp_in.interrupt = '1' then
1207             v.vector := 16#700#;
1208             ctrl_tmp.srr1(63 - 43) <= '1';
1209             exception := '1';
1210         end if;
1211
1212         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1213             exception := '1';
1214             v.vector := 16#700#;
1215             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1216             -- set bit 44 to indicate we have an illegal
1217             ctrl_tmp.srr1(63 - 44) <= '1';
1218             report "illegal";
1219         end if;
1220         if exception = '1' then
1221             v.e.exc_write_enable := '1';
1222             if exception_nextpc = '1' then
1223                 v.e.exc_write_data := next_nia;
1224             end if;
1225         end if;
1226
1227         -- generate DSI or DSegI for load/store exceptions
1228         -- or ISI or ISegI for instruction fetch exceptions
1229         if l_in.exception = '1' then
1230             if l_in.alignment = '1' then
1231                 v.vector := 16#600#;
1232             elsif l_in.instr_fault = '0' then
1233                 if l_in.segment_fault = '0' then
1234                     v.vector := 16#300#;
1235                 else
1236                     v.vector := 16#380#;
1237                 end if;
1238             else
1239                 if l_in.segment_fault = '0' then
1240                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1241                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1242                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1243                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1244                     v.vector := 16#400#;
1245                 else
1246                     v.vector := 16#480#;
1247                 end if;
1248             end if;
1249             v.e.exc_write_enable := '1';
1250             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1251             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1252         end if;
1253
1254         if exception = '1' or l_in.exception = '1' then
1255             ctrl_tmp.irq_state <= WRITE_SRR1;
1256             v.redirect := '1';
1257             v.do_intr := '1';
1258         end if;
1259
1260         if do_trace = '1' then
1261             v.trace_next := '1';
1262         end if;
1263
1264         if hold_wr_data = '0' then
1265             v.e.write_data := alu_result;
1266         else
1267             v.e.write_data := r.e.write_data;
1268         end if;
1269         v.e.write_reg := current.write_reg;
1270         v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
1271         v.e.rc := current.rc and v.e.valid and not exception;
1272
1273         -- Defer completion for one cycle when redirecting.
1274         -- This also ensures r.busy = 1 when ctrl.irq_state = WRITE_SRR1
1275         if v.redirect = '1' then
1276             v.busy := '1';
1277             v.e.valid := '0';
1278         end if;
1279         if r.redirect = '1' then
1280             v.e.valid := '1';
1281         end if;
1282
1283         -- Outputs to fetch1
1284         f.redirect := r.redirect;
1285         f.br_nia := r.last_nia;
1286         f.br_last := r.br_last and not r.do_intr;
1287         f.br_taken := r.taken_br;
1288         if r.do_intr = '1' then
1289             f.redirect_nia := std_ulogic_vector(to_unsigned(r.vector, 64));
1290             f.virt_mode := '0';
1291             f.priv_mode := '1';
1292             -- XXX need an interrupt LE bit here, e.g. from LPCR
1293             f.big_endian := '0';
1294             f.mode_32bit := '0';
1295         else
1296             if r.abs_br = '1' then
1297                 f.redirect_nia := r.br_offset;
1298             else
1299                 f.redirect_nia := std_ulogic_vector(unsigned(r.last_nia) + unsigned(r.br_offset));
1300             end if;
1301             -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
1302             f.virt_mode := r.redir_mode(3);
1303             f.priv_mode := r.redir_mode(2);
1304             f.big_endian := r.redir_mode(1);
1305             f.mode_32bit := r.redir_mode(0);
1306         end if;
1307
1308         -- Outputs to loadstore1 (async)
1309         lv.op := e_in.insn_type;
1310         lv.nia := e_in.nia;
1311         lv.instr_tag := e_in.instr_tag;
1312         lv.addr1 := a_in;
1313         lv.addr2 := b_in;
1314         lv.data := c_in;
1315         lv.write_reg := e_in.write_reg;
1316         lv.length := e_in.data_len;
1317         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1318         lv.sign_extend := e_in.sign_extend;
1319         lv.update := e_in.update;
1320         lv.xerc := v.e.xerc;
1321         lv.reserve := e_in.reserve;
1322         lv.rc := e_in.rc;
1323         lv.insn := e_in.insn;
1324         -- decode l*cix and st*cix instructions here
1325         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1326             e_in.insn(5 downto 1) = "10101" then
1327             lv.ci := '1';
1328         end if;
1329         lv.virt_mode := ctrl.msr(MSR_DR);
1330         lv.priv_mode := not ctrl.msr(MSR_PR);
1331         lv.mode_32bit := not ctrl.msr(MSR_SF);
1332         lv.is_32bit := e_in.is_32bit;
1333         lv.repeat := e_in.repeat;
1334         lv.second := e_in.second;
1335
1336         -- Outputs to FPU
1337         fv.op := e_in.insn_type;
1338         fv.nia := e_in.nia;
1339         fv.insn := e_in.insn;
1340         fv.itag := e_in.instr_tag;
1341         fv.single := e_in.is_32bit;
1342         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1343         fv.fra := a_in;
1344         fv.frb := b_in;
1345         fv.frc := c_in;
1346         fv.frt := e_in.write_reg;
1347         fv.rc := e_in.rc;
1348         fv.out_cr := e_in.output_cr;
1349
1350         -- Update registers
1351         rin <= v;
1352
1353         -- update outputs
1354         f_out <= f;
1355         l_out <= lv;
1356         e_out <= r.e;
1357         fp_out <= fv;
1358         flush_out <= f_out.redirect;
1359
1360         exception_log <= exception;
1361         irq_valid_log <= irq_valid;
1362     end process;
1363
1364     e1_log: if LOG_LENGTH > 0 generate
1365         signal log_data : std_ulogic_vector(14 downto 0);
1366     begin
1367         ex1_log : process(clk)
1368         begin
1369             if rising_edge(clk) then
1370                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1371                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1372                             exception_log &
1373                             irq_valid_log &
1374                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1375                             "000" &
1376                             r.e.write_enable &
1377                             r.e.valid &
1378                             f_out.redirect &
1379                             r.busy &
1380                             flush_out;
1381             end if;
1382         end process;
1383         log_out <= log_data;
1384     end generate;
1385 end architecture behaviour;