execute1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7 use work.common.all;
   8 use work.helpers.all;
   9 use work.crhelpers.all;
  10 use work.insn_helpers.all;
  11 use work.ppc_fx_insns.all;
  12
  13 entity execute1 is
  14     generic (
  15         EX1_BYPASS : boolean := true;
  16         HAS_FPU : boolean := true;
  17         -- Non-zero to enable log data collection
  18         LOG_LENGTH : natural := 0
  19         );
  20     port (
  21         clk   : in std_ulogic;
  22         rst   : in std_ulogic;
  23
  24         -- asynchronous
  25         flush_out : out std_ulogic;
  26         busy_out : out std_ulogic;
  27
  28         e_in  : in Decode2ToExecute1Type;
  29         l_in  : in Loadstore1ToExecute1Type;
  30         fp_in : in FPUToExecute1Type;
  31
  32         ext_irq_in : std_ulogic;
  33
  34         -- asynchronous
  35         l_out : out Execute1ToLoadstore1Type;
  36         f_out : out Execute1ToFetch1Type;
  37         fp_out : out Execute1ToFPUType;
  38
  39         e_out : out Execute1ToWritebackType;
  40
  41         dbg_msr_out : out std_ulogic_vector(63 downto 0);
  42
  43         icache_inval : out std_ulogic;
  44         terminate_out : out std_ulogic;
  45
  46         log_out : out std_ulogic_vector(14 downto 0);
  47         log_rd_addr : out std_ulogic_vector(31 downto 0);
  48         log_rd_data : in std_ulogic_vector(63 downto 0);
  49         log_wr_addr : in std_ulogic_vector(31 downto 0)
  50         );
  51 end entity execute1;
  52
  53 architecture behaviour of execute1 is
  54     type reg_type is record
  55         e : Execute1ToWritebackType;
  56         f : Execute1ToFetch1Type;
  57         busy: std_ulogic;
  58         terminate: std_ulogic;
  59         fp_exception_next : std_ulogic;
  60         trace_next : std_ulogic;
  61         prev_op : insn_type_t;
  62         lr_update : std_ulogic;
  63         next_lr : std_ulogic_vector(63 downto 0);
  64         mul_in_progress : std_ulogic;
  65         mul_finish : std_ulogic;
  66         div_in_progress : std_ulogic;
  67         cntz_in_progress : std_ulogic;
  68         slow_op_insn : insn_type_t;
  69         slow_op_dest : gpr_index_t;
  70         slow_op_rc : std_ulogic;
  71         slow_op_oe : std_ulogic;
  72         slow_op_xerc : xer_common_t;
  73         last_nia : std_ulogic_vector(63 downto 0);
  74         log_addr_spr : std_ulogic_vector(31 downto 0);
  75     end record;
  76     constant reg_type_init : reg_type :=
  77         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
  78          busy => '0', lr_update => '0', terminate => '0',
  79          fp_exception_next => '0', trace_next => '0', prev_op => OP_ILLEGAL,
  80          mul_in_progress => '0', mul_finish => '0', div_in_progress => '0', cntz_in_progress => '0',
  81          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
  82          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
  83
  84     signal r, rin : reg_type;
  85
  86     signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
  87     signal cr_in : std_ulogic_vector(31 downto 0);
  88
  89     signal valid_in : std_ulogic;
  90     signal ctrl: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  91     signal ctrl_tmp: ctrl_t := (irq_state => WRITE_SRR0, others => (others => '0'));
  92     signal right_shift, rot_clear_left, rot_clear_right: std_ulogic;
  93     signal rot_sign_ext: std_ulogic;
  94     signal rotator_result: std_ulogic_vector(63 downto 0);
  95     signal rotator_carry: std_ulogic;
  96     signal logical_result: std_ulogic_vector(63 downto 0);
  97     signal countzero_result: std_ulogic_vector(63 downto 0);
  98
  99     -- multiply signals
 100     signal x_to_multiply: MultiplyInputType;
 101     signal multiply_to_x: MultiplyOutputType;
 102
 103     -- divider signals
 104     signal x_to_divider: Execute1ToDividerType;
 105     signal divider_to_x: DividerToExecute1Type;
 106
 107     -- random number generator signals
 108     signal random_raw  : std_ulogic_vector(63 downto 0);
 109     signal random_cond : std_ulogic_vector(63 downto 0);
 110     signal random_err  : std_ulogic;
 111
 112     -- signals for logging
 113     signal exception_log : std_ulogic;
 114     signal irq_valid_log : std_ulogic;
 115
 116     type privilege_level is (USER, SUPER);
 117     type op_privilege_array is array(insn_type_t) of privilege_level;
 118     constant op_privilege: op_privilege_array := (
 119         OP_ATTN => SUPER,
 120         OP_MFMSR => SUPER,
 121         OP_MTMSRD => SUPER,
 122         OP_RFID => SUPER,
 123         OP_TLBIE => SUPER,
 124         others => USER
 125         );
 126
 127     function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
 128         return boolean is
 129     begin
 130         if op_privilege(op) = SUPER then
 131             return true;
 132         elsif op = OP_MFSPR or op = OP_MTSPR then
 133             return insn(20) = '1';
 134         else
 135             return false;
 136         end if;
 137     end;
 138
 139     procedure set_carry(e: inout Execute1ToWritebackType;
 140                         carry32 : in std_ulogic;
 141                         carry : in std_ulogic) is
 142     begin
 143         e.xerc.ca32 := carry32;
 144         e.xerc.ca := carry;
 145         e.write_xerc_enable := '1';
 146     end;
 147
 148     procedure set_ov(e: inout Execute1ToWritebackType;
 149                      ov   : in std_ulogic;
 150                      ov32 : in std_ulogic) is
 151     begin
 152         e.xerc.ov32 := ov32;
 153         e.xerc.ov := ov;
 154         if ov = '1' then
 155             e.xerc.so := '1';
 156         end if;
 157         e.write_xerc_enable := '1';
 158     end;
 159
 160     function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
 161                      ca: std_ulogic; msb_r: std_ulogic) return std_ulogic is
 162     begin
 163         return (ca xor msb_r) and not (msb_a xor msb_b);
 164     end;
 165
 166     function decode_input_carry(ic : carry_in_t;
 167                                 xerc : xer_common_t) return std_ulogic is
 168     begin
 169         case ic is
 170         when ZERO =>
 171             return '0';
 172         when CA =>
 173             return xerc.ca;
 174         when OV =>
 175             return xerc.ov;
 176         when ONE =>
 177             return '1';
 178         end case;
 179     end;
 180
 181     function msr_copy(msr: std_ulogic_vector(63 downto 0))
 182         return std_ulogic_vector is
 183         variable msr_out: std_ulogic_vector(63 downto 0);
 184     begin
 185         -- ISA says this:
 186         --  Defined MSR bits are classified as either full func-
 187         --  tion or partial function. Full function MSR bits are
 188         --  saved in SRR1 or HSRR1 when an interrupt other
 189         --  than a System Call Vectored interrupt occurs and
 190         --  restored by rfscv, rfid, or hrfid, while partial func-
 191         --  tion MSR bits are not saved or restored.
 192         --  Full function MSR bits lie in the range 0:32, 37:41, and
 193         --  48:63, and partial function MSR bits lie in the range
 194         --  33:36 and 42:47. (Note this is IBM bit numbering).
 195         msr_out := (others => '0');
 196         msr_out(63 downto 31) := msr(63 downto 31);
 197         msr_out(26 downto 22) := msr(26 downto 22);
 198         msr_out(15 downto 0)  := msr(15 downto 0);
 199         return msr_out;
 200     end;
 201
 202     -- Tell vivado to keep the hierarchy for the random module so that the
 203     -- net names in the xdc file match.
 204     attribute keep_hierarchy : string;
 205     attribute keep_hierarchy of random_0 : label is "yes";
 206
 207 begin
 208
 209     rotator_0: entity work.rotator
 210         port map (
 211             rs => c_in,
 212             ra => a_in,
 213             shift => b_in(6 downto 0),
 214             insn => e_in.insn,
 215             is_32bit => e_in.is_32bit,
 216             right_shift => right_shift,
 217             arith => e_in.is_signed,
 218             clear_left => rot_clear_left,
 219             clear_right => rot_clear_right,
 220             sign_ext_rs => rot_sign_ext,
 221             result => rotator_result,
 222             carry_out => rotator_carry
 223             );
 224
 225     logical_0: entity work.logical
 226         port map (
 227             rs => c_in,
 228             rb => b_in,
 229             op => e_in.insn_type,
 230             invert_in => e_in.invert_a,
 231             invert_out => e_in.invert_out,
 232             result => logical_result,
 233             datalen => e_in.data_len
 234             );
 235
 236     countzero_0: entity work.zero_counter
 237         port map (
 238             clk => clk,
 239             rs => c_in,
 240             count_right => e_in.insn(10),
 241             is_32bit => e_in.is_32bit,
 242             result => countzero_result
 243             );
 244
 245     multiply_0: entity work.multiply
 246         port map (
 247             clk => clk,
 248             m_in => x_to_multiply,
 249             m_out => multiply_to_x
 250             );
 251
 252     divider_0: entity work.divider
 253         port map (
 254             clk => clk,
 255             rst => rst,
 256             d_in => x_to_divider,
 257             d_out => divider_to_x
 258             );
 259
 260     random_0: entity work.random
 261         port map (
 262             clk => clk,
 263             data => random_cond,
 264             raw => random_raw,
 265             err => random_err
 266             );
 267
 268     dbg_msr_out <= ctrl.msr;
 269     log_rd_addr <= r.log_addr_spr;
 270
 271     a_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data1 = '1' else e_in.read_data1;
 272     b_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data2 = '1' else e_in.read_data2;
 273     c_in <= r.e.write_data when EX1_BYPASS and e_in.bypass_data3 = '1' else e_in.read_data3;
 274
 275     busy_out <= l_in.busy or r.busy or fp_in.busy;
 276     valid_in <= e_in.valid and not busy_out;
 277
 278     terminate_out <= r.terminate;
 279
 280     execute1_0: process(clk)
 281     begin
 282         if rising_edge(clk) then
 283             if rst = '1' then
 284                 r <= reg_type_init;
 285                 ctrl.tb <= (others => '0');
 286                 ctrl.dec <= (others => '0');
 287                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
 288                 ctrl.irq_state <= WRITE_SRR0;
 289             else
 290                 r <= rin;
 291                 ctrl <= ctrl_tmp;
 292                 assert not (r.lr_update = '1' and valid_in = '1')
 293                     report "LR update collision with valid in EX1"
 294                     severity failure;
 295                 if r.lr_update = '1' then
 296                     report "LR update to " & to_hstring(r.next_lr);
 297                 end if;
 298             end if;
 299         end if;
 300     end process;
 301
 302     execute1_1: process(all)
 303         variable v : reg_type;
 304         variable a_inv : std_ulogic_vector(63 downto 0);
 305         variable result : std_ulogic_vector(63 downto 0);
 306         variable newcrf : std_ulogic_vector(3 downto 0);
 307         variable sum_with_carry : std_ulogic_vector(64 downto 0);
 308         variable result_en : std_ulogic;
 309         variable crnum : crnum_t;
 310         variable crbit : integer range 0 to 31;
 311         variable scrnum : crnum_t;
 312         variable lo, hi : integer;
 313         variable sh, mb, me : std_ulogic_vector(5 downto 0);
 314         variable sh32, mb32, me32 : std_ulogic_vector(4 downto 0);
 315         variable bo, bi : std_ulogic_vector(4 downto 0);
 316         variable bf, bfa : std_ulogic_vector(2 downto 0);
 317         variable cr_op : std_ulogic_vector(9 downto 0);
 318         variable cr_operands : std_ulogic_vector(1 downto 0);
 319         variable bt, ba, bb : std_ulogic_vector(4 downto 0);
 320         variable btnum, banum, bbnum : integer range 0 to 31;
 321         variable crresult : std_ulogic;
 322         variable l : std_ulogic;
 323         variable next_nia : std_ulogic_vector(63 downto 0);
 324         variable carry_32, carry_64 : std_ulogic;
 325         variable sign1, sign2 : std_ulogic;
 326         variable abs1, abs2 : signed(63 downto 0);
 327         variable overflow : std_ulogic;
 328         variable zerohi, zerolo : std_ulogic;
 329         variable msb_a, msb_b : std_ulogic;
 330         variable a_lt : std_ulogic;
 331         variable lv : Execute1ToLoadstore1Type;
 332         variable irq_valid : std_ulogic;
 333         variable exception : std_ulogic;
 334         variable exception_nextpc : std_ulogic;
 335         variable trapval : std_ulogic_vector(4 downto 0);
 336         variable illegal : std_ulogic;
 337         variable is_branch : std_ulogic;
 338         variable taken_branch : std_ulogic;
 339         variable abs_branch : std_ulogic;
 340         variable spr_val : std_ulogic_vector(63 downto 0);
 341         variable addend : std_ulogic_vector(127 downto 0);
 342         variable do_trace : std_ulogic;
 343         variable fv : Execute1ToFPUType;
 344     begin
 345         result := (others => '0');
 346         sum_with_carry := (others => '0');
 347         result_en := '0';
 348         newcrf := (others => '0');
 349         is_branch := '0';
 350         taken_branch := '0';
 351         abs_branch := '0';
 352
 353         v := r;
 354         v.e := Execute1ToWritebackInit;
 355         lv := Execute1ToLoadstore1Init;
 356         v.f.redirect := '0';
 357         fv := Execute1ToFPUInit;
 358
 359         -- XER forwarding. To avoid having to track XER hazards, we
 360         -- use the previously latched value.
 361         --
 362         -- If the XER was modified by a multiply or a divide, those are
 363         -- single issue, we'll get the up to date value from decode2 from
 364         -- the register file.
 365         --
 366         -- If it was modified by an instruction older than the previous
 367         -- one in EX1, it will have also hit writeback and will be up
 368         -- to date in decode2.
 369         --
 370         -- That leaves us with the case where it was updated by the previous
 371         -- instruction in EX1. In that case, we can forward it back here.
 372         --
 373         -- This will break if we allow pipelining of multiply and divide,
 374         -- but ideally, those should go via EX1 anyway and run as a state
 375         -- machine from here.
 376         --
 377         -- One additional hazard to beware of is an XER:SO modifying instruction
 378         -- in EX1 followed immediately by a store conditional. Due to our
 379         -- writeback latency, the store will go down the LSU with the previous
 380         -- XER value, thus the stcx. will set CR0:SO using an obsolete SO value.
 381         --
 382         -- We will need to handle that if we ever make stcx. not single issue
 383         --
 384         -- We always pass a valid XER value downto writeback even when
 385         -- we aren't updating it, in order for XER:SO -> CR0:SO transfer
 386         -- to work for RC instructions.
 387         --
 388         if r.e.write_xerc_enable = '1' then
 389             v.e.xerc := r.e.xerc;
 390         else
 391             v.e.xerc := e_in.xerc;
 392         end if;
 393
 394         -- CR forwarding
 395         cr_in <= e_in.cr;
 396         if EX1_BYPASS and e_in.bypass_cr = '1' and r.e.write_cr_enable = '1' then
 397             for i in 0 to 7 loop
 398                 if r.e.write_cr_mask(i) = '1' then
 399                     cr_in(i * 4 + 3 downto i * 4) <= r.e.write_cr_data(i * 4 + 3 downto i * 4);
 400                 end if;
 401             end loop;
 402         end if;
 403
 404         v.lr_update := '0';
 405         v.mul_in_progress := '0';
 406         v.div_in_progress := '0';
 407         v.cntz_in_progress := '0';
 408         v.mul_finish := '0';
 409
 410         -- Main adder
 411         if e_in.invert_a = '0' then
 412             a_inv := a_in;
 413         else
 414             a_inv := not a_in;
 415         end if;
 416         sum_with_carry := ppc_adde(a_inv, b_in,
 417                                    decode_input_carry(e_in.input_carry, v.e.xerc));
 418
 419         -- signals to multiply and divide units
 420         sign1 := '0';
 421         sign2 := '0';
 422         if e_in.is_signed = '1' then
 423             if e_in.is_32bit = '1' then
 424                 sign1 := a_in(31);
 425                 sign2 := b_in(31);
 426             else
 427                 sign1 := a_in(63);
 428                 sign2 := b_in(63);
 429             end if;
 430         end if;
 431         -- take absolute values
 432         if sign1 = '0' then
 433             abs1 := signed(a_in);
 434         else
 435             abs1 := - signed(a_in);
 436         end if;
 437         if sign2 = '0' then
 438             abs2 := signed(b_in);
 439         else
 440             abs2 := - signed(b_in);
 441         end if;
 442
 443         x_to_multiply <= MultiplyInputInit;
 444         x_to_multiply.is_32bit <= e_in.is_32bit;
 445
 446         x_to_divider <= Execute1ToDividerInit;
 447         x_to_divider.is_signed <= e_in.is_signed;
 448         x_to_divider.is_32bit <= e_in.is_32bit;
 449         if e_in.insn_type = OP_MOD then
 450             x_to_divider.is_modulus <= '1';
 451         end if;
 452
 453         addend := (others => '0');
 454         if e_in.insn(26) = '0' then
 455             -- integer multiply-add, major op 4 (if it is a multiply)
 456             addend(63 downto 0) := c_in;
 457             if e_in.is_signed = '1' then
 458                 addend(127 downto 64) := (others => c_in(63));
 459             end if;
 460         end if;
 461         if (sign1 xor sign2) = '1' then
 462             addend := not addend;
 463         end if;
 464
 465         x_to_multiply.not_result <= sign1 xor sign2;
 466         x_to_multiply.addend <= addend;
 467         x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
 468         if e_in.is_32bit = '0' then
 469             -- 64-bit forms
 470             x_to_multiply.data1 <= std_ulogic_vector(abs1);
 471             x_to_multiply.data2 <= std_ulogic_vector(abs2);
 472             if e_in.insn_type = OP_DIVE then
 473                 x_to_divider.is_extended <= '1';
 474             end if;
 475             x_to_divider.dividend <= std_ulogic_vector(abs1);
 476             x_to_divider.divisor <= std_ulogic_vector(abs2);
 477         else
 478             -- 32-bit forms
 479             x_to_multiply.data1 <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 480             x_to_multiply.data2 <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 481             x_to_divider.is_extended <= '0';
 482             if e_in.insn_type = OP_DIVE then   -- extended forms
 483                 x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
 484             else
 485                 x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
 486             end if;
 487             x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
 488         end if;
 489
 490         ctrl_tmp <= ctrl;
 491         -- FIXME: run at 512MHz not core freq
 492         ctrl_tmp.tb <= std_ulogic_vector(unsigned(ctrl.tb) + 1);
 493         ctrl_tmp.dec <= std_ulogic_vector(unsigned(ctrl.dec) - 1);
 494
 495         irq_valid := '0';
 496         if ctrl.msr(MSR_EE) = '1' then
 497             if ctrl.dec(63) = '1' then
 498                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#900#, 64));
 499                 report "IRQ valid: DEC";
 500                 irq_valid := '1';
 501             elsif ext_irq_in = '1' then
 502                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#500#, 64));
 503                 report "IRQ valid: External";
 504                 irq_valid := '1';
 505             end if;
 506         end if;
 507
 508         v.terminate := '0';
 509         icache_inval <= '0';
 510         v.busy := '0';
 511         -- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
 512         v.f.virt_mode := ctrl.msr(MSR_IR);
 513         v.f.priv_mode := not ctrl.msr(MSR_PR);
 514         v.f.big_endian := not ctrl.msr(MSR_LE);
 515         v.f.mode_32bit := not ctrl.msr(MSR_SF);
 516
 517         -- Next insn adder used in a couple of places
 518         next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
 519
 520         -- rotator control signals
 521         right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
 522         rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCL else '0';
 523         rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type = OP_RLCR else '0';
 524         rot_sign_ext <= '1' when e_in.insn_type = OP_EXTSWSLI else '0';
 525
 526         ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 527         ctrl_tmp.irq_state <= WRITE_SRR0;
 528         exception := '0';
 529         illegal := '0';
 530         exception_nextpc := '0';
 531         v.e.exc_write_enable := '0';
 532         v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
 533         if valid_in = '1' then
 534             v.e.exc_write_data := e_in.nia;
 535             v.last_nia := e_in.nia;
 536         else
 537             v.e.exc_write_data := r.last_nia;
 538         end if;
 539
 540         v.e.mode_32bit := not ctrl.msr(MSR_SF);
 541
 542         do_trace := valid_in and ctrl.msr(MSR_SE);
 543         if valid_in = '1' then
 544             v.prev_op := e_in.insn_type;
 545         end if;
 546
 547         if ctrl.irq_state = WRITE_SRR1 then
 548             v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
 549             v.e.exc_write_data := ctrl.srr1;
 550             v.e.exc_write_enable := '1';
 551             ctrl_tmp.msr(MSR_SF) <= '1';
 552             ctrl_tmp.msr(MSR_EE) <= '0';
 553             ctrl_tmp.msr(MSR_PR) <= '0';
 554             ctrl_tmp.msr(MSR_SE) <= '0';
 555             ctrl_tmp.msr(MSR_BE) <= '0';
 556             ctrl_tmp.msr(MSR_FP) <= '0';
 557             ctrl_tmp.msr(MSR_FE0) <= '0';
 558             ctrl_tmp.msr(MSR_FE1) <= '0';
 559             ctrl_tmp.msr(MSR_IR) <= '0';
 560             ctrl_tmp.msr(MSR_DR) <= '0';
 561             ctrl_tmp.msr(MSR_RI) <= '0';
 562             ctrl_tmp.msr(MSR_LE) <= '1';
 563             v.e.valid := '1';
 564             v.trace_next := '0';
 565             v.fp_exception_next := '0';
 566             report "Writing SRR1: " & to_hstring(ctrl.srr1);
 567
 568         elsif valid_in = '1' and ((HAS_FPU and r.fp_exception_next = '1') or r.trace_next = '1') then
 569             if HAS_FPU and r.fp_exception_next = '1' then
 570                 -- This is used for FP-type program interrupts that
 571                 -- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
 572                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 573                 ctrl_tmp.srr1(63 - 43) <= '1';
 574                 ctrl_tmp.srr1(63 - 47) <= '1';
 575             else
 576                 -- Generate a trace interrupt rather than executing the next instruction
 577                 -- or taking any asynchronous interrupt
 578                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#d00#, 64));
 579                 ctrl_tmp.srr1(63 - 33) <= '1';
 580                 if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
 581                     r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
 582                     ctrl_tmp.srr1(63 - 35) <= '1';
 583                 elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
 584                     ctrl_tmp.srr1(63 - 36) <= '1';
 585                 end if;
 586             end if;
 587             exception := '1';
 588
 589         elsif irq_valid = '1' and valid_in = '1' then
 590             -- we need two cycles to write srr0 and 1
 591             -- will need more when we have to write HEIR
 592             -- Don't deliver the interrupt until we have a valid instruction
 593             -- coming in, so we have a valid NIA to put in SRR0.
 594             exception := '1';
 595
 596         elsif valid_in = '1' and ctrl.msr(MSR_PR) = '1' and
 597             instr_is_privileged(e_in.insn_type, e_in.insn) then
 598             -- generate a program interrupt
 599             exception := '1';
 600             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 601             -- set bit 45 to indicate privileged instruction type interrupt
 602             ctrl_tmp.srr1(63 - 45) <= '1';
 603             report "privileged instruction";
 604
 605         elsif not HAS_FPU and valid_in = '1' and
 606             (e_in.insn_type = OP_FPLOAD or e_in.insn_type = OP_FPSTORE) then
 607             -- make lfd/stfd/lfs/stfs etc. illegal in no-FPU implementations
 608             illegal := '1';
 609
 610         elsif HAS_FPU and valid_in = '1' and ctrl.msr(MSR_FP) = '0' and
 611             (e_in.unit = FPU or e_in.insn_type = OP_FPLOAD or e_in.insn_type = OP_FPSTORE) then
 612             -- generate a floating-point unavailable interrupt
 613             exception := '1';
 614             v.f.redirect_nia := std_logic_vector(to_unsigned(16#800#, 64));
 615             report "FP unavailable interrupt";
 616
 617         elsif valid_in = '1' and e_in.unit = ALU then
 618
 619             report "execute nia " & to_hstring(e_in.nia);
 620
 621             v.e.valid := '1';
 622             v.e.write_reg := e_in.write_reg;
 623             v.slow_op_insn := e_in.insn_type;
 624             v.slow_op_dest := gspr_to_gpr(e_in.write_reg);
 625             v.slow_op_rc := e_in.rc;
 626             v.slow_op_oe := e_in.oe;
 627             v.slow_op_xerc := v.e.xerc;
 628
 629             case_0: case e_in.insn_type is
 630
 631             when OP_ILLEGAL =>
 632                 -- we need two cycles to write srr0 and 1
 633                 -- will need more when we have to write HEIR
 634                 illegal := '1';
 635             when OP_SC =>
 636                 -- check bit 1 of the instruction is 1 so we know this is sc;
 637                 -- 0 would mean scv, so generate an illegal instruction interrupt
 638                 -- we need two cycles to write srr0 and 1
 639                 if e_in.insn(1) = '1' then
 640                     exception := '1';
 641                     exception_nextpc := '1';
 642                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#C00#, 64));
 643                     report "sc";
 644                 else
 645                     illegal := '1';
 646                 end if;
 647             when OP_ATTN =>
 648                 -- check bits 1-10 of the instruction to make sure it's attn
 649                 -- if not then it is illegal
 650                 if e_in.insn(10 downto 1) = "0100000000" then
 651                     v.terminate := '1';
 652                     report "ATTN";
 653                 else
 654                     illegal := '1';
 655                 end if;
 656             when OP_NOP | OP_DCBF | OP_DCBST | OP_DCBT | OP_DCBTST | OP_ICBT =>
 657                 -- Do nothing
 658             when OP_ADD | OP_CMP | OP_TRAP =>
 659                 result := sum_with_carry(63 downto 0);
 660                 carry_32 := result(32) xor a_inv(32) xor b_in(32);
 661                 carry_64 := sum_with_carry(64);
 662                 if e_in.insn_type = OP_ADD then
 663                     if e_in.output_carry = '1' then
 664                         if e_in.input_carry /= OV then
 665                             set_carry(v.e, carry_32, carry_64);
 666                         else
 667                             v.e.xerc.ov := carry_64;
 668                             v.e.xerc.ov32 := carry_32;
 669                             v.e.write_xerc_enable := '1';
 670                         end if;
 671                     end if;
 672                     if e_in.oe = '1' then
 673                         set_ov(v.e,
 674                                calc_ov(a_inv(63), b_in(63), carry_64, sum_with_carry(63)),
 675                                calc_ov(a_inv(31), b_in(31), carry_32, sum_with_carry(31)));
 676                     end if;
 677                     result_en := '1';
 678                 else
 679                     -- trap, CMP and CMPL instructions
 680                     -- Note, we have done RB - RA, not RA - RB
 681                     if e_in.insn_type = OP_CMP then
 682                         l := insn_l(e_in.insn);
 683                     else
 684                         l := not e_in.is_32bit;
 685                     end if;
 686                     zerolo := not (or (a_in(31 downto 0) xor b_in(31 downto 0)));
 687                     zerohi := not (or (a_in(63 downto 32) xor b_in(63 downto 32)));
 688                     if zerolo = '1' and (l = '0' or zerohi = '1') then
 689                         -- values are equal
 690                         trapval := "00100";
 691                     else
 692                         if l = '1' then
 693                             -- 64-bit comparison
 694                             msb_a := a_in(63);
 695                             msb_b := b_in(63);
 696                         else
 697                             -- 32-bit comparison
 698                             msb_a := a_in(31);
 699                             msb_b := b_in(31);
 700                         end if;
 701                         if msb_a /= msb_b then
 702                             -- Subtraction might overflow, but
 703                             -- comparison is clear from MSB difference.
 704                             -- for signed, 0 is greater; for unsigned, 1 is greater
 705                             trapval := msb_a & msb_b & '0' & msb_b & msb_a;
 706                         else
 707                             -- Subtraction cannot overflow since MSBs are equal.
 708                             -- carry = 1 indicates RA is smaller (signed or unsigned)
 709                             a_lt := (not l and carry_32) or (l and carry_64);
 710                             trapval := a_lt & not a_lt & '0' & a_lt & not a_lt;
 711                         end if;
 712                     end if;
 713                     if e_in.insn_type = OP_CMP then
 714                         if e_in.is_signed = '1' then
 715                             newcrf := trapval(4 downto 2) & v.e.xerc.so;
 716                         else
 717                             newcrf := trapval(1 downto 0) & trapval(2) & v.e.xerc.so;
 718                         end if;
 719                         bf := insn_bf(e_in.insn);
 720                         crnum := to_integer(unsigned(bf));
 721                         v.e.write_cr_enable := '1';
 722                         v.e.write_cr_mask := num_to_fxm(crnum);
 723                         for i in 0 to 7 loop
 724                             lo := i*4;
 725                             hi := lo + 3;
 726                             v.e.write_cr_data(hi downto lo) := newcrf;
 727                         end loop;
 728                     else
 729                         -- trap instructions (tw, twi, td, tdi)
 730                         v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
 731                         -- set bit 46 to say trap occurred
 732                         ctrl_tmp.srr1(63 - 46) <= '1';
 733                         if or (trapval and insn_to(e_in.insn)) = '1' then
 734                             -- generate trap-type program interrupt
 735                             exception := '1';
 736                             report "trap";
 737                         end if;
 738                     end if;
 739                 end if;
 740             when OP_ADDG6S =>
 741                 result := (others => '0');
 742                 for i in 0 to 14 loop
 743                     lo := i * 4;
 744                     hi := (i + 1) * 4;
 745                     if (a_in(hi) xor b_in(hi) xor sum_with_carry(hi)) = '0' then
 746                         result(lo + 3 downto lo) := "0110";
 747                     end if;
 748                 end loop;
 749                 if sum_with_carry(64) = '0' then
 750                     result(63 downto 60) := "0110";
 751                 end if;
 752                 result_en := '1';
 753             when OP_CMPRB =>
 754                 newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
 755                 bf := insn_bf(e_in.insn);
 756                 crnum := to_integer(unsigned(bf));
 757                 v.e.write_cr_enable := '1';
 758                 v.e.write_cr_mask := num_to_fxm(crnum);
 759                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 760                                      newcrf & newcrf & newcrf & newcrf;
 761             when OP_CMPEQB =>
 762                 newcrf := ppc_cmpeqb(a_in, b_in);
 763                 bf := insn_bf(e_in.insn);
 764                 crnum := to_integer(unsigned(bf));
 765                 v.e.write_cr_enable := '1';
 766                 v.e.write_cr_mask := num_to_fxm(crnum);
 767                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 768                                      newcrf & newcrf & newcrf & newcrf;
 769             when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
 770                     OP_BPERM | OP_BCD =>
 771                 result := logical_result;
 772                 result_en := '1';
 773             when OP_B =>
 774                 is_branch := '1';
 775                 taken_branch := '1';
 776                 abs_branch := insn_aa(e_in.insn);
 777                 if ctrl.msr(MSR_BE) = '1' then
 778                     do_trace := '1';
 779                 end if;
 780             when OP_BC =>
 781                 -- read_data1 is CTR
 782                 bo := insn_bo(e_in.insn);
 783                 bi := insn_bi(e_in.insn);
 784                 if bo(4-2) = '0' then
 785                     result := std_ulogic_vector(unsigned(a_in) - 1);
 786                     result_en := '1';
 787                     v.e.write_reg := fast_spr_num(SPR_CTR);
 788                 end if;
 789                 is_branch := '1';
 790                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 791                 abs_branch := insn_aa(e_in.insn);
 792                 if ctrl.msr(MSR_BE) = '1' then
 793                     do_trace := '1';
 794                 end if;
 795             when OP_BCREG =>
 796                 -- read_data1 is CTR
 797                 -- read_data2 is target register (CTR, LR or TAR)
 798                 bo := insn_bo(e_in.insn);
 799                 bi := insn_bi(e_in.insn);
 800                 if bo(4-2) = '0' and e_in.insn(10) = '0' then
 801                     result := std_ulogic_vector(unsigned(a_in) - 1);
 802                     result_en := '1';
 803                     v.e.write_reg := fast_spr_num(SPR_CTR);
 804                 end if;
 805                 is_branch := '1';
 806                 taken_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
 807                 abs_branch := '1';
 808                 if ctrl.msr(MSR_BE) = '1' then
 809                     do_trace := '1';
 810                 end if;
 811
 812             when OP_RFID =>
 813                 v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
 814                 v.f.priv_mode := not a_in(MSR_PR);
 815                 v.f.big_endian := not a_in(MSR_LE);
 816                 v.f.mode_32bit := not a_in(MSR_SF);
 817                 -- Can't use msr_copy here because the partial function MSR
 818                 -- bits should be left unchanged, not zeroed.
 819                 ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
 820                 ctrl_tmp.msr(26 downto 22) <= a_in(26 downto 22);
 821                 ctrl_tmp.msr(15 downto 0)  <= a_in(15 downto 0);
 822                 if a_in(MSR_PR) = '1' then
 823                     ctrl_tmp.msr(MSR_EE) <= '1';
 824                     ctrl_tmp.msr(MSR_IR) <= '1';
 825                     ctrl_tmp.msr(MSR_DR) <= '1';
 826                 end if;
 827                 -- mark this as a branch so CFAR gets updated
 828                 is_branch := '1';
 829                 taken_branch := '1';
 830                 abs_branch := '1';
 831                 if HAS_FPU then
 832                     v.fp_exception_next := fp_in.exception and
 833                                            (a_in(MSR_FE0) or a_in(MSR_FE1));
 834                 end if;
 835                 do_trace := '0';
 836
 837             when OP_CNTZ =>
 838                 v.e.valid := '0';
 839                 v.cntz_in_progress := '1';
 840                 v.busy := '1';
 841             when OP_ISEL =>
 842                 crbit := to_integer(unsigned(insn_bc(e_in.insn)));
 843                 if cr_in(31-crbit) = '1' then
 844                     result := a_in;
 845                 else
 846                     result := b_in;
 847                 end if;
 848                 result_en := '1';
 849             when OP_CROP =>
 850                 cr_op := insn_cr(e_in.insn);
 851                 report "CR OP " & to_hstring(cr_op);
 852                 if cr_op(0) = '0' then -- MCRF
 853                     bf := insn_bf(e_in.insn);
 854                     bfa := insn_bfa(e_in.insn);
 855                     v.e.write_cr_enable := '1';
 856                     crnum := to_integer(unsigned(bf));
 857                     scrnum := to_integer(unsigned(bfa));
 858                     v.e.write_cr_mask := num_to_fxm(crnum);
 859                     for i in 0 to 7 loop
 860                         lo := (7-i)*4;
 861                         hi := lo + 3;
 862                         if i = scrnum then
 863                             newcrf := cr_in(hi downto lo);
 864                         end if;
 865                     end loop;
 866                     for i in 0 to 7 loop
 867                         lo := i*4;
 868                         hi := lo + 3;
 869                         v.e.write_cr_data(hi downto lo) := newcrf;
 870                     end loop;
 871                 else
 872                     v.e.write_cr_enable := '1';
 873                     bt := insn_bt(e_in.insn);
 874                     ba := insn_ba(e_in.insn);
 875                     bb := insn_bb(e_in.insn);
 876                     btnum := 31 - to_integer(unsigned(bt));
 877                     banum := 31 - to_integer(unsigned(ba));
 878                     bbnum := 31 - to_integer(unsigned(bb));
 879                     -- Bits 5-8 of cr_op give the truth table of the requested
 880                     -- logical operation
 881                     cr_operands := cr_in(banum) & cr_in(bbnum);
 882                     crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
 883                     v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
 884                     for i in 0 to 31 loop
 885                         if i = btnum then
 886                             v.e.write_cr_data(i) := crresult;
 887                         else
 888                             v.e.write_cr_data(i) := cr_in(i);
 889                         end if;
 890                     end loop;
 891                 end if;
 892             when OP_MCRXRX =>
 893                 newcrf := v.e.xerc.ov & v.e.xerc.ca & v.e.xerc.ov32 & v.e.xerc.ca32;
 894                 bf := insn_bf(e_in.insn);
 895                 crnum := to_integer(unsigned(bf));
 896                 v.e.write_cr_enable := '1';
 897                 v.e.write_cr_mask := num_to_fxm(crnum);
 898                 v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
 899                                      newcrf & newcrf & newcrf & newcrf;
 900             when OP_DARN =>
 901                 if random_err = '0' then
 902                     case e_in.insn(17 downto 16) is
 903                         when "00" =>
 904                             result := x"00000000" & random_cond(31 downto 0);
 905                         when "10" =>
 906                             result := random_raw;
 907                         when others =>
 908                             result := random_cond;
 909                     end case;
 910                 else
 911                     result := (others => '1');
 912                 end if;
 913                 result_en := '1';
 914             when OP_MFMSR =>
 915                 result := ctrl.msr;
 916                 result_en := '1';
 917             when OP_MFSPR =>
 918                 report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
 919                     "=" & to_hstring(a_in);
 920                 result_en := '1';
 921                 if is_fast_spr(e_in.read_reg1) then
 922                     result := a_in;
 923                     if decode_spr_num(e_in.insn) = SPR_XER then
 924                         -- bits 0:31 and 35:43 are treated as reserved and return 0s when read using mfxer
 925                         result(63 downto 32) := (others => '0');
 926                         result(63-32) := v.e.xerc.so;
 927                         result(63-33) := v.e.xerc.ov;
 928                         result(63-34) := v.e.xerc.ca;
 929                         result(63-35 downto 63-43) := "000000000";
 930                         result(63-44) := v.e.xerc.ov32;
 931                         result(63-45) := v.e.xerc.ca32;
 932                     end if;
 933                 else
 934                     spr_val := c_in;
 935                     case decode_spr_num(e_in.insn) is
 936                     when SPR_TB =>
 937                         spr_val := ctrl.tb;
 938                     when SPR_TBU =>
 939                         spr_val(63 downto 32) := (others => '0');
 940                         spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 941                     when SPR_DEC =>
 942                         spr_val := ctrl.dec;
 943                     when SPR_CFAR =>
 944                         spr_val := ctrl.cfar;
 945                     when SPR_PVR =>
 946                         spr_val(63 downto 32) := (others => '0');
 947                         spr_val(31 downto 0) := PVR_MICROWATT;
 948                     when 724 =>     -- LOG_ADDR SPR
 949                         spr_val := log_wr_addr & r.log_addr_spr;
 950                     when 725 =>     -- LOG_DATA SPR
 951                         spr_val := log_rd_data;
 952                         v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
 953                     when others =>
 954                         -- mfspr from unimplemented SPRs should be a nop in
 955                         -- supervisor mode and a program interrupt for user mode
 956                         if ctrl.msr(MSR_PR) = '1' then
 957                             illegal := '1';
 958                         end if;
 959                     end case;
 960                     result := spr_val;
 961                 end if;
 962             when OP_MFCR =>
 963                 if e_in.insn(20) = '0' then
 964                     -- mfcr
 965                     result := x"00000000" & cr_in;
 966                 else
 967                     -- mfocrf
 968                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 969                     result := (others => '0');
 970                     for i in 0 to 7 loop
 971                         lo := (7-i)*4;
 972                         hi := lo + 3;
 973                         if crnum = i then
 974                             result(hi downto lo) := cr_in(hi downto lo);
 975                         end if;
 976                     end loop;
 977                 end if;
 978                 result_en := '1';
 979             when OP_MTCRF =>
 980                 v.e.write_cr_enable := '1';
 981                 if e_in.insn(20) = '0' then
 982                     -- mtcrf
 983                     v.e.write_cr_mask := insn_fxm(e_in.insn);
 984                 else
 985                     -- mtocrf: We require one hot priority encoding here
 986                     crnum := fxm_to_num(insn_fxm(e_in.insn));
 987                     v.e.write_cr_mask := num_to_fxm(crnum);
 988                 end if;
 989                 v.e.write_cr_data := c_in(31 downto 0);
 990             when OP_MTMSRD =>
 991                 if e_in.insn(16) = '1' then
 992                     -- just update EE and RI
 993                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 994                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 995                 else
 996                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 997                     -- and 63 (LE) (IBM bit numbering)
 998                     if e_in.is_32bit = '0' then
 999                         ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
1000                         ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
1001                     end if;
1002                     ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
1003                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
1004                     if c_in(MSR_PR) = '1' then
1005                         ctrl_tmp.msr(MSR_EE) <= '1';
1006                         ctrl_tmp.msr(MSR_IR) <= '1';
1007                         ctrl_tmp.msr(MSR_DR) <= '1';
1008                     end if;
1009                     if HAS_FPU then
1010                         v.fp_exception_next := fp_in.exception and
1011                                                (c_in(MSR_FE0) or c_in(MSR_FE1));
1012                     end if;
1013                 end if;
1014             when OP_MTSPR =>
1015                 report "MTSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
1016                     "=" & to_hstring(c_in);
1017                 if is_fast_spr(e_in.write_reg) then
1018                     result := c_in;
1019                     result_en := '1';
1020                     if decode_spr_num(e_in.insn) = SPR_XER then
1021                         v.e.xerc.so := c_in(63-32);
1022                         v.e.xerc.ov := c_in(63-33);
1023                         v.e.xerc.ca := c_in(63-34);
1024                         v.e.xerc.ov32 := c_in(63-44);
1025                         v.e.xerc.ca32 := c_in(63-45);
1026                         v.e.write_xerc_enable := '1';
1027                     end if;
1028                 else
1029                     -- slow spr
1030                     case decode_spr_num(e_in.insn) is
1031                     when SPR_DEC =>
1032                         ctrl_tmp.dec <= c_in;
1033                     when 724 =>     -- LOG_ADDR SPR
1034                         v.log_addr_spr := c_in(31 downto 0);
1035                     when others =>
1036                         -- mtspr to unimplemented SPRs should be a nop in
1037                         -- supervisor mode and a program interrupt for user mode
1038                         if ctrl.msr(MSR_PR) = '1' then
1039                             illegal := '1';
1040                         end if;
1041                     end case;
1042                 end if;
1043             when OP_RLC | OP_RLCL | OP_RLCR | OP_SHL | OP_SHR | OP_EXTSWSLI =>
1044                 result := rotator_result;
1045                 if e_in.output_carry = '1' then
1046                     set_carry(v.e, rotator_carry, rotator_carry);
1047                 end if;
1048                 result_en := '1';
1049             when OP_SETB =>
1050                 bfa := insn_bfa(e_in.insn);
1051                 crbit := to_integer(unsigned(bfa)) * 4;
1052                 result := (others => '0');
1053                 if cr_in(31 - crbit) = '1' then
1054                     result := (others => '1');
1055                 elsif cr_in(30 - crbit) = '1' then
1056                     result(0) := '1';
1057                 end if;
1058
1059             when OP_ISYNC =>
1060                 v.f.redirect := '1';
1061                 v.f.redirect_nia := next_nia;
1062
1063             when OP_ICBI =>
1064                 icache_inval <= '1';
1065
1066             when OP_MUL_L64 | OP_MUL_H64 | OP_MUL_H32 =>
1067                 v.e.valid := '0';
1068                 v.mul_in_progress := '1';
1069                 v.busy := '1';
1070                 x_to_multiply.valid <= '1';
1071
1072             when OP_DIV | OP_DIVE | OP_MOD =>
1073                 v.e.valid := '0';
1074                 v.div_in_progress := '1';
1075                 v.busy := '1';
1076                 x_to_divider.valid <= '1';
1077
1078             when others =>
1079                 v.terminate := '1';
1080                 report "illegal";
1081             end case;
1082
1083             v.e.rc := e_in.rc and valid_in;
1084
1085             -- Mispredicted branches cause a redirect
1086             if is_branch = '1' then
1087                 if taken_branch = '1' then
1088                     ctrl_tmp.cfar <= e_in.nia;
1089                 end if;
1090                 if e_in.br_pred = '0' then
1091                     if abs_branch = '1' then
1092                         v.f.redirect_nia := b_in;
1093                     else
1094                         v.f.redirect_nia := std_ulogic_vector(signed(e_in.nia) + signed(b_in));
1095                     end if;
1096                 else
1097                     v.f.redirect_nia := next_nia;
1098                 end if;
1099                 if taken_branch /= e_in.br_pred then
1100                     v.f.redirect := '1';
1101                 end if;
1102             end if;
1103
1104             -- Update LR on the next cycle after a branch link
1105             -- If we're not writing back anything else, we can write back LR
1106             -- this cycle, otherwise we take an extra cycle.  We use the
1107             -- exc_write path since next_nia is written through that path
1108             -- in other places.
1109             if e_in.lr = '1' then
1110                 if result_en = '0' then
1111                     v.e.exc_write_enable := '1';
1112                     v.e.exc_write_data := next_nia;
1113                     v.e.exc_write_reg := fast_spr_num(SPR_LR);
1114                 else
1115                     v.lr_update := '1';
1116                     v.next_lr := next_nia;
1117                     v.e.valid := '0';
1118                     report "Delayed LR update to " & to_hstring(next_nia);
1119                     v.busy := '1';
1120                 end if;
1121             end if;
1122
1123         elsif valid_in = '1' then
1124             -- instruction for other units, i.e. LDST
1125             if e_in.unit = LDST then
1126                 lv.valid := '1';
1127             elsif e_in.unit = NONE then
1128                 illegal := '1';
1129             elsif HAS_FPU and e_in.unit = FPU then
1130                 fv.valid := '1';
1131             end if;
1132             -- Handling an ITLB miss doesn't count as having executed an instruction
1133             if e_in.insn_type = OP_FETCH_FAILED then
1134                 do_trace := '0';
1135             end if;
1136         end if;
1137
1138         -- The following cases all occur when r.busy = 1 and therefore
1139         -- valid_in = 0.  Hence they don't happen in the same cycle as any of
1140         -- the cases above which depend on valid_in = 1.
1141
1142         if r.f.redirect = '1' then
1143             v.e.valid := '1';
1144         end if;
1145         if r.lr_update = '1' then
1146             v.e.exc_write_enable := '1';
1147             v.e.exc_write_data := r.next_lr;
1148             v.e.exc_write_reg := fast_spr_num(SPR_LR);
1149             v.e.valid := '1';
1150             -- Keep r.e.write_data unchanged next cycle in case it is needed
1151             -- for a forwarded result (e.g. for CTR).
1152             result := r.e.write_data;
1153         elsif r.cntz_in_progress = '1' then
1154             -- cnt[lt]z always takes two cycles
1155             result := countzero_result;
1156             result_en := '1';
1157             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1158             v.e.rc := r.slow_op_rc;
1159             v.e.xerc := r.slow_op_xerc;
1160             v.e.valid := '1';
1161         elsif r.mul_in_progress = '1' or r.div_in_progress = '1' then
1162             if (r.mul_in_progress = '1' and multiply_to_x.valid = '1') or
1163                (r.div_in_progress = '1' and divider_to_x.valid = '1') then
1164                 if r.mul_in_progress = '1' then
1165                     overflow := '0';
1166                     case r.slow_op_insn is
1167                         when OP_MUL_H32 =>
1168                             result := multiply_to_x.result(63 downto 32) &
1169                                       multiply_to_x.result(63 downto 32);
1170                         when OP_MUL_H64 =>
1171                             result := multiply_to_x.result(127 downto 64);
1172                         when others =>
1173                             -- i.e. OP_MUL_L64
1174                             result := multiply_to_x.result(63 downto 0);
1175                     end case;
1176                 else
1177                     result := divider_to_x.write_reg_data;
1178                     overflow := divider_to_x.overflow;
1179                 end if;
1180                 if r.mul_in_progress = '1' and r.slow_op_oe = '1' then
1181                     -- have to wait until next cycle for overflow indication
1182                     v.mul_finish := '1';
1183                     v.busy := '1';
1184                 else
1185                     result_en := '1';
1186                     v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1187                     v.e.rc := r.slow_op_rc;
1188                     v.e.xerc := r.slow_op_xerc;
1189                     v.e.write_xerc_enable := r.slow_op_oe;
1190                     -- We must test oe because the RC update code in writeback
1191                     -- will use the xerc value to set CR0:SO so we must not clobber
1192                     -- xerc if OE wasn't set.
1193                     if r.slow_op_oe = '1' then
1194                         v.e.xerc.ov := overflow;
1195                         v.e.xerc.ov32 := overflow;
1196                         v.e.xerc.so := r.slow_op_xerc.so or overflow;
1197                     end if;
1198                     v.e.valid := '1';
1199                 end if;
1200             else
1201                 v.busy := '1';
1202                 v.mul_in_progress := r.mul_in_progress;
1203                 v.div_in_progress := r.div_in_progress;
1204             end if;
1205         elsif r.mul_finish = '1' then
1206             result := r.e.write_data;
1207             result_en := '1';
1208             v.e.write_reg := gpr_to_gspr(r.slow_op_dest);
1209             v.e.rc := r.slow_op_rc;
1210             v.e.xerc := r.slow_op_xerc;
1211             v.e.write_xerc_enable := r.slow_op_oe;
1212             v.e.xerc.ov := multiply_to_x.overflow;
1213             v.e.xerc.ov32 := multiply_to_x.overflow;
1214             v.e.xerc.so := r.slow_op_xerc.so or multiply_to_x.overflow;
1215             v.e.valid := '1';
1216         end if;
1217
1218         -- Generate FP-type program interrupt.  fp_in.interrupt will only
1219         -- be set during the execution of a FP instruction.
1220         -- The case where MSR[FE0,FE1] goes from zero to non-zero is
1221         -- handled above by mtmsrd and rfid setting v.fp_exception_next.
1222         if HAS_FPU and fp_in.interrupt = '1' then
1223             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1224             ctrl_tmp.srr1(63 - 43) <= '1';
1225             exception := '1';
1226         end if;
1227
1228         if illegal = '1' or (HAS_FPU and fp_in.illegal = '1') then
1229             exception := '1';
1230             v.f.redirect_nia := std_logic_vector(to_unsigned(16#700#, 64));
1231             -- Since we aren't doing Hypervisor emulation assist (0xe40) we
1232             -- set bit 44 to indicate we have an illegal
1233             ctrl_tmp.srr1(63 - 44) <= '1';
1234             report "illegal";
1235         end if;
1236         if exception = '1' then
1237             v.e.exc_write_enable := '1';
1238             if exception_nextpc = '1' then
1239                 v.e.exc_write_data := next_nia;
1240             end if;
1241         end if;
1242
1243         if do_trace = '1' then
1244             v.trace_next := '1';
1245         end if;
1246
1247         v.e.write_data := result;
1248         v.e.write_enable := result_en and not exception;
1249
1250         -- generate DSI or DSegI for load/store exceptions
1251         -- or ISI or ISegI for instruction fetch exceptions
1252         if l_in.exception = '1' then
1253             if l_in.alignment = '1' then
1254                 v.f.redirect_nia := std_logic_vector(to_unsigned(16#600#, 64));
1255             elsif l_in.instr_fault = '0' then
1256                 if l_in.segment_fault = '0' then
1257                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
1258                 else
1259                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#380#, 64));
1260                 end if;
1261             else
1262                 if l_in.segment_fault = '0' then
1263                     ctrl_tmp.srr1(63 - 33) <= l_in.invalid;
1264                     ctrl_tmp.srr1(63 - 35) <= l_in.perm_error; -- noexec fault
1265                     ctrl_tmp.srr1(63 - 44) <= l_in.badtree;
1266                     ctrl_tmp.srr1(63 - 45) <= l_in.rc_error;
1267                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#400#, 64));
1268                 else
1269                     v.f.redirect_nia := std_logic_vector(to_unsigned(16#480#, 64));
1270                 end if;
1271             end if;
1272             v.e.exc_write_enable := '1';
1273             v.e.exc_write_reg := fast_spr_num(SPR_SRR0);
1274             report "ldst exception writing srr0=" & to_hstring(r.last_nia);
1275         end if;
1276
1277         if exception = '1' or l_in.exception = '1' then
1278             ctrl_tmp.irq_state <= WRITE_SRR1;
1279             v.f.redirect := '1';
1280             v.f.virt_mode := '0';
1281             v.f.priv_mode := '1';
1282             -- XXX need an interrupt LE bit here, e.g. from LPCR
1283             v.f.big_endian := '0';
1284             v.f.mode_32bit := '0';
1285         end if;
1286
1287         if v.f.redirect = '1' then
1288             v.busy := '1';
1289             v.e.valid := '0';
1290         end if;
1291
1292         -- Outputs to loadstore1 (async)
1293         lv.op := e_in.insn_type;
1294         lv.nia := e_in.nia;
1295         lv.addr1 := a_in;
1296         lv.addr2 := b_in;
1297         lv.data := c_in;
1298         lv.write_reg := e_in.write_reg;
1299         lv.length := e_in.data_len;
1300         lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
1301         lv.sign_extend := e_in.sign_extend;
1302         lv.update := e_in.update;
1303         lv.update_reg := gspr_to_gpr(e_in.read_reg1);
1304         lv.xerc := v.e.xerc;
1305         lv.reserve := e_in.reserve;
1306         lv.rc := e_in.rc;
1307         lv.insn := e_in.insn;
1308         -- decode l*cix and st*cix instructions here
1309         if e_in.insn(31 downto 26) = "011111" and e_in.insn(10 downto 9) = "11" and
1310             e_in.insn(5 downto 1) = "10101" then
1311             lv.ci := '1';
1312         end if;
1313         lv.virt_mode := ctrl.msr(MSR_DR);
1314         lv.priv_mode := not ctrl.msr(MSR_PR);
1315         lv.mode_32bit := not ctrl.msr(MSR_SF);
1316         lv.is_32bit := e_in.is_32bit;
1317
1318         -- Outputs to FPU
1319         fv.op := e_in.insn_type;
1320         fv.nia := e_in.nia;
1321         fv.insn := e_in.insn;
1322         fv.single := e_in.is_32bit;
1323         fv.fe_mode := ctrl.msr(MSR_FE0) & ctrl.msr(MSR_FE1);
1324         fv.fra := a_in;
1325         fv.frb := b_in;
1326         fv.frc := c_in;
1327         fv.frt := e_in.write_reg;
1328         fv.rc := e_in.rc;
1329         fv.out_cr := e_in.output_cr;
1330
1331         -- Update registers
1332         rin <= v;
1333
1334         -- update outputs
1335         f_out <= r.f;
1336         l_out <= lv;
1337         e_out <= r.e;
1338         fp_out <= fv;
1339         flush_out <= f_out.redirect;
1340
1341         exception_log <= exception;
1342         irq_valid_log <= irq_valid;
1343     end process;
1344
1345     e1_log: if LOG_LENGTH > 0 generate
1346         signal log_data : std_ulogic_vector(14 downto 0);
1347     begin
1348         ex1_log : process(clk)
1349         begin
1350             if rising_edge(clk) then
1351                 log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) &
1352                             ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) &
1353                             exception_log &
1354                             irq_valid_log &
1355                             std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) &
1356                             "000" &
1357                             r.e.write_enable &
1358                             r.e.valid &
1359                             f_out.redirect &
1360                             r.busy &
1361                             flush_out;
1362             end if;
1363         end process;
1364         log_out <= log_data;
1365     end generate;
1366 end architecture behaviour;