experiments/Makefile

   1 # -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
   2
   3         LOGICAL_SYNTHESIS = Yosys
   4        PHYSICAL_SYNTHESIS = Coriolis
   5                DESIGN_KIT = sxlib
   6
   7 #           YOSYS_FLATTEN = Yes
   8             VST_FLAGS = --vst-use-concat
   9             USE_CLOCKTREE = Yes
  10                 USE_DEBUG = No
  11                  USE_KITE = No
  12
  13                  NETLISTS = $(shell cat nets.txt)
  14                  PATTERNS = alu_hier_r
  15
  16
  17  include ./mk/design-flow.mk
  18
  19
  20 blif:      alu_hier.blif
  21 vst:       alu_hier.vst
  22 layout:    alu_hier_cts_r.ap
  23 gds:       alu_hier_cts_r.gds
  24
  25 lvx:       lvx-alu_hier_cts_r
  26 druc:      druc-alu_hier_cts_r
  27 view:      cgt-alu_hier_cts_r
  28 sim:       asimut-alu_hier_cts_r