experiments10_verilog/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = cmos45
   5             YOSYS_FLATTEN = No
   6             YOSYS_BLACKBOXES = pll
   7                      CHIP = chip
   8                      CORE = add
   9             USE_CLOCKTREE = Yes
  10                 USE_DEBUG = No
  11                  USE_KITE = No
  12                   RM_CHIP = Yes
  13
  14                  NETLISTS = $(shell cat netlists.txt)
  15 #                PATTERNS = add_r
  16
  17
  18  include ./mk/design-flow.mk
  19
  20 # generate verilog file from python nmigen command
  21 add.v: add.py
  22         python3 add.py
  23
  24 chip_r.vst: add.vst
  25         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  26
  27 chip_r.ap: chip_r.vst
  28
  29
  30 blif:      add.blif
  31 vst:       add.vst
  32
  33 lvx:       lvx-chip_r
  34 druc:      druc-chip_r
  35 dreal:     dreal-chip_r
  36 flatph:    flatph-chip_r
  37 view:      cgt-chip_r
  38
  39 layout:    chip_r.ap
  40 gds:       chip_r.gds
  41 gds_flat:  chip_r_flat.gds
  42 cif:       chip_r.cif
  43
  44 view:      cgt-chip_r
  45 sim:       asimut-add_r