experiments11/Makefile

   1
   2         LOGICAL_SYNTHESIS = Yosys
   3        PHYSICAL_SYNTHESIS = Coriolis
   4                DESIGN_KIT = FlexLib018
   5             YOSYS_FLATTEN = No
   6             YOSYS_SET_TOP = Yes
   7                     CHIP  = chip
   8                     CORE  = ls180
   9             USE_CLOCKTREE = Yes
  10                 USE_DEBUG = No
  11                  USE_KITE = No
  12                  RM_CHIP  = Yes
  13 #               VST_FLAGS = --vst-use-concat
  14
  15                  NETLISTS = ls180
  16 #                NETLISTS = $(shell cat cells.lst)
  17 #           YOSYS_FLATTEN = $(shell cat flatten.lst)
  18
  19
  20
  21  include ./mk/design-flow.mk
  22
  23 chip_r.vst: ls180.vst
  24         -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
  25
  26 chip_r.ap: chip_r.vst
  27
  28 blif:      ls180.blif
  29 vst:       ls180.vst
  30 view:      cgt-chip_r
  31 layout:    chip_r.ap