experiments12/Makefile

   1 # -*- explicit-buffer-name: "Makefile<soclayout/experiment12>" -*-
   2
   3         LOGICAL_SYNTHESIS = Yosys
   4        PHYSICAL_SYNTHESIS = Coriolis
   5                DESIGN_KIT = FlexLib018
   6
   7                      CHIP = chip
   8                      CORE = memory
   9             USE_CLOCKTREE = Yes
  10                 USE_DEBUG = No
  11                   RM_CHIP = Yes
  12
  13                 VST_FLAGS = --vst-no-lowercase
  14             YOSYS_FLATTEN =
  15          YOSYS_BLACKBOXES = SPBlock_512W64B8W
  16                  NETLISTS = $(shell cat netlists.txt)
  17
  18
  19  include ./mk/design-flow.mk
  20
  21
  22 blif:      memory.blif
  23 vst:       memory.vst
  24
  25 lvx:       lvx-chip_cts_r
  26 druc:      druc-chip_cts_r
  27 dreal:     dreal-chip_cts_r
  28 flatph:    flatph-chip_cts_r
  29 view:      cgt-chip_cts_r
  30 layout:    chip_cts_r.ap
  31 gds:       chip_cts_r.gds