experiments13/memory.py

   1 from nmigen import Elaboratable, Cat, Module, Signal, Instance, Memory
   2 from nmigen.cli import rtlil
   3
   4
   5 class ADD(Elaboratable):
   6     def __init__(self, width):
   7         self.a   = Signal(width)
   8         self.b   = Signal(width)
   9         self.f   = Signal(width)
  10         self.mem   = Memory(width=64, depth=64, init=range(64))
  11
  12     def elaborate(self, platform):
  13         m = Module()
  14         result = Signal.like(self.f)
  15         m.d.sync += result.eq(self.a + self.b)
  16
  17         # 64k SRAM instance
  18         a = Signal(16)
  19         q = Signal(64) # output
  20         d = Signal(64) # input
  21         we = Signal(1)
  22         # Memory
  23         m.submodules.rdport = rdport = self.mem.read_port()
  24         m.submodules.wrport = wrport = self.mem.write_port()
  25         m.d.comb += [
  26             rdport.addr.eq(a),
  27             q.eq(rdport.data),
  28             wrport.addr.eq(a),
  29             wrport.data.eq(d),
  30             wrport.en.eq(we),
  31         ]
  32
  33         # connect up some arbitrary signals, to get the memory to be
  34         # at least mostly instantiated.
  35         m.d.comb += a.eq(Cat(self.a, self.b, self.a, self.b)) # 16-bit
  36         m.d.comb += we.eq(self.a[0] ^ self.b[0])
  37         # in/out is 4 bit, mem is 64.  just... wrap/add
  38         for i in range(0,64,4):
  39             m.d.comb += d[i:i+4].eq(result)
  40         for i in range(0,64,4):
  41             result = result + q[i:i+4]
  42         m.d.comb += self.f.eq(result)
  43
  44         return m
  45
  46
  47 def create_ilang(dut, ports, test_name):
  48     vl = rtlil.convert(dut, name=test_name, ports=ports)
  49     with open("%s.il" % test_name, "w") as f:
  50         f.write(vl)
  51
  52 if __name__ == "__main__":
  53     alu = ADD(width=4)
  54     create_ilang(alu, [alu.a, alu.b, alu.f], "memory")