experiments9/build_full_4ksram_recon.sh

   1 #!/bin/sh
   2
   3 # full core build including QTY 4of 4k SRAMs: please remember to alter
   4 # doDesign.py before running!
   5 # change the settings to the larger chip/corona size
   6 #
   7 # also contains Staf's manually re-connected PLL edits to the verilog
   8 # see  commits 24cbbcc and 227a0f69
   9 #
  10 echo "remember to check doDesign core size"
  11 echo "also use yosys 049e3abf9"
  12
  13 # initialise/update the pinmux submodule
  14 git submodule update --init --remote
  15
  16 # makes symlinks to alliance
  17 ./mksyms.sh
  18
  19 # generates the io pads needed for ioring.py
  20 make pinmux
  21
  22 # clear out
  23 make clean
  24 rm *.vst *.ap
  25
  26 # copies over a "full" core
  27 #cp non_generated/full_core_4_4ksram_ls180.il ls180.il
  28 cp non_generated/full_core_4_4ksram_ls180.v ls180.v
  29 cp non_generated/full_core_4_4ksram_litex_ls180_recon.v litex_ls180.v
  30 cp non_generated/full_core_4_4ksram_libresoc_recon.v libresoc.v
  31 cp non_generated/spblock*.v .
  32 cp non_generated/spblock*.vbe .
  33 cp non_generated/pll.v .
  34 touch mem.init
  35 touch mem_1.init
  36 touch mem_2.init
  37 touch mem_3.init
  38 touch mem_4.init
  39 touch mem_5.init
  40
  41 # make the vst from verilog
  42 make vst
  43
  44 # starts the build.
  45 make lvx
  46