experiments9/build_full_4ksram_recon.sh

   1 #!/bin/sh
   2
   3 # full core build including QTY 4of 4k SRAMs: please remember to alter
   4 # doDesign.py before running!
   5 # change the settings to the larger chip/corona size
   6 #
   7 # also contains Staf's manually re-connected PLL edits to the verilog
   8 # see  commits 24cbbcc and 227a0f69
   9 #
  10 echo "remember to check doDesign core size"
  11 echo "also use yosys 049e3abf9"
  12
  13 # fetch GDS-II files
  14 echo "fetching GDS-II files"
  15 wget http://ftp.libre-soc.org/C4MLogo.gds
  16 wget http://ftp.libre-soc.org/lip6.gds
  17 wget http://ftp.libre-soc.org/sorbonne_logo.gds
  18 wget http://ftp.libre-soc.org/libresoc_logo.gds
  19
  20 # initialise/update the pinmux submodule
  21 git submodule update --init --remote
  22
  23 # makes symlinks to alliance
  24 ./mksyms.sh
  25
  26 # generates the io pads needed for ioring.py
  27 make pinmux
  28
  29 # clear out
  30 make clean
  31 rm *.vst *.ap *.blif *.gds
  32
  33 # copies over a "full" core
  34 #cp non_generated/full_core_4_4ksram_ls180.il ls180.il
  35 cp non_generated/full_core_4_4ksram_ls180.v ls180.v
  36 cp non_generated/full_core_4_4ksram_litex_ls180_recon.v litex_ls180.v
  37 cp non_generated/full_core_4_4ksram_libresoc_recon.v libresoc.v
  38 cp non_generated/spblock*.v .
  39 cp non_generated/spblock*.vbe .
  40 cp non_generated/pll.v .
  41 touch mem.init
  42 touch mem_1.init
  43 touch mem_2.init
  44 touch mem_3.init
  45 touch mem_4.init
  46 touch mem_5.init
  47
  48 # make the vst from verilog
  49 make vst
  50
  51 # starts the build.
  52 make lvx
  53