experiments9/non_generated/full_core_4_4ksram_litex_ls180.v

   1 //--------------------------------------------------------------------------------
   2 // Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 11:51:10
   3 //--------------------------------------------------------------------------------
   4 module ls180sram4k(
   5         output wire [12:0] sdram_a,
   6         input wire [15:0] sdram_dq_i,
   7         output wire [15:0] sdram_dq_o,
   8         output wire [15:0] sdram_dq_oe,
   9         output wire sdram_we_n,
  10         output wire sdram_ras_n,
  11         output wire sdram_cas_n,
  12         output wire sdram_cs_n,
  13         output wire sdram_cke,
  14         output wire [1:0] sdram_ba,
  15         output wire [1:0] sdram_dm,
  16         output wire sdram_clock,
  17         output wire i2c_scl,
  18         input wire i2c_sda_i,
  19         output wire i2c_sda_o,
  20         output wire i2c_sda_oe,
  21         input wire eint_0,
  22         input wire eint_1,
  23         input wire eint_2,
  24         output wire spimaster_clk,
  25         output wire spimaster_mosi,
  26         output wire spimaster_cs_n,
  27         input wire spimaster_miso,
  28         input wire uart_tx,
  29         input wire uart_rx,
  30         input wire [15:0] gpio_i,
  31         output wire [15:0] gpio_o,
  32         output wire [15:0] gpio_oe,
  33         input wire sys_clk,
  34         input wire sys_rst,
  35         input wire [1:0] sys_clksel_i,
  36         output wire sys_pll_testout_o,
  37         output wire sys_pll_vco_o,
  38         input wire jtag_tms,
  39         input wire jtag_tck,
  40         input wire jtag_tdi,
  41         output wire jtag_tdo,
  42         input wire [34:0] nc
  43 );
  44
  45 (* ram_style = "distributed" *) reg libresocsim_reset_storage = 1'd0;
  46 reg libresocsim_reset_re = 1'd0;
  47 (* ram_style = "distributed" *) reg [31:0] libresocsim_scratch_storage = 32'd305419896;
  48 reg libresocsim_scratch_re = 1'd0;
  49 wire [31:0] libresocsim_bus_errors_status;
  50 wire libresocsim_bus_errors_we;
  51 wire libresocsim_reset;
  52 wire libresocsim_bus_error;
  53 reg [31:0] libresocsim_bus_errors = 32'd0;
  54 wire libresocsim_libresoc_reset;
  55 reg [15:0] libresocsim_libresoc_interrupt = 16'd0;
  56 wire [28:0] libresocsim_libresoc_dbus_adr;
  57 wire [63:0] libresocsim_libresoc_dbus_dat_w;
  58 wire [63:0] libresocsim_libresoc_dbus_dat_r;
  59 wire [7:0] libresocsim_libresoc_dbus_sel;
  60 wire libresocsim_libresoc_dbus_cyc;
  61 wire libresocsim_libresoc_dbus_stb;
  62 reg libresocsim_libresoc_dbus_ack = 1'd0;
  63 wire libresocsim_libresoc_dbus_we;
  64 reg libresocsim_libresoc_dbus_err = 1'd0;
  65 wire [28:0] libresocsim_libresoc_ibus_adr;
  66 wire [63:0] libresocsim_libresoc_ibus_dat_w;
  67 wire [63:0] libresocsim_libresoc_ibus_dat_r;
  68 wire [7:0] libresocsim_libresoc_ibus_sel;
  69 wire libresocsim_libresoc_ibus_cyc;
  70 wire libresocsim_libresoc_ibus_stb;
  71 reg libresocsim_libresoc_ibus_ack = 1'd0;
  72 wire libresocsim_libresoc_ibus_we;
  73 reg libresocsim_libresoc_ibus_err = 1'd0;
  74 wire [29:0] libresocsim_libresoc_xics_icp_adr;
  75 wire [31:0] libresocsim_libresoc_xics_icp_dat_w;
  76 wire [31:0] libresocsim_libresoc_xics_icp_dat_r;
  77 wire [3:0] libresocsim_libresoc_xics_icp_sel;
  78 wire libresocsim_libresoc_xics_icp_cyc;
  79 wire libresocsim_libresoc_xics_icp_stb;
  80 wire libresocsim_libresoc_xics_icp_ack;
  81 wire libresocsim_libresoc_xics_icp_we;
  82 wire [2:0] libresocsim_libresoc_xics_icp_cti;
  83 wire [1:0] libresocsim_libresoc_xics_icp_bte;
  84 wire libresocsim_libresoc_xics_icp_err;
  85 wire [29:0] libresocsim_libresoc_xics_ics_adr;
  86 wire [31:0] libresocsim_libresoc_xics_ics_dat_w;
  87 wire [31:0] libresocsim_libresoc_xics_ics_dat_r;
  88 wire [3:0] libresocsim_libresoc_xics_ics_sel;
  89 wire libresocsim_libresoc_xics_ics_cyc;
  90 wire libresocsim_libresoc_xics_ics_stb;
  91 wire libresocsim_libresoc_xics_ics_ack;
  92 wire libresocsim_libresoc_xics_ics_we;
  93 wire [2:0] libresocsim_libresoc_xics_ics_cti;
  94 wire [1:0] libresocsim_libresoc_xics_ics_bte;
  95 wire libresocsim_libresoc_xics_ics_err;
  96 wire [29:0] libresocsim_libresoc_jtag_wb_adr;
  97 wire [31:0] libresocsim_libresoc_jtag_wb_dat_w;
  98 wire [31:0] libresocsim_libresoc_jtag_wb_dat_r;
  99 wire [3:0] libresocsim_libresoc_jtag_wb_sel;
 100 wire libresocsim_libresoc_jtag_wb_cyc;
 101 wire libresocsim_libresoc_jtag_wb_stb;
 102 wire libresocsim_libresoc_jtag_wb_ack;
 103 wire libresocsim_libresoc_jtag_wb_we;
 104 reg [2:0] libresocsim_libresoc_jtag_wb_cti = 3'd0;
 105 reg [1:0] libresocsim_libresoc_jtag_wb_bte = 2'd0;
 106 wire libresocsim_libresoc_jtag_wb_err;
 107 reg [28:0] libresocsim_libresoc_interface0_adr = 29'd0;
 108 reg [63:0] libresocsim_libresoc_interface0_dat_w = 64'd0;
 109 wire [63:0] libresocsim_libresoc_interface0_dat_r;
 110 reg [7:0] libresocsim_libresoc_interface0_sel = 8'd0;
 111 wire libresocsim_libresoc_interface0_cyc;
 112 wire libresocsim_libresoc_interface0_stb;
 113 wire libresocsim_libresoc_interface0_ack;
 114 wire libresocsim_libresoc_interface0_we;
 115 wire [2:0] libresocsim_libresoc_interface0_cti;
 116 wire [1:0] libresocsim_libresoc_interface0_bte;
 117 wire libresocsim_libresoc_interface0_err;
 118 reg [28:0] libresocsim_libresoc_interface1_adr = 29'd0;
 119 reg [63:0] libresocsim_libresoc_interface1_dat_w = 64'd0;
 120 wire [63:0] libresocsim_libresoc_interface1_dat_r;
 121 reg [7:0] libresocsim_libresoc_interface1_sel = 8'd0;
 122 wire libresocsim_libresoc_interface1_cyc;
 123 wire libresocsim_libresoc_interface1_stb;
 124 wire libresocsim_libresoc_interface1_ack;
 125 wire libresocsim_libresoc_interface1_we;
 126 wire [2:0] libresocsim_libresoc_interface1_cti;
 127 wire [1:0] libresocsim_libresoc_interface1_bte;
 128 wire libresocsim_libresoc_interface1_err;
 129 reg [28:0] libresocsim_libresoc_interface2_adr = 29'd0;
 130 reg [63:0] libresocsim_libresoc_interface2_dat_w = 64'd0;
 131 wire [63:0] libresocsim_libresoc_interface2_dat_r;
 132 reg [7:0] libresocsim_libresoc_interface2_sel = 8'd0;
 133 wire libresocsim_libresoc_interface2_cyc;
 134 wire libresocsim_libresoc_interface2_stb;
 135 wire libresocsim_libresoc_interface2_ack;
 136 wire libresocsim_libresoc_interface2_we;
 137 wire [2:0] libresocsim_libresoc_interface2_cti;
 138 wire [1:0] libresocsim_libresoc_interface2_bte;
 139 wire libresocsim_libresoc_interface2_err;
 140 reg [28:0] libresocsim_libresoc_interface3_adr = 29'd0;
 141 reg [63:0] libresocsim_libresoc_interface3_dat_w = 64'd0;
 142 wire [63:0] libresocsim_libresoc_interface3_dat_r;
 143 reg [7:0] libresocsim_libresoc_interface3_sel = 8'd0;
 144 wire libresocsim_libresoc_interface3_cyc;
 145 wire libresocsim_libresoc_interface3_stb;
 146 wire libresocsim_libresoc_interface3_ack;
 147 wire libresocsim_libresoc_interface3_we;
 148 wire [2:0] libresocsim_libresoc_interface3_cti;
 149 wire [1:0] libresocsim_libresoc_interface3_bte;
 150 wire libresocsim_libresoc_interface3_err;
 151 wire libresocsim_libresoc_jtag_tck;
 152 wire libresocsim_libresoc_jtag_tms;
 153 wire libresocsim_libresoc_jtag_tdi;
 154 wire libresocsim_libresoc_jtag_tdo;
 155 reg [63:0] libresocsim_libresoc0 = 64'd0;
 156 wire libresocsim_libresoc1;
 157 wire libresocsim_libresoc2;
 158 wire [63:0] libresocsim_libresoc3;
 159 wire libresocsim_libresoc_pll_18_o;
 160 wire [1:0] libresocsim_libresoc_clk_sel;
 161 wire libresocsim_libresoc_pll_ana_o;
 162 reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0;
 163 wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i;
 164 reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0;
 165 reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_oe = 16'd0;
 166 reg libresocsim_libresoc_constraintmanager_sdram_we_n = 1'd0;
 167 reg libresocsim_libresoc_constraintmanager_sdram_ras_n = 1'd0;
 168 reg libresocsim_libresoc_constraintmanager_sdram_cas_n = 1'd0;
 169 reg libresocsim_libresoc_constraintmanager_sdram_cs_n = 1'd0;
 170 reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0;
 171 reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0;
 172 reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0;
 173 reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0;
 174 wire libresocsim_libresoc_constraintmanager_i2c_scl;
 175 wire libresocsim_libresoc_constraintmanager_i2c_sda_i;
 176 wire libresocsim_libresoc_constraintmanager_i2c_sda_o;
 177 wire libresocsim_libresoc_constraintmanager_i2c_sda_oe;
 178 wire libresocsim_libresoc_constraintmanager_eint_0;
 179 wire libresocsim_libresoc_constraintmanager_eint_1;
 180 wire libresocsim_libresoc_constraintmanager_eint_2;
 181 reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0;
 182 reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0;
 183 reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0;
 184 wire libresocsim_libresoc_constraintmanager_spimaster_miso;
 185 reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1;
 186 reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0;
 187 wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i;
 188 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0;
 189 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0;
 190 reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0;
 191 reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0;
 192 wire [31:0] libresocsim_interface0_converted_interface_dat_r;
 193 reg [3:0] libresocsim_interface0_converted_interface_sel = 4'd0;
 194 reg libresocsim_interface0_converted_interface_cyc = 1'd0;
 195 reg libresocsim_interface0_converted_interface_stb = 1'd0;
 196 wire libresocsim_interface0_converted_interface_ack;
 197 reg libresocsim_interface0_converted_interface_we = 1'd0;
 198 reg [2:0] libresocsim_interface0_converted_interface_cti = 3'd0;
 199 reg [1:0] libresocsim_interface0_converted_interface_bte = 2'd0;
 200 wire libresocsim_interface0_converted_interface_err;
 201 reg libresocsim_converter0_skip = 1'd0;
 202 reg libresocsim_converter0_counter = 1'd0;
 203 wire libresocsim_converter0_reset;
 204 reg [63:0] libresocsim_converter0_dat_r = 64'd0;
 205 reg [29:0] libresocsim_interface1_converted_interface_adr = 30'd0;
 206 reg [31:0] libresocsim_interface1_converted_interface_dat_w = 32'd0;
 207 wire [31:0] libresocsim_interface1_converted_interface_dat_r;
 208 reg [3:0] libresocsim_interface1_converted_interface_sel = 4'd0;
 209 reg libresocsim_interface1_converted_interface_cyc = 1'd0;
 210 reg libresocsim_interface1_converted_interface_stb = 1'd0;
 211 wire libresocsim_interface1_converted_interface_ack;
 212 reg libresocsim_interface1_converted_interface_we = 1'd0;
 213 reg [2:0] libresocsim_interface1_converted_interface_cti = 3'd0;
 214 reg [1:0] libresocsim_interface1_converted_interface_bte = 2'd0;
 215 wire libresocsim_interface1_converted_interface_err;
 216 reg libresocsim_converter1_skip = 1'd0;
 217 reg libresocsim_converter1_counter = 1'd0;
 218 wire libresocsim_converter1_reset;
 219 reg [63:0] libresocsim_converter1_dat_r = 64'd0;
 220 wire [29:0] libresocsim_ram_bus_adr;
 221 wire [31:0] libresocsim_ram_bus_dat_w;
 222 wire [31:0] libresocsim_ram_bus_dat_r;
 223 wire [3:0] libresocsim_ram_bus_sel;
 224 wire libresocsim_ram_bus_cyc;
 225 wire libresocsim_ram_bus_stb;
 226 reg libresocsim_ram_bus_ack = 1'd0;
 227 wire libresocsim_ram_bus_we;
 228 wire [2:0] libresocsim_ram_bus_cti;
 229 wire [1:0] libresocsim_ram_bus_bte;
 230 reg libresocsim_ram_bus_err = 1'd0;
 231 wire [4:0] libresocsim_adr;
 232 wire [31:0] libresocsim_dat_r;
 233 reg [3:0] libresocsim_we = 4'd0;
 234 wire [31:0] libresocsim_dat_w;
 235 (* ram_style = "distributed" *) reg [31:0] libresocsim_load_storage = 32'd0;
 236 reg libresocsim_load_re = 1'd0;
 237 (* ram_style = "distributed" *) reg [31:0] libresocsim_reload_storage = 32'd0;
 238 reg libresocsim_reload_re = 1'd0;
 239 (* ram_style = "distributed" *) reg libresocsim_en_storage = 1'd0;
 240 reg libresocsim_en_re = 1'd0;
 241 (* ram_style = "distributed" *) reg libresocsim_update_value_storage = 1'd0;
 242 reg libresocsim_update_value_re = 1'd0;
 243 reg [31:0] libresocsim_value_status = 32'd0;
 244 wire libresocsim_value_we;
 245 wire libresocsim_irq;
 246 wire libresocsim_zero_status;
 247 reg libresocsim_zero_pending = 1'd0;
 248 wire libresocsim_zero_trigger;
 249 reg libresocsim_zero_clear = 1'd0;
 250 reg libresocsim_zero_old_trigger = 1'd0;
 251 wire libresocsim_eventmanager_status_re;
 252 wire libresocsim_eventmanager_status_r;
 253 wire libresocsim_eventmanager_status_we;
 254 wire libresocsim_eventmanager_status_w;
 255 wire libresocsim_eventmanager_pending_re;
 256 wire libresocsim_eventmanager_pending_r;
 257 wire libresocsim_eventmanager_pending_we;
 258 wire libresocsim_eventmanager_pending_w;
 259 (* ram_style = "distributed" *) reg libresocsim_eventmanager_storage = 1'd0;
 260 reg libresocsim_eventmanager_re = 1'd0;
 261 reg [31:0] libresocsim_value = 32'd0;
 262 wire [29:0] ram_bus_ram_bus_adr;
 263 wire [31:0] ram_bus_ram_bus_dat_w;
 264 wire [31:0] ram_bus_ram_bus_dat_r;
 265 wire [3:0] ram_bus_ram_bus_sel;
 266 wire ram_bus_ram_bus_cyc;
 267 wire ram_bus_ram_bus_stb;
 268 reg ram_bus_ram_bus_ack = 1'd0;
 269 wire ram_bus_ram_bus_we;
 270 wire [2:0] ram_bus_ram_bus_cti;
 271 wire [1:0] ram_bus_ram_bus_bte;
 272 reg ram_bus_ram_bus_err = 1'd0;
 273 wire [4:0] ram_adr;
 274 wire [31:0] ram_dat_r;
 275 reg [3:0] ram_we = 4'd0;
 276 wire [31:0] ram_dat_w;
 277 wire [29:0] interface0_converted_interface_adr;
 278 wire [31:0] interface0_converted_interface_dat_w;
 279 reg [31:0] interface0_converted_interface_dat_r = 32'd0;
 280 wire [3:0] interface0_converted_interface_sel;
 281 wire interface0_converted_interface_cyc;
 282 wire interface0_converted_interface_stb;
 283 wire interface0_converted_interface_ack;
 284 wire interface0_converted_interface_we;
 285 wire [2:0] interface0_converted_interface_cti;
 286 wire [1:0] interface0_converted_interface_bte;
 287 wire interface0_converted_interface_err;
 288 wire [29:0] interface1_converted_interface_adr;
 289 wire [31:0] interface1_converted_interface_dat_w;
 290 reg [31:0] interface1_converted_interface_dat_r = 32'd0;
 291 wire [3:0] interface1_converted_interface_sel;
 292 wire interface1_converted_interface_cyc;
 293 wire interface1_converted_interface_stb;
 294 wire interface1_converted_interface_ack;
 295 wire interface1_converted_interface_we;
 296 wire [2:0] interface1_converted_interface_cti;
 297 wire [1:0] interface1_converted_interface_bte;
 298 wire interface1_converted_interface_err;
 299 wire [29:0] interface2_converted_interface_adr;
 300 wire [31:0] interface2_converted_interface_dat_w;
 301 reg [31:0] interface2_converted_interface_dat_r = 32'd0;
 302 wire [3:0] interface2_converted_interface_sel;
 303 wire interface2_converted_interface_cyc;
 304 wire interface2_converted_interface_stb;
 305 wire interface2_converted_interface_ack;
 306 wire interface2_converted_interface_we;
 307 wire [2:0] interface2_converted_interface_cti;
 308 wire [1:0] interface2_converted_interface_bte;
 309 wire interface2_converted_interface_err;
 310 wire [29:0] interface3_converted_interface_adr;
 311 wire [31:0] interface3_converted_interface_dat_w;
 312 reg [31:0] interface3_converted_interface_dat_r = 32'd0;
 313 wire [3:0] interface3_converted_interface_sel;
 314 wire interface3_converted_interface_cyc;
 315 wire interface3_converted_interface_stb;
 316 wire interface3_converted_interface_ack;
 317 wire interface3_converted_interface_we;
 318 wire [2:0] interface3_converted_interface_cti;
 319 wire [1:0] interface3_converted_interface_bte;
 320 wire interface3_converted_interface_err;
 321 wire sys_clk_1;
 322 wire sys_rst_1;
 323 wire por_clk;
 324 reg int_rst = 1'd1;
 325 wire [12:0] dfi_p0_address;
 326 wire [1:0] dfi_p0_bank;
 327 wire dfi_p0_cas_n;
 328 wire dfi_p0_cs_n;
 329 wire dfi_p0_ras_n;
 330 wire dfi_p0_we_n;
 331 wire dfi_p0_cke;
 332 wire dfi_p0_odt;
 333 wire dfi_p0_reset_n;
 334 wire dfi_p0_act_n;
 335 wire [15:0] dfi_p0_wrdata;
 336 wire dfi_p0_wrdata_en;
 337 wire [1:0] dfi_p0_wrdata_mask;
 338 wire dfi_p0_rddata_en;
 339 reg [15:0] dfi_p0_rddata = 16'd0;
 340 reg dfi_p0_rddata_valid = 1'd0;
 341 reg [2:0] rddata_en = 3'd0;
 342 wire [12:0] sdram_inti_p0_address;
 343 wire [1:0] sdram_inti_p0_bank;
 344 reg sdram_inti_p0_cas_n = 1'd1;
 345 reg sdram_inti_p0_cs_n = 1'd1;
 346 reg sdram_inti_p0_ras_n = 1'd1;
 347 reg sdram_inti_p0_we_n = 1'd1;
 348 wire sdram_inti_p0_cke;
 349 wire sdram_inti_p0_odt;
 350 wire sdram_inti_p0_reset_n;
 351 reg sdram_inti_p0_act_n = 1'd1;
 352 wire [15:0] sdram_inti_p0_wrdata;
 353 wire sdram_inti_p0_wrdata_en;
 354 wire [1:0] sdram_inti_p0_wrdata_mask;
 355 wire sdram_inti_p0_rddata_en;
 356 reg [15:0] sdram_inti_p0_rddata = 16'd0;
 357 reg sdram_inti_p0_rddata_valid = 1'd0;
 358 wire [12:0] sdram_slave_p0_address;
 359 wire [1:0] sdram_slave_p0_bank;
 360 wire sdram_slave_p0_cas_n;
 361 wire sdram_slave_p0_cs_n;
 362 wire sdram_slave_p0_ras_n;
 363 wire sdram_slave_p0_we_n;
 364 wire sdram_slave_p0_cke;
 365 wire sdram_slave_p0_odt;
 366 wire sdram_slave_p0_reset_n;
 367 wire sdram_slave_p0_act_n;
 368 wire [15:0] sdram_slave_p0_wrdata;
 369 wire sdram_slave_p0_wrdata_en;
 370 wire [1:0] sdram_slave_p0_wrdata_mask;
 371 wire sdram_slave_p0_rddata_en;
 372 reg [15:0] sdram_slave_p0_rddata = 16'd0;
 373 reg sdram_slave_p0_rddata_valid = 1'd0;
 374 reg [12:0] sdram_master_p0_address = 13'd0;
 375 reg [1:0] sdram_master_p0_bank = 2'd0;
 376 reg sdram_master_p0_cas_n = 1'd1;
 377 reg sdram_master_p0_cs_n = 1'd1;
 378 reg sdram_master_p0_ras_n = 1'd1;
 379 reg sdram_master_p0_we_n = 1'd1;
 380 reg sdram_master_p0_cke = 1'd0;
 381 reg sdram_master_p0_odt = 1'd0;
 382 reg sdram_master_p0_reset_n = 1'd0;
 383 reg sdram_master_p0_act_n = 1'd1;
 384 reg [15:0] sdram_master_p0_wrdata = 16'd0;
 385 reg sdram_master_p0_wrdata_en = 1'd0;
 386 reg [1:0] sdram_master_p0_wrdata_mask = 2'd0;
 387 reg sdram_master_p0_rddata_en = 1'd0;
 388 wire [15:0] sdram_master_p0_rddata;
 389 wire sdram_master_p0_rddata_valid;
 390 wire sdram_sel;
 391 wire sdram_cke_1;
 392 wire sdram_odt;
 393 wire sdram_reset_n;
 394 (* ram_style = "distributed" *) reg [3:0] sdram_storage = 4'd1;
 395 reg sdram_re = 1'd0;
 396 (* ram_style = "distributed" *) reg [5:0] sdram_command_storage = 6'd0;
 397 reg sdram_command_re = 1'd0;
 398 wire sdram_command_issue_re;
 399 wire sdram_command_issue_r;
 400 wire sdram_command_issue_we;
 401 reg sdram_command_issue_w = 1'd0;
 402 (* ram_style = "distributed" *) reg [12:0] sdram_address_storage = 13'd0;
 403 reg sdram_address_re = 1'd0;
 404 (* ram_style = "distributed" *) reg [1:0] sdram_baddress_storage = 2'd0;
 405 reg sdram_baddress_re = 1'd0;
 406 (* ram_style = "distributed" *) reg [15:0] sdram_wrdata_storage = 16'd0;
 407 reg sdram_wrdata_re = 1'd0;
 408 reg [15:0] sdram_status = 16'd0;
 409 wire sdram_we;
 410 wire sdram_interface_bank0_valid;
 411 wire sdram_interface_bank0_ready;
 412 wire sdram_interface_bank0_we;
 413 wire [21:0] sdram_interface_bank0_addr;
 414 wire sdram_interface_bank0_lock;
 415 wire sdram_interface_bank0_wdata_ready;
 416 wire sdram_interface_bank0_rdata_valid;
 417 wire sdram_interface_bank1_valid;
 418 wire sdram_interface_bank1_ready;
 419 wire sdram_interface_bank1_we;
 420 wire [21:0] sdram_interface_bank1_addr;
 421 wire sdram_interface_bank1_lock;
 422 wire sdram_interface_bank1_wdata_ready;
 423 wire sdram_interface_bank1_rdata_valid;
 424 wire sdram_interface_bank2_valid;
 425 wire sdram_interface_bank2_ready;
 426 wire sdram_interface_bank2_we;
 427 wire [21:0] sdram_interface_bank2_addr;
 428 wire sdram_interface_bank2_lock;
 429 wire sdram_interface_bank2_wdata_ready;
 430 wire sdram_interface_bank2_rdata_valid;
 431 wire sdram_interface_bank3_valid;
 432 wire sdram_interface_bank3_ready;
 433 wire sdram_interface_bank3_we;
 434 wire [21:0] sdram_interface_bank3_addr;
 435 wire sdram_interface_bank3_lock;
 436 wire sdram_interface_bank3_wdata_ready;
 437 wire sdram_interface_bank3_rdata_valid;
 438 reg [15:0] sdram_interface_wdata = 16'd0;
 439 reg [1:0] sdram_interface_wdata_we = 2'd0;
 440 wire [15:0] sdram_interface_rdata;
 441 reg [12:0] sdram_dfi_p0_address = 13'd0;
 442 reg [1:0] sdram_dfi_p0_bank = 2'd0;
 443 reg sdram_dfi_p0_cas_n = 1'd1;
 444 reg sdram_dfi_p0_cs_n = 1'd1;
 445 reg sdram_dfi_p0_ras_n = 1'd1;
 446 reg sdram_dfi_p0_we_n = 1'd1;
 447 wire sdram_dfi_p0_cke;
 448 wire sdram_dfi_p0_odt;
 449 wire sdram_dfi_p0_reset_n;
 450 reg sdram_dfi_p0_act_n = 1'd1;
 451 wire [15:0] sdram_dfi_p0_wrdata;
 452 reg sdram_dfi_p0_wrdata_en = 1'd0;
 453 wire [1:0] sdram_dfi_p0_wrdata_mask;
 454 reg sdram_dfi_p0_rddata_en = 1'd0;
 455 wire [15:0] sdram_dfi_p0_rddata;
 456 wire sdram_dfi_p0_rddata_valid;
 457 reg sdram_cmd_valid = 1'd0;
 458 reg sdram_cmd_ready = 1'd0;
 459 reg sdram_cmd_last = 1'd0;
 460 reg [12:0] sdram_cmd_payload_a = 13'd0;
 461 reg [1:0] sdram_cmd_payload_ba = 2'd0;
 462 reg sdram_cmd_payload_cas = 1'd0;
 463 reg sdram_cmd_payload_ras = 1'd0;
 464 reg sdram_cmd_payload_we = 1'd0;
 465 reg sdram_cmd_payload_is_read = 1'd0;
 466 reg sdram_cmd_payload_is_write = 1'd0;
 467 wire sdram_wants_refresh;
 468 wire sdram_timer_wait;
 469 wire sdram_timer_done0;
 470 wire [9:0] sdram_timer_count0;
 471 wire sdram_timer_done1;
 472 reg [9:0] sdram_timer_count1 = 10'd781;
 473 wire sdram_postponer_req_i;
 474 reg sdram_postponer_req_o = 1'd0;
 475 reg sdram_postponer_count = 1'd0;
 476 reg sdram_sequencer_start0 = 1'd0;
 477 wire sdram_sequencer_done0;
 478 wire sdram_sequencer_start1;
 479 reg sdram_sequencer_done1 = 1'd0;
 480 reg [3:0] sdram_sequencer_counter = 4'd0;
 481 reg sdram_sequencer_count = 1'd0;
 482 wire sdram_bankmachine0_req_valid;
 483 wire sdram_bankmachine0_req_ready;
 484 wire sdram_bankmachine0_req_we;
 485 wire [21:0] sdram_bankmachine0_req_addr;
 486 wire sdram_bankmachine0_req_lock;
 487 reg sdram_bankmachine0_req_wdata_ready = 1'd0;
 488 reg sdram_bankmachine0_req_rdata_valid = 1'd0;
 489 wire sdram_bankmachine0_refresh_req;
 490 reg sdram_bankmachine0_refresh_gnt = 1'd0;
 491 reg sdram_bankmachine0_cmd_valid = 1'd0;
 492 reg sdram_bankmachine0_cmd_ready = 1'd0;
 493 reg [12:0] sdram_bankmachine0_cmd_payload_a = 13'd0;
 494 wire [1:0] sdram_bankmachine0_cmd_payload_ba;
 495 reg sdram_bankmachine0_cmd_payload_cas = 1'd0;
 496 reg sdram_bankmachine0_cmd_payload_ras = 1'd0;
 497 reg sdram_bankmachine0_cmd_payload_we = 1'd0;
 498 reg sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
 499 reg sdram_bankmachine0_cmd_payload_is_read = 1'd0;
 500 reg sdram_bankmachine0_cmd_payload_is_write = 1'd0;
 501 reg sdram_bankmachine0_auto_precharge = 1'd0;
 502 wire sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
 503 wire sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
 504 reg sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
 505 reg sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 506 wire sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 507 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 508 wire sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
 509 wire sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
 510 wire sdram_bankmachine0_cmd_buffer_lookahead_source_first;
 511 wire sdram_bankmachine0_cmd_buffer_lookahead_source_last;
 512 wire sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
 513 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
 514 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
 515 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
 516 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 517 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 518 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 519 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
 520 reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0;
 521 reg sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
 522 reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0;
 523 reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0;
 524 reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0;
 525 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 526 wire sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
 527 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
 528 wire sdram_bankmachine0_cmd_buffer_lookahead_do_read;
 529 wire [2:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
 530 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
 531 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
 532 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
 533 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
 534 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
 535 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
 536 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 537 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
 538 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
 539 wire sdram_bankmachine0_cmd_buffer_sink_valid;
 540 wire sdram_bankmachine0_cmd_buffer_sink_ready;
 541 wire sdram_bankmachine0_cmd_buffer_sink_first;
 542 wire sdram_bankmachine0_cmd_buffer_sink_last;
 543 wire sdram_bankmachine0_cmd_buffer_sink_payload_we;
 544 wire [21:0] sdram_bankmachine0_cmd_buffer_sink_payload_addr;
 545 reg sdram_bankmachine0_cmd_buffer_source_valid = 1'd0;
 546 wire sdram_bankmachine0_cmd_buffer_source_ready;
 547 reg sdram_bankmachine0_cmd_buffer_source_first = 1'd0;
 548 reg sdram_bankmachine0_cmd_buffer_source_last = 1'd0;
 549 reg sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
 550 reg [21:0] sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
 551 reg [12:0] sdram_bankmachine0_row = 13'd0;
 552 reg sdram_bankmachine0_row_opened = 1'd0;
 553 wire sdram_bankmachine0_row_hit;
 554 reg sdram_bankmachine0_row_open = 1'd0;
 555 reg sdram_bankmachine0_row_close = 1'd0;
 556 reg sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
 557 wire sdram_bankmachine0_twtpcon_valid;
 558 (* no_retiming = "true" *) reg sdram_bankmachine0_twtpcon_ready = 1'd0;
 559 reg [2:0] sdram_bankmachine0_twtpcon_count = 3'd0;
 560 wire sdram_bankmachine0_trccon_valid;
 561 (* no_retiming = "true" *) reg sdram_bankmachine0_trccon_ready = 1'd1;
 562 wire sdram_bankmachine0_trascon_valid;
 563 (* no_retiming = "true" *) reg sdram_bankmachine0_trascon_ready = 1'd1;
 564 wire sdram_bankmachine1_req_valid;
 565 wire sdram_bankmachine1_req_ready;
 566 wire sdram_bankmachine1_req_we;
 567 wire [21:0] sdram_bankmachine1_req_addr;
 568 wire sdram_bankmachine1_req_lock;
 569 reg sdram_bankmachine1_req_wdata_ready = 1'd0;
 570 reg sdram_bankmachine1_req_rdata_valid = 1'd0;
 571 wire sdram_bankmachine1_refresh_req;
 572 reg sdram_bankmachine1_refresh_gnt = 1'd0;
 573 reg sdram_bankmachine1_cmd_valid = 1'd0;
 574 reg sdram_bankmachine1_cmd_ready = 1'd0;
 575 reg [12:0] sdram_bankmachine1_cmd_payload_a = 13'd0;
 576 wire [1:0] sdram_bankmachine1_cmd_payload_ba;
 577 reg sdram_bankmachine1_cmd_payload_cas = 1'd0;
 578 reg sdram_bankmachine1_cmd_payload_ras = 1'd0;
 579 reg sdram_bankmachine1_cmd_payload_we = 1'd0;
 580 reg sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
 581 reg sdram_bankmachine1_cmd_payload_is_read = 1'd0;
 582 reg sdram_bankmachine1_cmd_payload_is_write = 1'd0;
 583 reg sdram_bankmachine1_auto_precharge = 1'd0;
 584 wire sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
 585 wire sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
 586 reg sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
 587 reg sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 588 wire sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 589 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 590 wire sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
 591 wire sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
 592 wire sdram_bankmachine1_cmd_buffer_lookahead_source_first;
 593 wire sdram_bankmachine1_cmd_buffer_lookahead_source_last;
 594 wire sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
 595 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
 596 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
 597 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
 598 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 599 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 600 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 601 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
 602 reg [3:0] sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0;
 603 reg sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
 604 reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0;
 605 reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0;
 606 reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0;
 607 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 608 wire sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
 609 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
 610 wire sdram_bankmachine1_cmd_buffer_lookahead_do_read;
 611 wire [2:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
 612 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
 613 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
 614 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
 615 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
 616 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
 617 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
 618 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 619 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
 620 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
 621 wire sdram_bankmachine1_cmd_buffer_sink_valid;
 622 wire sdram_bankmachine1_cmd_buffer_sink_ready;
 623 wire sdram_bankmachine1_cmd_buffer_sink_first;
 624 wire sdram_bankmachine1_cmd_buffer_sink_last;
 625 wire sdram_bankmachine1_cmd_buffer_sink_payload_we;
 626 wire [21:0] sdram_bankmachine1_cmd_buffer_sink_payload_addr;
 627 reg sdram_bankmachine1_cmd_buffer_source_valid = 1'd0;
 628 wire sdram_bankmachine1_cmd_buffer_source_ready;
 629 reg sdram_bankmachine1_cmd_buffer_source_first = 1'd0;
 630 reg sdram_bankmachine1_cmd_buffer_source_last = 1'd0;
 631 reg sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
 632 reg [21:0] sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
 633 reg [12:0] sdram_bankmachine1_row = 13'd0;
 634 reg sdram_bankmachine1_row_opened = 1'd0;
 635 wire sdram_bankmachine1_row_hit;
 636 reg sdram_bankmachine1_row_open = 1'd0;
 637 reg sdram_bankmachine1_row_close = 1'd0;
 638 reg sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
 639 wire sdram_bankmachine1_twtpcon_valid;
 640 (* no_retiming = "true" *) reg sdram_bankmachine1_twtpcon_ready = 1'd0;
 641 reg [2:0] sdram_bankmachine1_twtpcon_count = 3'd0;
 642 wire sdram_bankmachine1_trccon_valid;
 643 (* no_retiming = "true" *) reg sdram_bankmachine1_trccon_ready = 1'd1;
 644 wire sdram_bankmachine1_trascon_valid;
 645 (* no_retiming = "true" *) reg sdram_bankmachine1_trascon_ready = 1'd1;
 646 wire sdram_bankmachine2_req_valid;
 647 wire sdram_bankmachine2_req_ready;
 648 wire sdram_bankmachine2_req_we;
 649 wire [21:0] sdram_bankmachine2_req_addr;
 650 wire sdram_bankmachine2_req_lock;
 651 reg sdram_bankmachine2_req_wdata_ready = 1'd0;
 652 reg sdram_bankmachine2_req_rdata_valid = 1'd0;
 653 wire sdram_bankmachine2_refresh_req;
 654 reg sdram_bankmachine2_refresh_gnt = 1'd0;
 655 reg sdram_bankmachine2_cmd_valid = 1'd0;
 656 reg sdram_bankmachine2_cmd_ready = 1'd0;
 657 reg [12:0] sdram_bankmachine2_cmd_payload_a = 13'd0;
 658 wire [1:0] sdram_bankmachine2_cmd_payload_ba;
 659 reg sdram_bankmachine2_cmd_payload_cas = 1'd0;
 660 reg sdram_bankmachine2_cmd_payload_ras = 1'd0;
 661 reg sdram_bankmachine2_cmd_payload_we = 1'd0;
 662 reg sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
 663 reg sdram_bankmachine2_cmd_payload_is_read = 1'd0;
 664 reg sdram_bankmachine2_cmd_payload_is_write = 1'd0;
 665 reg sdram_bankmachine2_auto_precharge = 1'd0;
 666 wire sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
 667 wire sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
 668 reg sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
 669 reg sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 670 wire sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 671 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 672 wire sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
 673 wire sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
 674 wire sdram_bankmachine2_cmd_buffer_lookahead_source_first;
 675 wire sdram_bankmachine2_cmd_buffer_lookahead_source_last;
 676 wire sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
 677 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
 678 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
 679 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
 680 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 681 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 682 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 683 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
 684 reg [3:0] sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0;
 685 reg sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
 686 reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0;
 687 reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0;
 688 reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0;
 689 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 690 wire sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
 691 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
 692 wire sdram_bankmachine2_cmd_buffer_lookahead_do_read;
 693 wire [2:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
 694 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
 695 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
 696 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
 697 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
 698 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
 699 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
 700 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 701 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
 702 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
 703 wire sdram_bankmachine2_cmd_buffer_sink_valid;
 704 wire sdram_bankmachine2_cmd_buffer_sink_ready;
 705 wire sdram_bankmachine2_cmd_buffer_sink_first;
 706 wire sdram_bankmachine2_cmd_buffer_sink_last;
 707 wire sdram_bankmachine2_cmd_buffer_sink_payload_we;
 708 wire [21:0] sdram_bankmachine2_cmd_buffer_sink_payload_addr;
 709 reg sdram_bankmachine2_cmd_buffer_source_valid = 1'd0;
 710 wire sdram_bankmachine2_cmd_buffer_source_ready;
 711 reg sdram_bankmachine2_cmd_buffer_source_first = 1'd0;
 712 reg sdram_bankmachine2_cmd_buffer_source_last = 1'd0;
 713 reg sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
 714 reg [21:0] sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
 715 reg [12:0] sdram_bankmachine2_row = 13'd0;
 716 reg sdram_bankmachine2_row_opened = 1'd0;
 717 wire sdram_bankmachine2_row_hit;
 718 reg sdram_bankmachine2_row_open = 1'd0;
 719 reg sdram_bankmachine2_row_close = 1'd0;
 720 reg sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
 721 wire sdram_bankmachine2_twtpcon_valid;
 722 (* no_retiming = "true" *) reg sdram_bankmachine2_twtpcon_ready = 1'd0;
 723 reg [2:0] sdram_bankmachine2_twtpcon_count = 3'd0;
 724 wire sdram_bankmachine2_trccon_valid;
 725 (* no_retiming = "true" *) reg sdram_bankmachine2_trccon_ready = 1'd1;
 726 wire sdram_bankmachine2_trascon_valid;
 727 (* no_retiming = "true" *) reg sdram_bankmachine2_trascon_ready = 1'd1;
 728 wire sdram_bankmachine3_req_valid;
 729 wire sdram_bankmachine3_req_ready;
 730 wire sdram_bankmachine3_req_we;
 731 wire [21:0] sdram_bankmachine3_req_addr;
 732 wire sdram_bankmachine3_req_lock;
 733 reg sdram_bankmachine3_req_wdata_ready = 1'd0;
 734 reg sdram_bankmachine3_req_rdata_valid = 1'd0;
 735 wire sdram_bankmachine3_refresh_req;
 736 reg sdram_bankmachine3_refresh_gnt = 1'd0;
 737 reg sdram_bankmachine3_cmd_valid = 1'd0;
 738 reg sdram_bankmachine3_cmd_ready = 1'd0;
 739 reg [12:0] sdram_bankmachine3_cmd_payload_a = 13'd0;
 740 wire [1:0] sdram_bankmachine3_cmd_payload_ba;
 741 reg sdram_bankmachine3_cmd_payload_cas = 1'd0;
 742 reg sdram_bankmachine3_cmd_payload_ras = 1'd0;
 743 reg sdram_bankmachine3_cmd_payload_we = 1'd0;
 744 reg sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
 745 reg sdram_bankmachine3_cmd_payload_is_read = 1'd0;
 746 reg sdram_bankmachine3_cmd_payload_is_write = 1'd0;
 747 reg sdram_bankmachine3_auto_precharge = 1'd0;
 748 wire sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
 749 wire sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
 750 reg sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
 751 reg sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 752 wire sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 753 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 754 wire sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
 755 wire sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
 756 wire sdram_bankmachine3_cmd_buffer_lookahead_source_first;
 757 wire sdram_bankmachine3_cmd_buffer_lookahead_source_last;
 758 wire sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
 759 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
 760 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
 761 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
 762 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 763 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 764 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 765 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
 766 reg [3:0] sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0;
 767 reg sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
 768 reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0;
 769 reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0;
 770 reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0;
 771 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 772 wire sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
 773 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
 774 wire sdram_bankmachine3_cmd_buffer_lookahead_do_read;
 775 wire [2:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
 776 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
 777 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
 778 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
 779 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
 780 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
 781 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
 782 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 783 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
 784 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
 785 wire sdram_bankmachine3_cmd_buffer_sink_valid;
 786 wire sdram_bankmachine3_cmd_buffer_sink_ready;
 787 wire sdram_bankmachine3_cmd_buffer_sink_first;
 788 wire sdram_bankmachine3_cmd_buffer_sink_last;
 789 wire sdram_bankmachine3_cmd_buffer_sink_payload_we;
 790 wire [21:0] sdram_bankmachine3_cmd_buffer_sink_payload_addr;
 791 reg sdram_bankmachine3_cmd_buffer_source_valid = 1'd0;
 792 wire sdram_bankmachine3_cmd_buffer_source_ready;
 793 reg sdram_bankmachine3_cmd_buffer_source_first = 1'd0;
 794 reg sdram_bankmachine3_cmd_buffer_source_last = 1'd0;
 795 reg sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
 796 reg [21:0] sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
 797 reg [12:0] sdram_bankmachine3_row = 13'd0;
 798 reg sdram_bankmachine3_row_opened = 1'd0;
 799 wire sdram_bankmachine3_row_hit;
 800 reg sdram_bankmachine3_row_open = 1'd0;
 801 reg sdram_bankmachine3_row_close = 1'd0;
 802 reg sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
 803 wire sdram_bankmachine3_twtpcon_valid;
 804 (* no_retiming = "true" *) reg sdram_bankmachine3_twtpcon_ready = 1'd0;
 805 reg [2:0] sdram_bankmachine3_twtpcon_count = 3'd0;
 806 wire sdram_bankmachine3_trccon_valid;
 807 (* no_retiming = "true" *) reg sdram_bankmachine3_trccon_ready = 1'd1;
 808 wire sdram_bankmachine3_trascon_valid;
 809 (* no_retiming = "true" *) reg sdram_bankmachine3_trascon_ready = 1'd1;
 810 wire sdram_ras_allowed;
 811 wire sdram_cas_allowed;
 812 reg sdram_choose_cmd_want_reads = 1'd0;
 813 reg sdram_choose_cmd_want_writes = 1'd0;
 814 reg sdram_choose_cmd_want_cmds = 1'd0;
 815 reg sdram_choose_cmd_want_activates = 1'd0;
 816 wire sdram_choose_cmd_cmd_valid;
 817 reg sdram_choose_cmd_cmd_ready = 1'd0;
 818 wire [12:0] sdram_choose_cmd_cmd_payload_a;
 819 wire [1:0] sdram_choose_cmd_cmd_payload_ba;
 820 reg sdram_choose_cmd_cmd_payload_cas = 1'd0;
 821 reg sdram_choose_cmd_cmd_payload_ras = 1'd0;
 822 reg sdram_choose_cmd_cmd_payload_we = 1'd0;
 823 wire sdram_choose_cmd_cmd_payload_is_cmd;
 824 wire sdram_choose_cmd_cmd_payload_is_read;
 825 wire sdram_choose_cmd_cmd_payload_is_write;
 826 reg [3:0] sdram_choose_cmd_valids = 4'd0;
 827 wire [3:0] sdram_choose_cmd_request;
 828 reg [1:0] sdram_choose_cmd_grant = 2'd0;
 829 wire sdram_choose_cmd_ce;
 830 reg sdram_choose_req_want_reads = 1'd0;
 831 reg sdram_choose_req_want_writes = 1'd0;
 832 wire sdram_choose_req_want_cmds;
 833 reg sdram_choose_req_want_activates = 1'd0;
 834 wire sdram_choose_req_cmd_valid;
 835 reg sdram_choose_req_cmd_ready = 1'd0;
 836 wire [12:0] sdram_choose_req_cmd_payload_a;
 837 wire [1:0] sdram_choose_req_cmd_payload_ba;
 838 reg sdram_choose_req_cmd_payload_cas = 1'd0;
 839 reg sdram_choose_req_cmd_payload_ras = 1'd0;
 840 reg sdram_choose_req_cmd_payload_we = 1'd0;
 841 wire sdram_choose_req_cmd_payload_is_cmd;
 842 wire sdram_choose_req_cmd_payload_is_read;
 843 wire sdram_choose_req_cmd_payload_is_write;
 844 reg [3:0] sdram_choose_req_valids = 4'd0;
 845 wire [3:0] sdram_choose_req_request;
 846 reg [1:0] sdram_choose_req_grant = 2'd0;
 847 wire sdram_choose_req_ce;
 848 reg [12:0] sdram_nop_a = 13'd0;
 849 reg [1:0] sdram_nop_ba = 2'd0;
 850 reg [1:0] sdram_steerer_sel = 2'd0;
 851 reg sdram_steerer0 = 1'd1;
 852 reg sdram_steerer1 = 1'd1;
 853 wire sdram_trrdcon_valid;
 854 (* no_retiming = "true" *) reg sdram_trrdcon_ready = 1'd1;
 855 wire sdram_tfawcon_valid;
 856 (* no_retiming = "true" *) reg sdram_tfawcon_ready = 1'd1;
 857 wire sdram_tccdcon_valid;
 858 (* no_retiming = "true" *) reg sdram_tccdcon_ready = 1'd0;
 859 reg sdram_tccdcon_count = 1'd0;
 860 wire sdram_twtrcon_valid;
 861 (* no_retiming = "true" *) reg sdram_twtrcon_ready = 1'd0;
 862 reg [2:0] sdram_twtrcon_count = 3'd0;
 863 wire sdram_read_available;
 864 wire sdram_write_available;
 865 reg sdram_en0 = 1'd0;
 866 wire sdram_max_time0;
 867 reg [4:0] sdram_time0 = 5'd0;
 868 reg sdram_en1 = 1'd0;
 869 wire sdram_max_time1;
 870 reg [3:0] sdram_time1 = 4'd0;
 871 wire sdram_go_to_refresh;
 872 wire port_flush;
 873 wire port_cmd_valid;
 874 wire port_cmd_ready;
 875 wire port_cmd_last;
 876 wire port_cmd_payload_we;
 877 wire [23:0] port_cmd_payload_addr;
 878 wire port_wdata_valid;
 879 wire port_wdata_ready;
 880 wire [15:0] port_wdata_payload_data;
 881 wire [1:0] port_wdata_payload_we;
 882 wire port_rdata_valid;
 883 wire port_rdata_ready;
 884 wire [15:0] port_rdata_payload_data;
 885 wire [29:0] wb_sdram_adr;
 886 wire [31:0] wb_sdram_dat_w;
 887 wire [31:0] wb_sdram_dat_r;
 888 wire [3:0] wb_sdram_sel;
 889 wire wb_sdram_cyc;
 890 wire wb_sdram_stb;
 891 reg wb_sdram_ack = 1'd0;
 892 wire wb_sdram_we;
 893 wire [2:0] wb_sdram_cti;
 894 wire [1:0] wb_sdram_bte;
 895 reg wb_sdram_err = 1'd0;
 896 reg [29:0] litedram_wb_adr = 30'd0;
 897 reg [15:0] litedram_wb_dat_w = 16'd0;
 898 wire [15:0] litedram_wb_dat_r;
 899 reg [1:0] litedram_wb_sel = 2'd0;
 900 reg litedram_wb_cyc = 1'd0;
 901 reg litedram_wb_stb = 1'd0;
 902 wire litedram_wb_ack;
 903 reg litedram_wb_we = 1'd0;
 904 reg converter_skip = 1'd0;
 905 reg converter_counter = 1'd0;
 906 wire converter_reset;
 907 reg [31:0] converter_dat_r = 32'd0;
 908 reg cmd_consumed = 1'd0;
 909 reg wdata_consumed = 1'd0;
 910 wire ack_cmd;
 911 wire ack_wdata;
 912 wire ack_rdata;
 913 (* ram_style = "distributed" *) reg [31:0] uart_phy_storage = 32'd9895604;
 914 reg uart_phy_re = 1'd0;
 915 wire uart_phy_sink_valid;
 916 reg uart_phy_sink_ready = 1'd0;
 917 wire uart_phy_sink_first;
 918 wire uart_phy_sink_last;
 919 wire [7:0] uart_phy_sink_payload_data;
 920 reg uart_phy_uart_clk_txen = 1'd0;
 921 reg [31:0] uart_phy_phase_accumulator_tx = 32'd0;
 922 reg [7:0] uart_phy_tx_reg = 8'd0;
 923 reg [3:0] uart_phy_tx_bitcount = 4'd0;
 924 reg uart_phy_tx_busy = 1'd0;
 925 reg uart_phy_source_valid = 1'd0;
 926 wire uart_phy_source_ready;
 927 reg uart_phy_source_first = 1'd0;
 928 reg uart_phy_source_last = 1'd0;
 929 reg [7:0] uart_phy_source_payload_data = 8'd0;
 930 reg uart_phy_uart_clk_rxen = 1'd0;
 931 reg [31:0] uart_phy_phase_accumulator_rx = 32'd0;
 932 wire uart_phy_rx;
 933 reg uart_phy_rx_r = 1'd0;
 934 reg [7:0] uart_phy_rx_reg = 8'd0;
 935 reg [3:0] uart_phy_rx_bitcount = 4'd0;
 936 reg uart_phy_rx_busy = 1'd0;
 937 wire rxtx_re;
 938 wire [7:0] rxtx_r;
 939 wire rxtx_we;
 940 wire [7:0] rxtx_w;
 941 wire txfull_status;
 942 wire txfull_we;
 943 wire rxempty_status;
 944 wire rxempty_we;
 945 wire irq;
 946 wire tx_status;
 947 reg tx_pending = 1'd0;
 948 wire tx_trigger;
 949 reg tx_clear = 1'd0;
 950 reg tx_old_trigger = 1'd0;
 951 wire rx_status;
 952 reg rx_pending = 1'd0;
 953 wire rx_trigger;
 954 reg rx_clear = 1'd0;
 955 reg rx_old_trigger = 1'd0;
 956 wire eventmanager_status_re;
 957 wire [1:0] eventmanager_status_r;
 958 wire eventmanager_status_we;
 959 reg [1:0] eventmanager_status_w = 2'd0;
 960 wire eventmanager_pending_re;
 961 wire [1:0] eventmanager_pending_r;
 962 wire eventmanager_pending_we;
 963 reg [1:0] eventmanager_pending_w = 2'd0;
 964 (* ram_style = "distributed" *) reg [1:0] eventmanager_storage = 2'd0;
 965 reg eventmanager_re = 1'd0;
 966 wire txempty_status;
 967 wire txempty_we;
 968 wire rxfull_status;
 969 wire rxfull_we;
 970 wire uart_sink_valid;
 971 wire uart_sink_ready;
 972 wire uart_sink_first;
 973 wire uart_sink_last;
 974 wire [7:0] uart_sink_payload_data;
 975 wire uart_source_valid;
 976 wire uart_source_ready;
 977 wire uart_source_first;
 978 wire uart_source_last;
 979 wire [7:0] uart_source_payload_data;
 980 wire tx_fifo_sink_valid;
 981 wire tx_fifo_sink_ready;
 982 reg tx_fifo_sink_first = 1'd0;
 983 reg tx_fifo_sink_last = 1'd0;
 984 wire [7:0] tx_fifo_sink_payload_data;
 985 wire tx_fifo_source_valid;
 986 wire tx_fifo_source_ready;
 987 wire tx_fifo_source_first;
 988 wire tx_fifo_source_last;
 989 wire [7:0] tx_fifo_source_payload_data;
 990 wire tx_fifo_re;
 991 reg tx_fifo_readable = 1'd0;
 992 wire tx_fifo_syncfifo_we;
 993 wire tx_fifo_syncfifo_writable;
 994 wire tx_fifo_syncfifo_re;
 995 wire tx_fifo_syncfifo_readable;
 996 wire [9:0] tx_fifo_syncfifo_din;
 997 wire [9:0] tx_fifo_syncfifo_dout;
 998 reg [4:0] tx_fifo_level0 = 5'd0;
 999 reg tx_fifo_replace = 1'd0;
1000 reg [3:0] tx_fifo_produce = 4'd0;
1001 reg [3:0] tx_fifo_consume = 4'd0;
1002 reg [3:0] tx_fifo_wrport_adr = 4'd0;
1003 wire [9:0] tx_fifo_wrport_dat_r;
1004 wire tx_fifo_wrport_we;
1005 wire [9:0] tx_fifo_wrport_dat_w;
1006 wire tx_fifo_do_read;
1007 wire [3:0] tx_fifo_rdport_adr;
1008 wire [9:0] tx_fifo_rdport_dat_r;
1009 wire tx_fifo_rdport_re;
1010 wire [4:0] tx_fifo_level1;
1011 wire [7:0] tx_fifo_fifo_in_payload_data;
1012 wire tx_fifo_fifo_in_first;
1013 wire tx_fifo_fifo_in_last;
1014 wire [7:0] tx_fifo_fifo_out_payload_data;
1015 wire tx_fifo_fifo_out_first;
1016 wire tx_fifo_fifo_out_last;
1017 wire rx_fifo_sink_valid;
1018 wire rx_fifo_sink_ready;
1019 wire rx_fifo_sink_first;
1020 wire rx_fifo_sink_last;
1021 wire [7:0] rx_fifo_sink_payload_data;
1022 wire rx_fifo_source_valid;
1023 wire rx_fifo_source_ready;
1024 wire rx_fifo_source_first;
1025 wire rx_fifo_source_last;
1026 wire [7:0] rx_fifo_source_payload_data;
1027 wire rx_fifo_re;
1028 reg rx_fifo_readable = 1'd0;
1029 wire rx_fifo_syncfifo_we;
1030 wire rx_fifo_syncfifo_writable;
1031 wire rx_fifo_syncfifo_re;
1032 wire rx_fifo_syncfifo_readable;
1033 wire [9:0] rx_fifo_syncfifo_din;
1034 wire [9:0] rx_fifo_syncfifo_dout;
1035 reg [4:0] rx_fifo_level0 = 5'd0;
1036 reg rx_fifo_replace = 1'd0;
1037 reg [3:0] rx_fifo_produce = 4'd0;
1038 reg [3:0] rx_fifo_consume = 4'd0;
1039 reg [3:0] rx_fifo_wrport_adr = 4'd0;
1040 wire [9:0] rx_fifo_wrport_dat_r;
1041 wire rx_fifo_wrport_we;
1042 wire [9:0] rx_fifo_wrport_dat_w;
1043 wire rx_fifo_do_read;
1044 wire [3:0] rx_fifo_rdport_adr;
1045 wire [9:0] rx_fifo_rdport_dat_r;
1046 wire rx_fifo_rdport_re;
1047 wire [4:0] rx_fifo_level1;
1048 wire [7:0] rx_fifo_fifo_in_payload_data;
1049 wire rx_fifo_fifo_in_first;
1050 wire rx_fifo_fifo_in_last;
1051 wire [7:0] rx_fifo_fifo_out_payload_data;
1052 wire rx_fifo_fifo_out_first;
1053 wire rx_fifo_fifo_out_last;
1054 reg reset = 1'd0;
1055 (* ram_style = "distributed" *) reg [7:0] gpio0_oe_storage = 8'd0;
1056 reg gpio0_oe_re = 1'd0;
1057 reg [7:0] gpio0_status = 8'd0;
1058 wire gpio0_we;
1059 (* ram_style = "distributed" *) reg [7:0] gpio0_out_storage = 8'd0;
1060 reg gpio0_out_re = 1'd0;
1061 reg [7:0] gpio0_pads_gpio0i = 8'd0;
1062 reg [7:0] gpio0_pads_gpio0o = 8'd0;
1063 reg [7:0] gpio0_pads_gpio0oe = 8'd0;
1064 (* ram_style = "distributed" *) reg [7:0] gpio1_oe_storage = 8'd0;
1065 reg gpio1_oe_re = 1'd0;
1066 reg [7:0] gpio1_status = 8'd0;
1067 wire gpio1_we;
1068 (* ram_style = "distributed" *) reg [7:0] gpio1_out_storage = 8'd0;
1069 reg gpio1_out_re = 1'd0;
1070 reg [7:0] gpio1_pads_gpio1i = 8'd0;
1071 reg [7:0] gpio1_pads_gpio1o = 8'd0;
1072 reg [7:0] gpio1_pads_gpio1oe = 8'd0;
1073 reg [2:0] eint_tmp = 3'd0;
1074 wire [34:0] nc_1;
1075 reg [34:0] dummy = 35'd0;
1076 wire i2c_scl_1;
1077 wire i2c_oe;
1078 wire i2c_sda0;
1079 (* ram_style = "distributed" *) reg [2:0] i2c_storage = 3'd0;
1080 reg i2c_re = 1'd0;
1081 wire i2c_sda1;
1082 wire i2c_status;
1083 wire i2c_we;
1084 reg subfragments_converter0_state = 1'd0;
1085 reg subfragments_converter0_next_state = 1'd0;
1086 reg libresocsim_converter0_counter_subfragments_converter0_next_value = 1'd0;
1087 reg libresocsim_converter0_counter_subfragments_converter0_next_value_ce = 1'd0;
1088 reg subfragments_converter1_state = 1'd0;
1089 reg subfragments_converter1_next_state = 1'd0;
1090 reg libresocsim_converter1_counter_subfragments_converter1_next_value = 1'd0;
1091 reg libresocsim_converter1_counter_subfragments_converter1_next_value_ce = 1'd0;
1092 reg [1:0] subfragments_refresher_state = 2'd0;
1093 reg [1:0] subfragments_refresher_next_state = 2'd0;
1094 reg [2:0] subfragments_bankmachine0_state = 3'd0;
1095 reg [2:0] subfragments_bankmachine0_next_state = 3'd0;
1096 reg [2:0] subfragments_bankmachine1_state = 3'd0;
1097 reg [2:0] subfragments_bankmachine1_next_state = 3'd0;
1098 reg [2:0] subfragments_bankmachine2_state = 3'd0;
1099 reg [2:0] subfragments_bankmachine2_next_state = 3'd0;
1100 reg [2:0] subfragments_bankmachine3_state = 3'd0;
1101 reg [2:0] subfragments_bankmachine3_next_state = 3'd0;
1102 reg [2:0] subfragments_multiplexer_state = 3'd0;
1103 reg [2:0] subfragments_multiplexer_next_state = 3'd0;
1104 wire subfragments_roundrobin0_request;
1105 wire subfragments_roundrobin0_grant;
1106 wire subfragments_roundrobin0_ce;
1107 wire subfragments_roundrobin1_request;
1108 wire subfragments_roundrobin1_grant;
1109 wire subfragments_roundrobin1_ce;
1110 wire subfragments_roundrobin2_request;
1111 wire subfragments_roundrobin2_grant;
1112 wire subfragments_roundrobin2_ce;
1113 wire subfragments_roundrobin3_request;
1114 wire subfragments_roundrobin3_grant;
1115 wire subfragments_roundrobin3_ce;
1116 reg subfragments_locked0 = 1'd0;
1117 reg subfragments_locked1 = 1'd0;
1118 reg subfragments_locked2 = 1'd0;
1119 reg subfragments_locked3 = 1'd0;
1120 reg subfragments_new_master_wdata_ready = 1'd0;
1121 reg subfragments_new_master_rdata_valid0 = 1'd0;
1122 reg subfragments_new_master_rdata_valid1 = 1'd0;
1123 reg subfragments_new_master_rdata_valid2 = 1'd0;
1124 reg subfragments_new_master_rdata_valid3 = 1'd0;
1125 reg subfragments_state = 1'd0;
1126 reg subfragments_next_state = 1'd0;
1127 reg converter_counter_subfragments_next_value = 1'd0;
1128 reg converter_counter_subfragments_next_value_ce = 1'd0;
1129 reg [12:0] libresocsim_libresocsim_adr = 13'd0;
1130 reg libresocsim_libresocsim_we = 1'd0;
1131 reg [7:0] libresocsim_libresocsim_dat_w = 8'd0;
1132 wire [7:0] libresocsim_libresocsim_dat_r;
1133 wire [29:0] libresocsim_libresocsim_wishbone_adr;
1134 wire [31:0] libresocsim_libresocsim_wishbone_dat_w;
1135 reg [31:0] libresocsim_libresocsim_wishbone_dat_r = 32'd0;
1136 wire [3:0] libresocsim_libresocsim_wishbone_sel;
1137 wire libresocsim_libresocsim_wishbone_cyc;
1138 wire libresocsim_libresocsim_wishbone_stb;
1139 reg libresocsim_libresocsim_wishbone_ack = 1'd0;
1140 wire libresocsim_libresocsim_wishbone_we;
1141 wire [2:0] libresocsim_libresocsim_wishbone_cti;
1142 wire [1:0] libresocsim_libresocsim_wishbone_bte;
1143 reg libresocsim_libresocsim_wishbone_err = 1'd0;
1144 wire [29:0] libresocsim_shared_adr;
1145 wire [31:0] libresocsim_shared_dat_w;
1146 reg [31:0] libresocsim_shared_dat_r = 32'd0;
1147 wire [3:0] libresocsim_shared_sel;
1148 wire libresocsim_shared_cyc;
1149 wire libresocsim_shared_stb;
1150 reg libresocsim_shared_ack = 1'd0;
1151 wire libresocsim_shared_we;
1152 wire [2:0] libresocsim_shared_cti;
1153 wire [1:0] libresocsim_shared_bte;
1154 wire libresocsim_shared_err;
1155 wire [2:0] libresocsim_request;
1156 reg [1:0] libresocsim_grant = 2'd0;
1157 reg [9:0] libresocsim_slave_sel = 10'd0;
1158 reg [9:0] libresocsim_slave_sel_r = 10'd0;
1159 reg libresocsim_error = 1'd0;
1160 wire libresocsim_wait;
1161 wire libresocsim_done;
1162 reg [19:0] libresocsim_count = 20'd1000000;
1163 wire [12:0] libresocsim_interface0_bank_bus_adr;
1164 wire libresocsim_interface0_bank_bus_we;
1165 wire [7:0] libresocsim_interface0_bank_bus_dat_w;
1166 reg [7:0] libresocsim_interface0_bank_bus_dat_r = 8'd0;
1167 wire libresocsim_csrbank0_reset0_re;
1168 wire libresocsim_csrbank0_reset0_r;
1169 wire libresocsim_csrbank0_reset0_we;
1170 wire libresocsim_csrbank0_reset0_w;
1171 wire libresocsim_csrbank0_scratch3_re;
1172 wire [7:0] libresocsim_csrbank0_scratch3_r;
1173 wire libresocsim_csrbank0_scratch3_we;
1174 wire [7:0] libresocsim_csrbank0_scratch3_w;
1175 wire libresocsim_csrbank0_scratch2_re;
1176 wire [7:0] libresocsim_csrbank0_scratch2_r;
1177 wire libresocsim_csrbank0_scratch2_we;
1178 wire [7:0] libresocsim_csrbank0_scratch2_w;
1179 wire libresocsim_csrbank0_scratch1_re;
1180 wire [7:0] libresocsim_csrbank0_scratch1_r;
1181 wire libresocsim_csrbank0_scratch1_we;
1182 wire [7:0] libresocsim_csrbank0_scratch1_w;
1183 wire libresocsim_csrbank0_scratch0_re;
1184 wire [7:0] libresocsim_csrbank0_scratch0_r;
1185 wire libresocsim_csrbank0_scratch0_we;
1186 wire [7:0] libresocsim_csrbank0_scratch0_w;
1187 wire libresocsim_csrbank0_bus_errors3_re;
1188 wire [7:0] libresocsim_csrbank0_bus_errors3_r;
1189 wire libresocsim_csrbank0_bus_errors3_we;
1190 wire [7:0] libresocsim_csrbank0_bus_errors3_w;
1191 wire libresocsim_csrbank0_bus_errors2_re;
1192 wire [7:0] libresocsim_csrbank0_bus_errors2_r;
1193 wire libresocsim_csrbank0_bus_errors2_we;
1194 wire [7:0] libresocsim_csrbank0_bus_errors2_w;
1195 wire libresocsim_csrbank0_bus_errors1_re;
1196 wire [7:0] libresocsim_csrbank0_bus_errors1_r;
1197 wire libresocsim_csrbank0_bus_errors1_we;
1198 wire [7:0] libresocsim_csrbank0_bus_errors1_w;
1199 wire libresocsim_csrbank0_bus_errors0_re;
1200 wire [7:0] libresocsim_csrbank0_bus_errors0_r;
1201 wire libresocsim_csrbank0_bus_errors0_we;
1202 wire [7:0] libresocsim_csrbank0_bus_errors0_w;
1203 wire libresocsim_csrbank0_sel;
1204 wire [12:0] libresocsim_interface1_bank_bus_adr;
1205 wire libresocsim_interface1_bank_bus_we;
1206 wire [7:0] libresocsim_interface1_bank_bus_dat_w;
1207 reg [7:0] libresocsim_interface1_bank_bus_dat_r = 8'd0;
1208 wire libresocsim_csrbank1_oe0_re;
1209 wire [7:0] libresocsim_csrbank1_oe0_r;
1210 wire libresocsim_csrbank1_oe0_we;
1211 wire [7:0] libresocsim_csrbank1_oe0_w;
1212 wire libresocsim_csrbank1_in_re;
1213 wire [7:0] libresocsim_csrbank1_in_r;
1214 wire libresocsim_csrbank1_in_we;
1215 wire [7:0] libresocsim_csrbank1_in_w;
1216 wire libresocsim_csrbank1_out0_re;
1217 wire [7:0] libresocsim_csrbank1_out0_r;
1218 wire libresocsim_csrbank1_out0_we;
1219 wire [7:0] libresocsim_csrbank1_out0_w;
1220 wire libresocsim_csrbank1_sel;
1221 wire [12:0] libresocsim_interface2_bank_bus_adr;
1222 wire libresocsim_interface2_bank_bus_we;
1223 wire [7:0] libresocsim_interface2_bank_bus_dat_w;
1224 reg [7:0] libresocsim_interface2_bank_bus_dat_r = 8'd0;
1225 wire libresocsim_csrbank2_oe0_re;
1226 wire [7:0] libresocsim_csrbank2_oe0_r;
1227 wire libresocsim_csrbank2_oe0_we;
1228 wire [7:0] libresocsim_csrbank2_oe0_w;
1229 wire libresocsim_csrbank2_in_re;
1230 wire [7:0] libresocsim_csrbank2_in_r;
1231 wire libresocsim_csrbank2_in_we;
1232 wire [7:0] libresocsim_csrbank2_in_w;
1233 wire libresocsim_csrbank2_out0_re;
1234 wire [7:0] libresocsim_csrbank2_out0_r;
1235 wire libresocsim_csrbank2_out0_we;
1236 wire [7:0] libresocsim_csrbank2_out0_w;
1237 wire libresocsim_csrbank2_sel;
1238 wire [12:0] libresocsim_interface3_bank_bus_adr;
1239 wire libresocsim_interface3_bank_bus_we;
1240 wire [7:0] libresocsim_interface3_bank_bus_dat_w;
1241 reg [7:0] libresocsim_interface3_bank_bus_dat_r = 8'd0;
1242 wire libresocsim_csrbank3_w0_re;
1243 wire [2:0] libresocsim_csrbank3_w0_r;
1244 wire libresocsim_csrbank3_w0_we;
1245 wire [2:0] libresocsim_csrbank3_w0_w;
1246 wire libresocsim_csrbank3_r_re;
1247 wire libresocsim_csrbank3_r_r;
1248 wire libresocsim_csrbank3_r_we;
1249 wire libresocsim_csrbank3_r_w;
1250 wire libresocsim_csrbank3_sel;
1251 wire [12:0] libresocsim_interface4_bank_bus_adr;
1252 wire libresocsim_interface4_bank_bus_we;
1253 wire [7:0] libresocsim_interface4_bank_bus_dat_w;
1254 reg [7:0] libresocsim_interface4_bank_bus_dat_r = 8'd0;
1255 wire libresocsim_csrbank4_dfii_control0_re;
1256 wire [3:0] libresocsim_csrbank4_dfii_control0_r;
1257 wire libresocsim_csrbank4_dfii_control0_we;
1258 wire [3:0] libresocsim_csrbank4_dfii_control0_w;
1259 wire libresocsim_csrbank4_dfii_pi0_command0_re;
1260 wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_r;
1261 wire libresocsim_csrbank4_dfii_pi0_command0_we;
1262 wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_w;
1263 wire libresocsim_csrbank4_dfii_pi0_address1_re;
1264 wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_r;
1265 wire libresocsim_csrbank4_dfii_pi0_address1_we;
1266 wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_w;
1267 wire libresocsim_csrbank4_dfii_pi0_address0_re;
1268 wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_r;
1269 wire libresocsim_csrbank4_dfii_pi0_address0_we;
1270 wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_w;
1271 wire libresocsim_csrbank4_dfii_pi0_baddress0_re;
1272 wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_r;
1273 wire libresocsim_csrbank4_dfii_pi0_baddress0_we;
1274 wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_w;
1275 wire libresocsim_csrbank4_dfii_pi0_wrdata1_re;
1276 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_r;
1277 wire libresocsim_csrbank4_dfii_pi0_wrdata1_we;
1278 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_w;
1279 wire libresocsim_csrbank4_dfii_pi0_wrdata0_re;
1280 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_r;
1281 wire libresocsim_csrbank4_dfii_pi0_wrdata0_we;
1282 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_w;
1283 wire libresocsim_csrbank4_dfii_pi0_rddata1_re;
1284 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_r;
1285 wire libresocsim_csrbank4_dfii_pi0_rddata1_we;
1286 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_w;
1287 wire libresocsim_csrbank4_dfii_pi0_rddata0_re;
1288 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_r;
1289 wire libresocsim_csrbank4_dfii_pi0_rddata0_we;
1290 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_w;
1291 wire libresocsim_csrbank4_sel;
1292 wire [12:0] libresocsim_interface5_bank_bus_adr;
1293 wire libresocsim_interface5_bank_bus_we;
1294 wire [7:0] libresocsim_interface5_bank_bus_dat_w;
1295 reg [7:0] libresocsim_interface5_bank_bus_dat_r = 8'd0;
1296 wire libresocsim_csrbank5_load3_re;
1297 wire [7:0] libresocsim_csrbank5_load3_r;
1298 wire libresocsim_csrbank5_load3_we;
1299 wire [7:0] libresocsim_csrbank5_load3_w;
1300 wire libresocsim_csrbank5_load2_re;
1301 wire [7:0] libresocsim_csrbank5_load2_r;
1302 wire libresocsim_csrbank5_load2_we;
1303 wire [7:0] libresocsim_csrbank5_load2_w;
1304 wire libresocsim_csrbank5_load1_re;
1305 wire [7:0] libresocsim_csrbank5_load1_r;
1306 wire libresocsim_csrbank5_load1_we;
1307 wire [7:0] libresocsim_csrbank5_load1_w;
1308 wire libresocsim_csrbank5_load0_re;
1309 wire [7:0] libresocsim_csrbank5_load0_r;
1310 wire libresocsim_csrbank5_load0_we;
1311 wire [7:0] libresocsim_csrbank5_load0_w;
1312 wire libresocsim_csrbank5_reload3_re;
1313 wire [7:0] libresocsim_csrbank5_reload3_r;
1314 wire libresocsim_csrbank5_reload3_we;
1315 wire [7:0] libresocsim_csrbank5_reload3_w;
1316 wire libresocsim_csrbank5_reload2_re;
1317 wire [7:0] libresocsim_csrbank5_reload2_r;
1318 wire libresocsim_csrbank5_reload2_we;
1319 wire [7:0] libresocsim_csrbank5_reload2_w;
1320 wire libresocsim_csrbank5_reload1_re;
1321 wire [7:0] libresocsim_csrbank5_reload1_r;
1322 wire libresocsim_csrbank5_reload1_we;
1323 wire [7:0] libresocsim_csrbank5_reload1_w;
1324 wire libresocsim_csrbank5_reload0_re;
1325 wire [7:0] libresocsim_csrbank5_reload0_r;
1326 wire libresocsim_csrbank5_reload0_we;
1327 wire [7:0] libresocsim_csrbank5_reload0_w;
1328 wire libresocsim_csrbank5_en0_re;
1329 wire libresocsim_csrbank5_en0_r;
1330 wire libresocsim_csrbank5_en0_we;
1331 wire libresocsim_csrbank5_en0_w;
1332 wire libresocsim_csrbank5_update_value0_re;
1333 wire libresocsim_csrbank5_update_value0_r;
1334 wire libresocsim_csrbank5_update_value0_we;
1335 wire libresocsim_csrbank5_update_value0_w;
1336 wire libresocsim_csrbank5_value3_re;
1337 wire [7:0] libresocsim_csrbank5_value3_r;
1338 wire libresocsim_csrbank5_value3_we;
1339 wire [7:0] libresocsim_csrbank5_value3_w;
1340 wire libresocsim_csrbank5_value2_re;
1341 wire [7:0] libresocsim_csrbank5_value2_r;
1342 wire libresocsim_csrbank5_value2_we;
1343 wire [7:0] libresocsim_csrbank5_value2_w;
1344 wire libresocsim_csrbank5_value1_re;
1345 wire [7:0] libresocsim_csrbank5_value1_r;
1346 wire libresocsim_csrbank5_value1_we;
1347 wire [7:0] libresocsim_csrbank5_value1_w;
1348 wire libresocsim_csrbank5_value0_re;
1349 wire [7:0] libresocsim_csrbank5_value0_r;
1350 wire libresocsim_csrbank5_value0_we;
1351 wire [7:0] libresocsim_csrbank5_value0_w;
1352 wire libresocsim_csrbank5_ev_enable0_re;
1353 wire libresocsim_csrbank5_ev_enable0_r;
1354 wire libresocsim_csrbank5_ev_enable0_we;
1355 wire libresocsim_csrbank5_ev_enable0_w;
1356 wire libresocsim_csrbank5_sel;
1357 wire [12:0] libresocsim_interface6_bank_bus_adr;
1358 wire libresocsim_interface6_bank_bus_we;
1359 wire [7:0] libresocsim_interface6_bank_bus_dat_w;
1360 reg [7:0] libresocsim_interface6_bank_bus_dat_r = 8'd0;
1361 wire libresocsim_csrbank6_txfull_re;
1362 wire libresocsim_csrbank6_txfull_r;
1363 wire libresocsim_csrbank6_txfull_we;
1364 wire libresocsim_csrbank6_txfull_w;
1365 wire libresocsim_csrbank6_rxempty_re;
1366 wire libresocsim_csrbank6_rxempty_r;
1367 wire libresocsim_csrbank6_rxempty_we;
1368 wire libresocsim_csrbank6_rxempty_w;
1369 wire libresocsim_csrbank6_ev_enable0_re;
1370 wire [1:0] libresocsim_csrbank6_ev_enable0_r;
1371 wire libresocsim_csrbank6_ev_enable0_we;
1372 wire [1:0] libresocsim_csrbank6_ev_enable0_w;
1373 wire libresocsim_csrbank6_txempty_re;
1374 wire libresocsim_csrbank6_txempty_r;
1375 wire libresocsim_csrbank6_txempty_we;
1376 wire libresocsim_csrbank6_txempty_w;
1377 wire libresocsim_csrbank6_rxfull_re;
1378 wire libresocsim_csrbank6_rxfull_r;
1379 wire libresocsim_csrbank6_rxfull_we;
1380 wire libresocsim_csrbank6_rxfull_w;
1381 wire libresocsim_csrbank6_sel;
1382 wire [12:0] libresocsim_interface7_bank_bus_adr;
1383 wire libresocsim_interface7_bank_bus_we;
1384 wire [7:0] libresocsim_interface7_bank_bus_dat_w;
1385 reg [7:0] libresocsim_interface7_bank_bus_dat_r = 8'd0;
1386 wire libresocsim_csrbank7_tuning_word3_re;
1387 wire [7:0] libresocsim_csrbank7_tuning_word3_r;
1388 wire libresocsim_csrbank7_tuning_word3_we;
1389 wire [7:0] libresocsim_csrbank7_tuning_word3_w;
1390 wire libresocsim_csrbank7_tuning_word2_re;
1391 wire [7:0] libresocsim_csrbank7_tuning_word2_r;
1392 wire libresocsim_csrbank7_tuning_word2_we;
1393 wire [7:0] libresocsim_csrbank7_tuning_word2_w;
1394 wire libresocsim_csrbank7_tuning_word1_re;
1395 wire [7:0] libresocsim_csrbank7_tuning_word1_r;
1396 wire libresocsim_csrbank7_tuning_word1_we;
1397 wire [7:0] libresocsim_csrbank7_tuning_word1_w;
1398 wire libresocsim_csrbank7_tuning_word0_re;
1399 wire [7:0] libresocsim_csrbank7_tuning_word0_r;
1400 wire libresocsim_csrbank7_tuning_word0_we;
1401 wire [7:0] libresocsim_csrbank7_tuning_word0_w;
1402 wire libresocsim_csrbank7_sel;
1403 wire [12:0] libresocsim_csr_interconnect_adr;
1404 wire libresocsim_csr_interconnect_we;
1405 wire [7:0] libresocsim_csr_interconnect_dat_w;
1406 wire [7:0] libresocsim_csr_interconnect_dat_r;
1407 reg [1:0] libresocsim_state = 2'd0;
1408 reg [1:0] libresocsim_next_state = 2'd0;
1409 reg [7:0] libresocsim_libresocsim_dat_w_libresocsim_next_value0 = 8'd0;
1410 reg libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 = 1'd0;
1411 reg [12:0] libresocsim_libresocsim_adr_libresocsim_next_value1 = 13'd0;
1412 reg libresocsim_libresocsim_adr_libresocsim_next_value_ce1 = 1'd0;
1413 reg libresocsim_libresocsim_we_libresocsim_next_value2 = 1'd0;
1414 reg libresocsim_libresocsim_we_libresocsim_next_value_ce2 = 1'd0;
1415 reg rhs_array_muxed0 = 1'd0;
1416 reg [12:0] rhs_array_muxed1 = 13'd0;
1417 reg [1:0] rhs_array_muxed2 = 2'd0;
1418 reg rhs_array_muxed3 = 1'd0;
1419 reg rhs_array_muxed4 = 1'd0;
1420 reg rhs_array_muxed5 = 1'd0;
1421 reg t_array_muxed0 = 1'd0;
1422 reg t_array_muxed1 = 1'd0;
1423 reg t_array_muxed2 = 1'd0;
1424 reg rhs_array_muxed6 = 1'd0;
1425 reg [12:0] rhs_array_muxed7 = 13'd0;
1426 reg [1:0] rhs_array_muxed8 = 2'd0;
1427 reg rhs_array_muxed9 = 1'd0;
1428 reg rhs_array_muxed10 = 1'd0;
1429 reg rhs_array_muxed11 = 1'd0;
1430 reg t_array_muxed3 = 1'd0;
1431 reg t_array_muxed4 = 1'd0;
1432 reg t_array_muxed5 = 1'd0;
1433 reg [21:0] rhs_array_muxed12 = 22'd0;
1434 reg rhs_array_muxed13 = 1'd0;
1435 reg rhs_array_muxed14 = 1'd0;
1436 reg [21:0] rhs_array_muxed15 = 22'd0;
1437 reg rhs_array_muxed16 = 1'd0;
1438 reg rhs_array_muxed17 = 1'd0;
1439 reg [21:0] rhs_array_muxed18 = 22'd0;
1440 reg rhs_array_muxed19 = 1'd0;
1441 reg rhs_array_muxed20 = 1'd0;
1442 reg [21:0] rhs_array_muxed21 = 22'd0;
1443 reg rhs_array_muxed22 = 1'd0;
1444 reg rhs_array_muxed23 = 1'd0;
1445 reg [29:0] rhs_array_muxed24 = 30'd0;
1446 reg [31:0] rhs_array_muxed25 = 32'd0;
1447 reg [3:0] rhs_array_muxed26 = 4'd0;
1448 reg rhs_array_muxed27 = 1'd0;
1449 reg rhs_array_muxed28 = 1'd0;
1450 reg rhs_array_muxed29 = 1'd0;
1451 reg [2:0] rhs_array_muxed30 = 3'd0;
1452 reg [1:0] rhs_array_muxed31 = 2'd0;
1453 reg [1:0] array_muxed0 = 2'd0;
1454 reg [12:0] array_muxed1 = 13'd0;
1455 reg array_muxed2 = 1'd0;
1456 reg array_muxed3 = 1'd0;
1457 reg array_muxed4 = 1'd0;
1458 reg array_muxed5 = 1'd0;
1459 reg array_muxed6 = 1'd0;
1460 wire sdrio_clk;
1461 wire sdrio_clk_1;
1462 wire sdrio_clk_2;
1463 wire sdrio_clk_3;
1464 wire sdrio_clk_4;
1465 wire sdrio_clk_5;
1466 wire sdrio_clk_6;
1467 wire sdrio_clk_7;
1468 wire sdrio_clk_8;
1469 wire sdrio_clk_9;
1470 wire sdrio_clk_10;
1471 wire sdrio_clk_11;
1472 wire sdrio_clk_12;
1473 wire sdrio_clk_13;
1474 wire sdrio_clk_14;
1475 wire sdrio_clk_15;
1476 wire sdrio_clk_16;
1477 wire sdrio_clk_17;
1478 wire sdrio_clk_18;
1479 wire sdrio_clk_19;
1480 wire sdrio_clk_20;
1481 wire sdrio_clk_21;
1482 wire sdrio_clk_22;
1483 wire sdrio_clk_23;
1484 wire sdrio_clk_24;
1485 wire sdrio_clk_25;
1486 wire sdrio_clk_26;
1487 wire sdrio_clk_27;
1488 wire sdrio_clk_28;
1489 wire sdrio_clk_29;
1490 wire sdrio_clk_30;
1491 wire sdrio_clk_31;
1492 wire sdrio_clk_32;
1493 wire sdrio_clk_33;
1494 wire sdrio_clk_34;
1495 wire sdrio_clk_35;
1496 wire sdrio_clk_36;
1497 wire sdrio_clk_37;
1498 wire sdrio_clk_38;
1499 wire sdrio_clk_39;
1500 wire sdrio_clk_40;
1501 wire sdrio_clk_41;
1502 wire sdrio_clk_42;
1503 wire sdrio_clk_43;
1504 wire sdrio_clk_44;
1505 wire sdrio_clk_45;
1506 wire sdrio_clk_46;
1507 wire sdrio_clk_47;
1508 wire sdrio_clk_48;
1509 wire sdrio_clk_49;
1510 wire sdrio_clk_50;
1511 wire sdrio_clk_51;
1512 wire sdrio_clk_52;
1513 wire sdrio_clk_53;
1514 wire sdrio_clk_54;
1515 wire sdrio_clk_55;
1516 wire sdrio_clk_56;
1517 wire sdrio_clk_57;
1518 wire sdrio_clk_58;
1519 wire sdrio_clk_59;
1520 wire sdrio_clk_60;
1521 wire sdrio_clk_61;
1522 wire sdrio_clk_62;
1523 wire sdrio_clk_63;
1524 wire sdrio_clk_64;
1525 wire sdrio_clk_65;
1526 wire sdrio_clk_66;
1527 wire sdrio_clk_67;
1528 wire sdrio_clk_68;
1529 wire sdrio_clk_69;
1530 wire sdrio_clk_70;
1531 (* no_retiming = "true" *) reg regs0 = 1'd0;
1532 (* no_retiming = "true" *) reg regs1 = 1'd0;
1533 wire sdrio_clk_71;
1534 wire sdrio_clk_72;
1535 wire sdrio_clk_73;
1536 wire sdrio_clk_74;
1537 wire sdrio_clk_75;
1538 wire sdrio_clk_76;
1539 wire sdrio_clk_77;
1540 wire sdrio_clk_78;
1541 wire sdrio_clk_79;
1542 wire sdrio_clk_80;
1543 wire sdrio_clk_81;
1544 wire sdrio_clk_82;
1545 wire sdrio_clk_83;
1546 wire sdrio_clk_84;
1547 wire sdrio_clk_85;
1548 wire sdrio_clk_86;
1549 wire sdrio_clk_87;
1550 wire sdrio_clk_88;
1551 wire sdrio_clk_89;
1552 wire sdrio_clk_90;
1553 wire sdrio_clk_91;
1554 wire sdrio_clk_92;
1555 wire sdrio_clk_93;
1556 wire sdrio_clk_94;
1557 wire sdrio_clk_95;
1558 wire sdrio_clk_96;
1559 wire sdrio_clk_97;
1560 wire sdrio_clk_98;
1561 wire sdrio_clk_99;
1562 wire sdrio_clk_100;
1563 wire sdrio_clk_101;
1564 wire sdrio_clk_102;
1565 wire sdrio_clk_103;
1566 wire sdrio_clk_104;
1567 wire sdrio_clk_105;
1568 wire sdrio_clk_106;
1569 wire sdrio_clk_107;
1570 wire sdrio_clk_108;
1571 wire sdrio_clk_109;
1572 wire sdrio_clk_110;
1573 wire sdrio_clk_111;
1574 wire sdrio_clk_112;
1575 wire sdrio_clk_113;
1576 wire sdrio_clk_114;
1577 wire sdrio_clk_115;
1578 wire sdrio_clk_116;
1579 wire sdrio_clk_117;
1580 wire sdrio_clk_118;
1581
1582 assign libresocsim_libresoc_reset = libresocsim_reset;
1583 assign libresocsim_libresoc_clk_sel = sys_clksel_i;
1584 assign sys_pll_testout_o = libresocsim_libresoc_pll_18_o;
1585 assign sys_pll_vco_o = libresocsim_libresoc_pll_ana_o;
1586 always @(*) begin
1587         eint_tmp <= 3'd0;
1588         eint_tmp[0] <= libresocsim_libresoc_constraintmanager_eint_0;
1589         eint_tmp[1] <= libresocsim_libresoc_constraintmanager_eint_1;
1590         eint_tmp[2] <= libresocsim_libresoc_constraintmanager_eint_2;
1591 end
1592 assign libresocsim_libresoc_jtag_tck = jtag_tck;
1593 assign libresocsim_libresoc_jtag_tms = jtag_tms;
1594 assign libresocsim_libresoc_jtag_tdi = jtag_tdi;
1595 assign jtag_tdo = libresocsim_libresoc_jtag_tdo;
1596 assign nc_1 = nc;
1597 assign libresocsim_bus_error = libresocsim_error;
1598 always @(*) begin
1599         libresocsim_libresoc_interrupt <= 16'd0;
1600         libresocsim_libresoc_interrupt[13] <= eint_tmp[0];
1601         libresocsim_libresoc_interrupt[14] <= eint_tmp[1];
1602         libresocsim_libresoc_interrupt[15] <= eint_tmp[2];
1603         libresocsim_libresoc_interrupt[0] <= libresocsim_irq;
1604         libresocsim_libresoc_interrupt[1] <= irq;
1605 end
1606 assign libresocsim_converter0_reset = (~libresocsim_libresoc_ibus_cyc);
1607 always @(*) begin
1608         libresocsim_interface0_converted_interface_dat_w <= 32'd0;
1609         case (libresocsim_converter0_counter)
1610                 1'd0: begin
1611                         libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:0];
1612                 end
1613                 1'd1: begin
1614                         libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:32];
1615                 end
1616         endcase
1617 end
1618 assign libresocsim_libresoc_ibus_dat_r = {libresocsim_interface0_converted_interface_dat_r, libresocsim_converter0_dat_r[63:32]};
1619 always @(*) begin
1620         libresocsim_interface0_converted_interface_cyc <= 1'd0;
1621         subfragments_converter0_next_state <= 1'd0;
1622         libresocsim_interface0_converted_interface_stb <= 1'd0;
1623         libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0;
1624         libresocsim_libresoc_ibus_ack <= 1'd0;
1625         libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0;
1626         libresocsim_interface0_converted_interface_we <= 1'd0;
1627         libresocsim_converter0_skip <= 1'd0;
1628         libresocsim_interface0_converted_interface_adr <= 30'd0;
1629         libresocsim_interface0_converted_interface_sel <= 4'd0;
1630         subfragments_converter0_next_state <= subfragments_converter0_state;
1631         case (subfragments_converter0_state)
1632                 1'd1: begin
1633                         libresocsim_interface0_converted_interface_adr <= {libresocsim_libresoc_ibus_adr, libresocsim_converter0_counter};
1634                         case (libresocsim_converter0_counter)
1635                                 1'd0: begin
1636                                         libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:0];
1637                                 end
1638                                 1'd1: begin
1639                                         libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:4];
1640                                 end
1641                         endcase
1642                         if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin
1643                                 libresocsim_converter0_skip <= (libresocsim_interface0_converted_interface_sel == 1'd0);
1644                                 libresocsim_interface0_converted_interface_we <= libresocsim_libresoc_ibus_we;
1645                                 libresocsim_interface0_converted_interface_cyc <= (~libresocsim_converter0_skip);
1646                                 libresocsim_interface0_converted_interface_stb <= (~libresocsim_converter0_skip);
1647                                 if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin
1648                                         libresocsim_converter0_counter_subfragments_converter0_next_value <= (libresocsim_converter0_counter + 1'd1);
1649                                         libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1;
1650                                         if ((libresocsim_converter0_counter == 1'd1)) begin
1651                                                 libresocsim_libresoc_ibus_ack <= 1'd1;
1652                                                 subfragments_converter0_next_state <= 1'd0;
1653                                         end
1654                                 end
1655                         end
1656                 end
1657                 default: begin
1658                         libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0;
1659                         libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1;
1660                         if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin
1661                                 subfragments_converter0_next_state <= 1'd1;
1662                         end
1663                 end
1664         endcase
1665 end
1666 assign libresocsim_converter1_reset = (~libresocsim_libresoc_dbus_cyc);
1667 always @(*) begin
1668         libresocsim_interface1_converted_interface_dat_w <= 32'd0;
1669         case (libresocsim_converter1_counter)
1670                 1'd0: begin
1671                         libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:0];
1672                 end
1673                 1'd1: begin
1674                         libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:32];
1675                 end
1676         endcase
1677 end
1678 assign libresocsim_libresoc_dbus_dat_r = {libresocsim_interface1_converted_interface_dat_r, libresocsim_converter1_dat_r[63:32]};
1679 always @(*) begin
1680         libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0;
1681         libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0;
1682         libresocsim_converter1_skip <= 1'd0;
1683         libresocsim_libresoc_dbus_ack <= 1'd0;
1684         libresocsim_interface1_converted_interface_adr <= 30'd0;
1685         libresocsim_interface1_converted_interface_sel <= 4'd0;
1686         libresocsim_interface1_converted_interface_cyc <= 1'd0;
1687         libresocsim_interface1_converted_interface_stb <= 1'd0;
1688         libresocsim_interface1_converted_interface_we <= 1'd0;
1689         subfragments_converter1_next_state <= 1'd0;
1690         subfragments_converter1_next_state <= subfragments_converter1_state;
1691         case (subfragments_converter1_state)
1692                 1'd1: begin
1693                         libresocsim_interface1_converted_interface_adr <= {libresocsim_libresoc_dbus_adr, libresocsim_converter1_counter};
1694                         case (libresocsim_converter1_counter)
1695                                 1'd0: begin
1696                                         libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:0];
1697                                 end
1698                                 1'd1: begin
1699                                         libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:4];
1700                                 end
1701                         endcase
1702                         if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin
1703                                 libresocsim_converter1_skip <= (libresocsim_interface1_converted_interface_sel == 1'd0);
1704                                 libresocsim_interface1_converted_interface_we <= libresocsim_libresoc_dbus_we;
1705                                 libresocsim_interface1_converted_interface_cyc <= (~libresocsim_converter1_skip);
1706                                 libresocsim_interface1_converted_interface_stb <= (~libresocsim_converter1_skip);
1707                                 if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin
1708                                         libresocsim_converter1_counter_subfragments_converter1_next_value <= (libresocsim_converter1_counter + 1'd1);
1709                                         libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1;
1710                                         if ((libresocsim_converter1_counter == 1'd1)) begin
1711                                                 libresocsim_libresoc_dbus_ack <= 1'd1;
1712                                                 subfragments_converter1_next_state <= 1'd0;
1713                                         end
1714                                 end
1715                         end
1716                 end
1717                 default: begin
1718                         libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0;
1719                         libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1;
1720                         if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin
1721                                 subfragments_converter1_next_state <= 1'd1;
1722                         end
1723                 end
1724         endcase
1725 end
1726 assign libresocsim_libresoc_interface0_cyc = interface0_converted_interface_cyc;
1727 assign libresocsim_libresoc_interface0_stb = interface0_converted_interface_stb;
1728 assign interface0_converted_interface_ack = libresocsim_libresoc_interface0_ack;
1729 assign libresocsim_libresoc_interface0_we = interface0_converted_interface_we;
1730 assign libresocsim_libresoc_interface0_cti = interface0_converted_interface_cti;
1731 assign libresocsim_libresoc_interface0_bte = interface0_converted_interface_bte;
1732 assign interface0_converted_interface_err = libresocsim_libresoc_interface0_err;
1733 always @(*) begin
1734         libresocsim_libresoc_interface0_adr <= 29'd0;
1735         libresocsim_libresoc_interface0_dat_w <= 64'd0;
1736         libresocsim_libresoc_interface0_sel <= 8'd0;
1737         interface0_converted_interface_dat_r <= 32'd0;
1738         case (interface0_converted_interface_adr[0])
1739                 1'd0: begin
1740                         libresocsim_libresoc_interface0_adr <= interface0_converted_interface_adr[29:1];
1741                         libresocsim_libresoc_interface0_sel[3:0] <= 4'd15;
1742                         libresocsim_libresoc_interface0_dat_w[31:0] <= interface0_converted_interface_dat_w;
1743                         interface0_converted_interface_dat_r <= libresocsim_libresoc_interface0_dat_r[31:0];
1744                 end
1745                 1'd1: begin
1746                         libresocsim_libresoc_interface0_adr <= interface0_converted_interface_adr[29:1];
1747                         libresocsim_libresoc_interface0_sel[7:4] <= 4'd15;
1748                         libresocsim_libresoc_interface0_dat_w[63:32] <= interface0_converted_interface_dat_w;
1749                         interface0_converted_interface_dat_r <= libresocsim_libresoc_interface0_dat_r[63:32];
1750                 end
1751         endcase
1752 end
1753 assign libresocsim_libresoc_interface1_cyc = interface1_converted_interface_cyc;
1754 assign libresocsim_libresoc_interface1_stb = interface1_converted_interface_stb;
1755 assign interface1_converted_interface_ack = libresocsim_libresoc_interface1_ack;
1756 assign libresocsim_libresoc_interface1_we = interface1_converted_interface_we;
1757 assign libresocsim_libresoc_interface1_cti = interface1_converted_interface_cti;
1758 assign libresocsim_libresoc_interface1_bte = interface1_converted_interface_bte;
1759 assign interface1_converted_interface_err = libresocsim_libresoc_interface1_err;
1760 always @(*) begin
1761         libresocsim_libresoc_interface1_dat_w <= 64'd0;
1762         libresocsim_libresoc_interface1_sel <= 8'd0;
1763         interface1_converted_interface_dat_r <= 32'd0;
1764         libresocsim_libresoc_interface1_adr <= 29'd0;
1765         case (interface1_converted_interface_adr[0])
1766                 1'd0: begin
1767                         libresocsim_libresoc_interface1_adr <= interface1_converted_interface_adr[29:1];
1768                         libresocsim_libresoc_interface1_sel[3:0] <= 4'd15;
1769                         libresocsim_libresoc_interface1_dat_w[31:0] <= interface1_converted_interface_dat_w;
1770                         interface1_converted_interface_dat_r <= libresocsim_libresoc_interface1_dat_r[31:0];
1771                 end
1772                 1'd1: begin
1773                         libresocsim_libresoc_interface1_adr <= interface1_converted_interface_adr[29:1];
1774                         libresocsim_libresoc_interface1_sel[7:4] <= 4'd15;
1775                         libresocsim_libresoc_interface1_dat_w[63:32] <= interface1_converted_interface_dat_w;
1776                         interface1_converted_interface_dat_r <= libresocsim_libresoc_interface1_dat_r[63:32];
1777                 end
1778         endcase
1779 end
1780 assign libresocsim_libresoc_interface2_cyc = interface2_converted_interface_cyc;
1781 assign libresocsim_libresoc_interface2_stb = interface2_converted_interface_stb;
1782 assign interface2_converted_interface_ack = libresocsim_libresoc_interface2_ack;
1783 assign libresocsim_libresoc_interface2_we = interface2_converted_interface_we;
1784 assign libresocsim_libresoc_interface2_cti = interface2_converted_interface_cti;
1785 assign libresocsim_libresoc_interface2_bte = interface2_converted_interface_bte;
1786 assign interface2_converted_interface_err = libresocsim_libresoc_interface2_err;
1787 always @(*) begin
1788         interface2_converted_interface_dat_r <= 32'd0;
1789         libresocsim_libresoc_interface2_sel <= 8'd0;
1790         libresocsim_libresoc_interface2_adr <= 29'd0;
1791         libresocsim_libresoc_interface2_dat_w <= 64'd0;
1792         case (interface2_converted_interface_adr[0])
1793                 1'd0: begin
1794                         libresocsim_libresoc_interface2_adr <= interface2_converted_interface_adr[29:1];
1795                         libresocsim_libresoc_interface2_sel[3:0] <= 4'd15;
1796                         libresocsim_libresoc_interface2_dat_w[31:0] <= interface2_converted_interface_dat_w;
1797                         interface2_converted_interface_dat_r <= libresocsim_libresoc_interface2_dat_r[31:0];
1798                 end
1799                 1'd1: begin
1800                         libresocsim_libresoc_interface2_adr <= interface2_converted_interface_adr[29:1];
1801                         libresocsim_libresoc_interface2_sel[7:4] <= 4'd15;
1802                         libresocsim_libresoc_interface2_dat_w[63:32] <= interface2_converted_interface_dat_w;
1803                         interface2_converted_interface_dat_r <= libresocsim_libresoc_interface2_dat_r[63:32];
1804                 end
1805         endcase
1806 end
1807 assign libresocsim_libresoc_interface3_cyc = interface3_converted_interface_cyc;
1808 assign libresocsim_libresoc_interface3_stb = interface3_converted_interface_stb;
1809 assign interface3_converted_interface_ack = libresocsim_libresoc_interface3_ack;
1810 assign libresocsim_libresoc_interface3_we = interface3_converted_interface_we;
1811 assign libresocsim_libresoc_interface3_cti = interface3_converted_interface_cti;
1812 assign libresocsim_libresoc_interface3_bte = interface3_converted_interface_bte;
1813 assign interface3_converted_interface_err = libresocsim_libresoc_interface3_err;
1814 always @(*) begin
1815         libresocsim_libresoc_interface3_sel <= 8'd0;
1816         libresocsim_libresoc_interface3_adr <= 29'd0;
1817         interface3_converted_interface_dat_r <= 32'd0;
1818         libresocsim_libresoc_interface3_dat_w <= 64'd0;
1819         case (interface3_converted_interface_adr[0])
1820                 1'd0: begin
1821                         libresocsim_libresoc_interface3_adr <= interface3_converted_interface_adr[29:1];
1822                         libresocsim_libresoc_interface3_sel[3:0] <= 4'd15;
1823                         libresocsim_libresoc_interface3_dat_w[31:0] <= interface3_converted_interface_dat_w;
1824                         interface3_converted_interface_dat_r <= libresocsim_libresoc_interface3_dat_r[31:0];
1825                 end
1826                 1'd1: begin
1827                         libresocsim_libresoc_interface3_adr <= interface3_converted_interface_adr[29:1];
1828                         libresocsim_libresoc_interface3_sel[7:4] <= 4'd15;
1829                         libresocsim_libresoc_interface3_dat_w[63:32] <= interface3_converted_interface_dat_w;
1830                         interface3_converted_interface_dat_r <= libresocsim_libresoc_interface3_dat_r[63:32];
1831                 end
1832         endcase
1833 end
1834 assign libresocsim_reset = libresocsim_reset_re;
1835 assign libresocsim_bus_errors_status = libresocsim_bus_errors;
1836 always @(*) begin
1837         libresocsim_we <= 4'd0;
1838         libresocsim_we[0] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[0]);
1839         libresocsim_we[1] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[1]);
1840         libresocsim_we[2] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[2]);
1841         libresocsim_we[3] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[3]);
1842 end
1843 assign libresocsim_adr = libresocsim_ram_bus_adr[4:0];
1844 assign libresocsim_ram_bus_dat_r = libresocsim_dat_r;
1845 assign libresocsim_dat_w = libresocsim_ram_bus_dat_w;
1846 assign libresocsim_zero_trigger = (libresocsim_value != 1'd0);
1847 assign libresocsim_eventmanager_status_w = libresocsim_zero_status;
1848 always @(*) begin
1849         libresocsim_zero_clear <= 1'd0;
1850         if ((libresocsim_eventmanager_pending_re & libresocsim_eventmanager_pending_r)) begin
1851                 libresocsim_zero_clear <= 1'd1;
1852         end
1853 end
1854 assign libresocsim_eventmanager_pending_w = libresocsim_zero_pending;
1855 assign libresocsim_irq = (libresocsim_eventmanager_pending_w & libresocsim_eventmanager_storage);
1856 assign libresocsim_zero_status = libresocsim_zero_trigger;
1857 always @(*) begin
1858         ram_we <= 4'd0;
1859         ram_we[0] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[0]);
1860         ram_we[1] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[1]);
1861         ram_we[2] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[2]);
1862         ram_we[3] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[3]);
1863 end
1864 assign ram_adr = ram_bus_ram_bus_adr[4:0];
1865 assign ram_bus_ram_bus_dat_r = ram_dat_r;
1866 assign ram_dat_w = ram_bus_ram_bus_dat_w;
1867 assign sys_clk_1 = sys_clk;
1868 assign por_clk = sys_clk;
1869 assign sys_rst_1 = int_rst;
1870 assign dfi_p0_address = sdram_master_p0_address;
1871 assign dfi_p0_bank = sdram_master_p0_bank;
1872 assign dfi_p0_cas_n = sdram_master_p0_cas_n;
1873 assign dfi_p0_cs_n = sdram_master_p0_cs_n;
1874 assign dfi_p0_ras_n = sdram_master_p0_ras_n;
1875 assign dfi_p0_we_n = sdram_master_p0_we_n;
1876 assign dfi_p0_cke = sdram_master_p0_cke;
1877 assign dfi_p0_odt = sdram_master_p0_odt;
1878 assign dfi_p0_reset_n = sdram_master_p0_reset_n;
1879 assign dfi_p0_act_n = sdram_master_p0_act_n;
1880 assign dfi_p0_wrdata = sdram_master_p0_wrdata;
1881 assign dfi_p0_wrdata_en = sdram_master_p0_wrdata_en;
1882 assign dfi_p0_wrdata_mask = sdram_master_p0_wrdata_mask;
1883 assign dfi_p0_rddata_en = sdram_master_p0_rddata_en;
1884 assign sdram_master_p0_rddata = dfi_p0_rddata;
1885 assign sdram_master_p0_rddata_valid = dfi_p0_rddata_valid;
1886 assign sdram_slave_p0_address = sdram_dfi_p0_address;
1887 assign sdram_slave_p0_bank = sdram_dfi_p0_bank;
1888 assign sdram_slave_p0_cas_n = sdram_dfi_p0_cas_n;
1889 assign sdram_slave_p0_cs_n = sdram_dfi_p0_cs_n;
1890 assign sdram_slave_p0_ras_n = sdram_dfi_p0_ras_n;
1891 assign sdram_slave_p0_we_n = sdram_dfi_p0_we_n;
1892 assign sdram_slave_p0_cke = sdram_dfi_p0_cke;
1893 assign sdram_slave_p0_odt = sdram_dfi_p0_odt;
1894 assign sdram_slave_p0_reset_n = sdram_dfi_p0_reset_n;
1895 assign sdram_slave_p0_act_n = sdram_dfi_p0_act_n;
1896 assign sdram_slave_p0_wrdata = sdram_dfi_p0_wrdata;
1897 assign sdram_slave_p0_wrdata_en = sdram_dfi_p0_wrdata_en;
1898 assign sdram_slave_p0_wrdata_mask = sdram_dfi_p0_wrdata_mask;
1899 assign sdram_slave_p0_rddata_en = sdram_dfi_p0_rddata_en;
1900 assign sdram_dfi_p0_rddata = sdram_slave_p0_rddata;
1901 assign sdram_dfi_p0_rddata_valid = sdram_slave_p0_rddata_valid;
1902 always @(*) begin
1903         sdram_master_p0_wrdata_mask <= 2'd0;
1904         sdram_master_p0_rddata_en <= 1'd0;
1905         sdram_master_p0_act_n <= 1'd1;
1906         sdram_master_p0_wrdata <= 16'd0;
1907         sdram_slave_p0_rddata <= 16'd0;
1908         sdram_slave_p0_rddata_valid <= 1'd0;
1909         sdram_master_p0_address <= 13'd0;
1910         sdram_master_p0_bank <= 2'd0;
1911         sdram_master_p0_cas_n <= 1'd1;
1912         sdram_master_p0_cs_n <= 1'd1;
1913         sdram_master_p0_ras_n <= 1'd1;
1914         sdram_master_p0_we_n <= 1'd1;
1915         sdram_master_p0_cke <= 1'd0;
1916         sdram_master_p0_odt <= 1'd0;
1917         sdram_master_p0_reset_n <= 1'd0;
1918         sdram_inti_p0_rddata <= 16'd0;
1919         sdram_inti_p0_rddata_valid <= 1'd0;
1920         sdram_master_p0_wrdata_en <= 1'd0;
1921         if (sdram_sel) begin
1922                 sdram_master_p0_address <= sdram_slave_p0_address;
1923                 sdram_master_p0_bank <= sdram_slave_p0_bank;
1924                 sdram_master_p0_cas_n <= sdram_slave_p0_cas_n;
1925                 sdram_master_p0_cs_n <= sdram_slave_p0_cs_n;
1926                 sdram_master_p0_ras_n <= sdram_slave_p0_ras_n;
1927                 sdram_master_p0_we_n <= sdram_slave_p0_we_n;
1928                 sdram_master_p0_cke <= sdram_slave_p0_cke;
1929                 sdram_master_p0_odt <= sdram_slave_p0_odt;
1930                 sdram_master_p0_reset_n <= sdram_slave_p0_reset_n;
1931                 sdram_master_p0_act_n <= sdram_slave_p0_act_n;
1932                 sdram_master_p0_wrdata <= sdram_slave_p0_wrdata;
1933                 sdram_master_p0_wrdata_en <= sdram_slave_p0_wrdata_en;
1934                 sdram_master_p0_wrdata_mask <= sdram_slave_p0_wrdata_mask;
1935                 sdram_master_p0_rddata_en <= sdram_slave_p0_rddata_en;
1936                 sdram_slave_p0_rddata <= sdram_master_p0_rddata;
1937                 sdram_slave_p0_rddata_valid <= sdram_master_p0_rddata_valid;
1938         end else begin
1939                 sdram_master_p0_address <= sdram_inti_p0_address;
1940                 sdram_master_p0_bank <= sdram_inti_p0_bank;
1941                 sdram_master_p0_cas_n <= sdram_inti_p0_cas_n;
1942                 sdram_master_p0_cs_n <= sdram_inti_p0_cs_n;
1943                 sdram_master_p0_ras_n <= sdram_inti_p0_ras_n;
1944                 sdram_master_p0_we_n <= sdram_inti_p0_we_n;
1945                 sdram_master_p0_cke <= sdram_inti_p0_cke;
1946                 sdram_master_p0_odt <= sdram_inti_p0_odt;
1947                 sdram_master_p0_reset_n <= sdram_inti_p0_reset_n;
1948                 sdram_master_p0_act_n <= sdram_inti_p0_act_n;
1949                 sdram_master_p0_wrdata <= sdram_inti_p0_wrdata;
1950                 sdram_master_p0_wrdata_en <= sdram_inti_p0_wrdata_en;
1951                 sdram_master_p0_wrdata_mask <= sdram_inti_p0_wrdata_mask;
1952                 sdram_master_p0_rddata_en <= sdram_inti_p0_rddata_en;
1953                 sdram_inti_p0_rddata <= sdram_master_p0_rddata;
1954                 sdram_inti_p0_rddata_valid <= sdram_master_p0_rddata_valid;
1955         end
1956 end
1957 assign sdram_inti_p0_cke = sdram_cke_1;
1958 assign sdram_inti_p0_odt = sdram_odt;
1959 assign sdram_inti_p0_reset_n = sdram_reset_n;
1960 always @(*) begin
1961         sdram_inti_p0_we_n <= 1'd1;
1962         sdram_inti_p0_cas_n <= 1'd1;
1963         sdram_inti_p0_cs_n <= 1'd1;
1964         sdram_inti_p0_ras_n <= 1'd1;
1965         if (sdram_command_issue_re) begin
1966                 sdram_inti_p0_cs_n <= {1{(~sdram_command_storage[0])}};
1967                 sdram_inti_p0_we_n <= (~sdram_command_storage[1]);
1968                 sdram_inti_p0_cas_n <= (~sdram_command_storage[2]);
1969                 sdram_inti_p0_ras_n <= (~sdram_command_storage[3]);
1970         end else begin
1971                 sdram_inti_p0_cs_n <= {1{1'd1}};
1972                 sdram_inti_p0_we_n <= 1'd1;
1973                 sdram_inti_p0_cas_n <= 1'd1;
1974                 sdram_inti_p0_ras_n <= 1'd1;
1975         end
1976 end
1977 assign sdram_inti_p0_address = sdram_address_storage;
1978 assign sdram_inti_p0_bank = sdram_baddress_storage;
1979 assign sdram_inti_p0_wrdata_en = (sdram_command_issue_re & sdram_command_storage[4]);
1980 assign sdram_inti_p0_rddata_en = (sdram_command_issue_re & sdram_command_storage[5]);
1981 assign sdram_inti_p0_wrdata = sdram_wrdata_storage;
1982 assign sdram_inti_p0_wrdata_mask = 1'd0;
1983 assign sdram_bankmachine0_req_valid = sdram_interface_bank0_valid;
1984 assign sdram_interface_bank0_ready = sdram_bankmachine0_req_ready;
1985 assign sdram_bankmachine0_req_we = sdram_interface_bank0_we;
1986 assign sdram_bankmachine0_req_addr = sdram_interface_bank0_addr;
1987 assign sdram_interface_bank0_lock = sdram_bankmachine0_req_lock;
1988 assign sdram_interface_bank0_wdata_ready = sdram_bankmachine0_req_wdata_ready;
1989 assign sdram_interface_bank0_rdata_valid = sdram_bankmachine0_req_rdata_valid;
1990 assign sdram_bankmachine1_req_valid = sdram_interface_bank1_valid;
1991 assign sdram_interface_bank1_ready = sdram_bankmachine1_req_ready;
1992 assign sdram_bankmachine1_req_we = sdram_interface_bank1_we;
1993 assign sdram_bankmachine1_req_addr = sdram_interface_bank1_addr;
1994 assign sdram_interface_bank1_lock = sdram_bankmachine1_req_lock;
1995 assign sdram_interface_bank1_wdata_ready = sdram_bankmachine1_req_wdata_ready;
1996 assign sdram_interface_bank1_rdata_valid = sdram_bankmachine1_req_rdata_valid;
1997 assign sdram_bankmachine2_req_valid = sdram_interface_bank2_valid;
1998 assign sdram_interface_bank2_ready = sdram_bankmachine2_req_ready;
1999 assign sdram_bankmachine2_req_we = sdram_interface_bank2_we;
2000 assign sdram_bankmachine2_req_addr = sdram_interface_bank2_addr;
2001 assign sdram_interface_bank2_lock = sdram_bankmachine2_req_lock;
2002 assign sdram_interface_bank2_wdata_ready = sdram_bankmachine2_req_wdata_ready;
2003 assign sdram_interface_bank2_rdata_valid = sdram_bankmachine2_req_rdata_valid;
2004 assign sdram_bankmachine3_req_valid = sdram_interface_bank3_valid;
2005 assign sdram_interface_bank3_ready = sdram_bankmachine3_req_ready;
2006 assign sdram_bankmachine3_req_we = sdram_interface_bank3_we;
2007 assign sdram_bankmachine3_req_addr = sdram_interface_bank3_addr;
2008 assign sdram_interface_bank3_lock = sdram_bankmachine3_req_lock;
2009 assign sdram_interface_bank3_wdata_ready = sdram_bankmachine3_req_wdata_ready;
2010 assign sdram_interface_bank3_rdata_valid = sdram_bankmachine3_req_rdata_valid;
2011 assign sdram_timer_wait = (~sdram_timer_done0);
2012 assign sdram_postponer_req_i = sdram_timer_done0;
2013 assign sdram_wants_refresh = sdram_postponer_req_o;
2014 assign sdram_timer_done1 = (sdram_timer_count1 == 1'd0);
2015 assign sdram_timer_done0 = sdram_timer_done1;
2016 assign sdram_timer_count0 = sdram_timer_count1;
2017 assign sdram_sequencer_start1 = (sdram_sequencer_start0 | (sdram_sequencer_count != 1'd0));
2018 assign sdram_sequencer_done0 = (sdram_sequencer_done1 & (sdram_sequencer_count == 1'd0));
2019 always @(*) begin
2020         sdram_sequencer_start0 <= 1'd0;
2021         subfragments_refresher_next_state <= 2'd0;
2022         sdram_cmd_valid <= 1'd0;
2023         sdram_cmd_last <= 1'd0;
2024         subfragments_refresher_next_state <= subfragments_refresher_state;
2025         case (subfragments_refresher_state)
2026                 1'd1: begin
2027                         sdram_cmd_valid <= 1'd1;
2028                         if (sdram_cmd_ready) begin
2029                                 sdram_sequencer_start0 <= 1'd1;
2030                                 subfragments_refresher_next_state <= 2'd2;
2031                         end
2032                 end
2033                 2'd2: begin
2034                         sdram_cmd_valid <= 1'd1;
2035                         if (sdram_sequencer_done0) begin
2036                                 sdram_cmd_valid <= 1'd0;
2037                                 sdram_cmd_last <= 1'd1;
2038                                 subfragments_refresher_next_state <= 1'd0;
2039                         end
2040                 end
2041                 default: begin
2042                         if (1'd1) begin
2043                                 if (sdram_wants_refresh) begin
2044                                         subfragments_refresher_next_state <= 1'd1;
2045                                 end
2046                         end
2047                 end
2048         endcase
2049 end
2050 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = sdram_bankmachine0_req_valid;
2051 assign sdram_bankmachine0_req_ready = sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
2052 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine0_req_we;
2053 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine0_req_addr;
2054 assign sdram_bankmachine0_cmd_buffer_sink_valid = sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
2055 assign sdram_bankmachine0_cmd_buffer_lookahead_source_ready = sdram_bankmachine0_cmd_buffer_sink_ready;
2056 assign sdram_bankmachine0_cmd_buffer_sink_first = sdram_bankmachine0_cmd_buffer_lookahead_source_first;
2057 assign sdram_bankmachine0_cmd_buffer_sink_last = sdram_bankmachine0_cmd_buffer_lookahead_source_last;
2058 assign sdram_bankmachine0_cmd_buffer_sink_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
2059 assign sdram_bankmachine0_cmd_buffer_sink_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
2060 assign sdram_bankmachine0_cmd_buffer_source_ready = (sdram_bankmachine0_req_wdata_ready | sdram_bankmachine0_req_rdata_valid);
2061 assign sdram_bankmachine0_req_lock = (sdram_bankmachine0_cmd_buffer_lookahead_source_valid | sdram_bankmachine0_cmd_buffer_source_valid);
2062 assign sdram_bankmachine0_row_hit = (sdram_bankmachine0_row == sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]);
2063 assign sdram_bankmachine0_cmd_payload_ba = 1'd0;
2064 always @(*) begin
2065         sdram_bankmachine0_cmd_payload_a <= 13'd0;
2066         if (sdram_bankmachine0_row_col_n_addr_sel) begin
2067                 sdram_bankmachine0_cmd_payload_a <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
2068         end else begin
2069                 sdram_bankmachine0_cmd_payload_a <= ((sdram_bankmachine0_auto_precharge <<< 4'd10) | {sdram_bankmachine0_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2070         end
2071 end
2072 assign sdram_bankmachine0_twtpcon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_cmd_payload_is_write);
2073 assign sdram_bankmachine0_trccon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open);
2074 assign sdram_bankmachine0_trascon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open);
2075 always @(*) begin
2076         sdram_bankmachine0_auto_precharge <= 1'd0;
2077         if ((sdram_bankmachine0_cmd_buffer_lookahead_source_valid & sdram_bankmachine0_cmd_buffer_source_valid)) begin
2078                 if ((sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9])) begin
2079                         sdram_bankmachine0_auto_precharge <= (sdram_bankmachine0_row_close == 1'd0);
2080                 end
2081         end
2082 end
2083 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
2084 assign {sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
2085 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
2086 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
2087 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
2088 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
2089 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
2090 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
2091 assign sdram_bankmachine0_cmd_buffer_lookahead_source_valid = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
2092 assign sdram_bankmachine0_cmd_buffer_lookahead_source_first = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
2093 assign sdram_bankmachine0_cmd_buffer_lookahead_source_last = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
2094 assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
2095 assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
2096 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
2097 always @(*) begin
2098         sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2099         if (sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
2100                 sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
2101         end else begin
2102                 sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine0_cmd_buffer_lookahead_produce;
2103         end
2104 end
2105 assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
2106 assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | sdram_bankmachine0_cmd_buffer_lookahead_replace));
2107 assign sdram_bankmachine0_cmd_buffer_lookahead_do_read = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
2108 assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine0_cmd_buffer_lookahead_consume;
2109 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
2110 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8);
2111 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
2112 assign sdram_bankmachine0_cmd_buffer_sink_ready = ((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready);
2113 always @(*) begin
2114         sdram_bankmachine0_refresh_gnt <= 1'd0;
2115         sdram_bankmachine0_cmd_valid <= 1'd0;
2116         sdram_bankmachine0_row_open <= 1'd0;
2117         sdram_bankmachine0_row_close <= 1'd0;
2118         subfragments_bankmachine0_next_state <= 3'd0;
2119         sdram_bankmachine0_cmd_payload_cas <= 1'd0;
2120         sdram_bankmachine0_cmd_payload_ras <= 1'd0;
2121         sdram_bankmachine0_cmd_payload_we <= 1'd0;
2122         sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
2123         sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
2124         sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
2125         sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
2126         sdram_bankmachine0_req_wdata_ready <= 1'd0;
2127         sdram_bankmachine0_req_rdata_valid <= 1'd0;
2128         subfragments_bankmachine0_next_state <= subfragments_bankmachine0_state;
2129         case (subfragments_bankmachine0_state)
2130                 1'd1: begin
2131                         if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin
2132                                 sdram_bankmachine0_cmd_valid <= 1'd1;
2133                                 if (sdram_bankmachine0_cmd_ready) begin
2134                                         subfragments_bankmachine0_next_state <= 3'd5;
2135                                 end
2136                                 sdram_bankmachine0_cmd_payload_ras <= 1'd1;
2137                                 sdram_bankmachine0_cmd_payload_we <= 1'd1;
2138                                 sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
2139                         end
2140                         sdram_bankmachine0_row_close <= 1'd1;
2141                 end
2142                 2'd2: begin
2143                         if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin
2144                                 subfragments_bankmachine0_next_state <= 3'd5;
2145                         end
2146                         sdram_bankmachine0_row_close <= 1'd1;
2147                 end
2148                 2'd3: begin
2149                         if (sdram_bankmachine0_trccon_ready) begin
2150                                 sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
2151                                 sdram_bankmachine0_row_open <= 1'd1;
2152                                 sdram_bankmachine0_cmd_valid <= 1'd1;
2153                                 sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
2154                                 if (sdram_bankmachine0_cmd_ready) begin
2155                                         subfragments_bankmachine0_next_state <= 3'd6;
2156                                 end
2157                                 sdram_bankmachine0_cmd_payload_ras <= 1'd1;
2158                         end
2159                 end
2160                 3'd4: begin
2161                         if (sdram_bankmachine0_twtpcon_ready) begin
2162                                 sdram_bankmachine0_refresh_gnt <= 1'd1;
2163                         end
2164                         sdram_bankmachine0_row_close <= 1'd1;
2165                         sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
2166                         if ((~sdram_bankmachine0_refresh_req)) begin
2167                                 subfragments_bankmachine0_next_state <= 1'd0;
2168                         end
2169                 end
2170                 3'd5: begin
2171                         subfragments_bankmachine0_next_state <= 2'd3;
2172                 end
2173                 3'd6: begin
2174                         subfragments_bankmachine0_next_state <= 1'd0;
2175                 end
2176                 default: begin
2177                         if (sdram_bankmachine0_refresh_req) begin
2178                                 subfragments_bankmachine0_next_state <= 3'd4;
2179                         end else begin
2180                                 if (sdram_bankmachine0_cmd_buffer_source_valid) begin
2181                                         if (sdram_bankmachine0_row_opened) begin
2182                                                 if (sdram_bankmachine0_row_hit) begin
2183                                                         sdram_bankmachine0_cmd_valid <= 1'd1;
2184                                                         if (sdram_bankmachine0_cmd_buffer_source_payload_we) begin
2185                                                                 sdram_bankmachine0_req_wdata_ready <= sdram_bankmachine0_cmd_ready;
2186                                                                 sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
2187                                                                 sdram_bankmachine0_cmd_payload_we <= 1'd1;
2188                                                         end else begin
2189                                                                 sdram_bankmachine0_req_rdata_valid <= sdram_bankmachine0_cmd_ready;
2190                                                                 sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
2191                                                         end
2192                                                         sdram_bankmachine0_cmd_payload_cas <= 1'd1;
2193                                                         if ((sdram_bankmachine0_cmd_ready & sdram_bankmachine0_auto_precharge)) begin
2194                                                                 subfragments_bankmachine0_next_state <= 2'd2;
2195                                                         end
2196                                                 end else begin
2197                                                         subfragments_bankmachine0_next_state <= 1'd1;
2198                                                 end
2199                                         end else begin
2200                                                 subfragments_bankmachine0_next_state <= 2'd3;
2201                                         end
2202                                 end
2203                         end
2204                 end
2205         endcase
2206 end
2207 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = sdram_bankmachine1_req_valid;
2208 assign sdram_bankmachine1_req_ready = sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
2209 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine1_req_we;
2210 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine1_req_addr;
2211 assign sdram_bankmachine1_cmd_buffer_sink_valid = sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
2212 assign sdram_bankmachine1_cmd_buffer_lookahead_source_ready = sdram_bankmachine1_cmd_buffer_sink_ready;
2213 assign sdram_bankmachine1_cmd_buffer_sink_first = sdram_bankmachine1_cmd_buffer_lookahead_source_first;
2214 assign sdram_bankmachine1_cmd_buffer_sink_last = sdram_bankmachine1_cmd_buffer_lookahead_source_last;
2215 assign sdram_bankmachine1_cmd_buffer_sink_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
2216 assign sdram_bankmachine1_cmd_buffer_sink_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
2217 assign sdram_bankmachine1_cmd_buffer_source_ready = (sdram_bankmachine1_req_wdata_ready | sdram_bankmachine1_req_rdata_valid);
2218 assign sdram_bankmachine1_req_lock = (sdram_bankmachine1_cmd_buffer_lookahead_source_valid | sdram_bankmachine1_cmd_buffer_source_valid);
2219 assign sdram_bankmachine1_row_hit = (sdram_bankmachine1_row == sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]);
2220 assign sdram_bankmachine1_cmd_payload_ba = 1'd1;
2221 always @(*) begin
2222         sdram_bankmachine1_cmd_payload_a <= 13'd0;
2223         if (sdram_bankmachine1_row_col_n_addr_sel) begin
2224                 sdram_bankmachine1_cmd_payload_a <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
2225         end else begin
2226                 sdram_bankmachine1_cmd_payload_a <= ((sdram_bankmachine1_auto_precharge <<< 4'd10) | {sdram_bankmachine1_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2227         end
2228 end
2229 assign sdram_bankmachine1_twtpcon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_cmd_payload_is_write);
2230 assign sdram_bankmachine1_trccon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open);
2231 assign sdram_bankmachine1_trascon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open);
2232 always @(*) begin
2233         sdram_bankmachine1_auto_precharge <= 1'd0;
2234         if ((sdram_bankmachine1_cmd_buffer_lookahead_source_valid & sdram_bankmachine1_cmd_buffer_source_valid)) begin
2235                 if ((sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9])) begin
2236                         sdram_bankmachine1_auto_precharge <= (sdram_bankmachine1_row_close == 1'd0);
2237                 end
2238         end
2239 end
2240 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
2241 assign {sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
2242 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
2243 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
2244 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
2245 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
2246 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
2247 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
2248 assign sdram_bankmachine1_cmd_buffer_lookahead_source_valid = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
2249 assign sdram_bankmachine1_cmd_buffer_lookahead_source_first = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
2250 assign sdram_bankmachine1_cmd_buffer_lookahead_source_last = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
2251 assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
2252 assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
2253 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
2254 always @(*) begin
2255         sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2256         if (sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
2257                 sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
2258         end else begin
2259                 sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine1_cmd_buffer_lookahead_produce;
2260         end
2261 end
2262 assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
2263 assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | sdram_bankmachine1_cmd_buffer_lookahead_replace));
2264 assign sdram_bankmachine1_cmd_buffer_lookahead_do_read = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
2265 assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine1_cmd_buffer_lookahead_consume;
2266 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
2267 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8);
2268 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
2269 assign sdram_bankmachine1_cmd_buffer_sink_ready = ((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready);
2270 always @(*) begin
2271         sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
2272         sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
2273         sdram_bankmachine1_req_wdata_ready <= 1'd0;
2274         sdram_bankmachine1_req_rdata_valid <= 1'd0;
2275         sdram_bankmachine1_refresh_gnt <= 1'd0;
2276         subfragments_bankmachine1_next_state <= 3'd0;
2277         sdram_bankmachine1_cmd_valid <= 1'd0;
2278         sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
2279         sdram_bankmachine1_row_open <= 1'd0;
2280         sdram_bankmachine1_row_close <= 1'd0;
2281         sdram_bankmachine1_cmd_payload_cas <= 1'd0;
2282         sdram_bankmachine1_cmd_payload_ras <= 1'd0;
2283         sdram_bankmachine1_cmd_payload_we <= 1'd0;
2284         sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
2285         subfragments_bankmachine1_next_state <= subfragments_bankmachine1_state;
2286         case (subfragments_bankmachine1_state)
2287                 1'd1: begin
2288                         if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin
2289                                 sdram_bankmachine1_cmd_valid <= 1'd1;
2290                                 if (sdram_bankmachine1_cmd_ready) begin
2291                                         subfragments_bankmachine1_next_state <= 3'd5;
2292                                 end
2293                                 sdram_bankmachine1_cmd_payload_ras <= 1'd1;
2294                                 sdram_bankmachine1_cmd_payload_we <= 1'd1;
2295                                 sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2296                         end
2297                         sdram_bankmachine1_row_close <= 1'd1;
2298                 end
2299                 2'd2: begin
2300                         if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin
2301                                 subfragments_bankmachine1_next_state <= 3'd5;
2302                         end
2303                         sdram_bankmachine1_row_close <= 1'd1;
2304                 end
2305                 2'd3: begin
2306                         if (sdram_bankmachine1_trccon_ready) begin
2307                                 sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
2308                                 sdram_bankmachine1_row_open <= 1'd1;
2309                                 sdram_bankmachine1_cmd_valid <= 1'd1;
2310                                 sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2311                                 if (sdram_bankmachine1_cmd_ready) begin
2312                                         subfragments_bankmachine1_next_state <= 3'd6;
2313                                 end
2314                                 sdram_bankmachine1_cmd_payload_ras <= 1'd1;
2315                         end
2316                 end
2317                 3'd4: begin
2318                         if (sdram_bankmachine1_twtpcon_ready) begin
2319                                 sdram_bankmachine1_refresh_gnt <= 1'd1;
2320                         end
2321                         sdram_bankmachine1_row_close <= 1'd1;
2322                         sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2323                         if ((~sdram_bankmachine1_refresh_req)) begin
2324                                 subfragments_bankmachine1_next_state <= 1'd0;
2325                         end
2326                 end
2327                 3'd5: begin
2328                         subfragments_bankmachine1_next_state <= 2'd3;
2329                 end
2330                 3'd6: begin
2331                         subfragments_bankmachine1_next_state <= 1'd0;
2332                 end
2333                 default: begin
2334                         if (sdram_bankmachine1_refresh_req) begin
2335                                 subfragments_bankmachine1_next_state <= 3'd4;
2336                         end else begin
2337                                 if (sdram_bankmachine1_cmd_buffer_source_valid) begin
2338                                         if (sdram_bankmachine1_row_opened) begin
2339                                                 if (sdram_bankmachine1_row_hit) begin
2340                                                         sdram_bankmachine1_cmd_valid <= 1'd1;
2341                                                         if (sdram_bankmachine1_cmd_buffer_source_payload_we) begin
2342                                                                 sdram_bankmachine1_req_wdata_ready <= sdram_bankmachine1_cmd_ready;
2343                                                                 sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
2344                                                                 sdram_bankmachine1_cmd_payload_we <= 1'd1;
2345                                                         end else begin
2346                                                                 sdram_bankmachine1_req_rdata_valid <= sdram_bankmachine1_cmd_ready;
2347                                                                 sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
2348                                                         end
2349                                                         sdram_bankmachine1_cmd_payload_cas <= 1'd1;
2350                                                         if ((sdram_bankmachine1_cmd_ready & sdram_bankmachine1_auto_precharge)) begin
2351                                                                 subfragments_bankmachine1_next_state <= 2'd2;
2352                                                         end
2353                                                 end else begin
2354                                                         subfragments_bankmachine1_next_state <= 1'd1;
2355                                                 end
2356                                         end else begin
2357                                                 subfragments_bankmachine1_next_state <= 2'd3;
2358                                         end
2359                                 end
2360                         end
2361                 end
2362         endcase
2363 end
2364 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = sdram_bankmachine2_req_valid;
2365 assign sdram_bankmachine2_req_ready = sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
2366 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine2_req_we;
2367 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine2_req_addr;
2368 assign sdram_bankmachine2_cmd_buffer_sink_valid = sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
2369 assign sdram_bankmachine2_cmd_buffer_lookahead_source_ready = sdram_bankmachine2_cmd_buffer_sink_ready;
2370 assign sdram_bankmachine2_cmd_buffer_sink_first = sdram_bankmachine2_cmd_buffer_lookahead_source_first;
2371 assign sdram_bankmachine2_cmd_buffer_sink_last = sdram_bankmachine2_cmd_buffer_lookahead_source_last;
2372 assign sdram_bankmachine2_cmd_buffer_sink_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
2373 assign sdram_bankmachine2_cmd_buffer_sink_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
2374 assign sdram_bankmachine2_cmd_buffer_source_ready = (sdram_bankmachine2_req_wdata_ready | sdram_bankmachine2_req_rdata_valid);
2375 assign sdram_bankmachine2_req_lock = (sdram_bankmachine2_cmd_buffer_lookahead_source_valid | sdram_bankmachine2_cmd_buffer_source_valid);
2376 assign sdram_bankmachine2_row_hit = (sdram_bankmachine2_row == sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]);
2377 assign sdram_bankmachine2_cmd_payload_ba = 2'd2;
2378 always @(*) begin
2379         sdram_bankmachine2_cmd_payload_a <= 13'd0;
2380         if (sdram_bankmachine2_row_col_n_addr_sel) begin
2381                 sdram_bankmachine2_cmd_payload_a <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
2382         end else begin
2383                 sdram_bankmachine2_cmd_payload_a <= ((sdram_bankmachine2_auto_precharge <<< 4'd10) | {sdram_bankmachine2_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2384         end
2385 end
2386 assign sdram_bankmachine2_twtpcon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_cmd_payload_is_write);
2387 assign sdram_bankmachine2_trccon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open);
2388 assign sdram_bankmachine2_trascon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open);
2389 always @(*) begin
2390         sdram_bankmachine2_auto_precharge <= 1'd0;
2391         if ((sdram_bankmachine2_cmd_buffer_lookahead_source_valid & sdram_bankmachine2_cmd_buffer_source_valid)) begin
2392                 if ((sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9])) begin
2393                         sdram_bankmachine2_auto_precharge <= (sdram_bankmachine2_row_close == 1'd0);
2394                 end
2395         end
2396 end
2397 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
2398 assign {sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
2399 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
2400 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
2401 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
2402 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
2403 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
2404 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
2405 assign sdram_bankmachine2_cmd_buffer_lookahead_source_valid = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
2406 assign sdram_bankmachine2_cmd_buffer_lookahead_source_first = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
2407 assign sdram_bankmachine2_cmd_buffer_lookahead_source_last = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
2408 assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
2409 assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
2410 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
2411 always @(*) begin
2412         sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2413         if (sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
2414                 sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
2415         end else begin
2416                 sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine2_cmd_buffer_lookahead_produce;
2417         end
2418 end
2419 assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
2420 assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | sdram_bankmachine2_cmd_buffer_lookahead_replace));
2421 assign sdram_bankmachine2_cmd_buffer_lookahead_do_read = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
2422 assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine2_cmd_buffer_lookahead_consume;
2423 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
2424 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8);
2425 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
2426 assign sdram_bankmachine2_cmd_buffer_sink_ready = ((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready);
2427 always @(*) begin
2428         sdram_bankmachine2_cmd_payload_cas <= 1'd0;
2429         sdram_bankmachine2_cmd_payload_ras <= 1'd0;
2430         sdram_bankmachine2_cmd_payload_we <= 1'd0;
2431         sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
2432         sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
2433         subfragments_bankmachine2_next_state <= 3'd0;
2434         sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
2435         sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
2436         sdram_bankmachine2_req_wdata_ready <= 1'd0;
2437         sdram_bankmachine2_req_rdata_valid <= 1'd0;
2438         sdram_bankmachine2_refresh_gnt <= 1'd0;
2439         sdram_bankmachine2_cmd_valid <= 1'd0;
2440         sdram_bankmachine2_row_open <= 1'd0;
2441         sdram_bankmachine2_row_close <= 1'd0;
2442         subfragments_bankmachine2_next_state <= subfragments_bankmachine2_state;
2443         case (subfragments_bankmachine2_state)
2444                 1'd1: begin
2445                         if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin
2446                                 sdram_bankmachine2_cmd_valid <= 1'd1;
2447                                 if (sdram_bankmachine2_cmd_ready) begin
2448                                         subfragments_bankmachine2_next_state <= 3'd5;
2449                                 end
2450                                 sdram_bankmachine2_cmd_payload_ras <= 1'd1;
2451                                 sdram_bankmachine2_cmd_payload_we <= 1'd1;
2452                                 sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2453                         end
2454                         sdram_bankmachine2_row_close <= 1'd1;
2455                 end
2456                 2'd2: begin
2457                         if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin
2458                                 subfragments_bankmachine2_next_state <= 3'd5;
2459                         end
2460                         sdram_bankmachine2_row_close <= 1'd1;
2461                 end
2462                 2'd3: begin
2463                         if (sdram_bankmachine2_trccon_ready) begin
2464                                 sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
2465                                 sdram_bankmachine2_row_open <= 1'd1;
2466                                 sdram_bankmachine2_cmd_valid <= 1'd1;
2467                                 sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2468                                 if (sdram_bankmachine2_cmd_ready) begin
2469                                         subfragments_bankmachine2_next_state <= 3'd6;
2470                                 end
2471                                 sdram_bankmachine2_cmd_payload_ras <= 1'd1;
2472                         end
2473                 end
2474                 3'd4: begin
2475                         if (sdram_bankmachine2_twtpcon_ready) begin
2476                                 sdram_bankmachine2_refresh_gnt <= 1'd1;
2477                         end
2478                         sdram_bankmachine2_row_close <= 1'd1;
2479                         sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2480                         if ((~sdram_bankmachine2_refresh_req)) begin
2481                                 subfragments_bankmachine2_next_state <= 1'd0;
2482                         end
2483                 end
2484                 3'd5: begin
2485                         subfragments_bankmachine2_next_state <= 2'd3;
2486                 end
2487                 3'd6: begin
2488                         subfragments_bankmachine2_next_state <= 1'd0;
2489                 end
2490                 default: begin
2491                         if (sdram_bankmachine2_refresh_req) begin
2492                                 subfragments_bankmachine2_next_state <= 3'd4;
2493                         end else begin
2494                                 if (sdram_bankmachine2_cmd_buffer_source_valid) begin
2495                                         if (sdram_bankmachine2_row_opened) begin
2496                                                 if (sdram_bankmachine2_row_hit) begin
2497                                                         sdram_bankmachine2_cmd_valid <= 1'd1;
2498                                                         if (sdram_bankmachine2_cmd_buffer_source_payload_we) begin
2499                                                                 sdram_bankmachine2_req_wdata_ready <= sdram_bankmachine2_cmd_ready;
2500                                                                 sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
2501                                                                 sdram_bankmachine2_cmd_payload_we <= 1'd1;
2502                                                         end else begin
2503                                                                 sdram_bankmachine2_req_rdata_valid <= sdram_bankmachine2_cmd_ready;
2504                                                                 sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
2505                                                         end
2506                                                         sdram_bankmachine2_cmd_payload_cas <= 1'd1;
2507                                                         if ((sdram_bankmachine2_cmd_ready & sdram_bankmachine2_auto_precharge)) begin
2508                                                                 subfragments_bankmachine2_next_state <= 2'd2;
2509                                                         end
2510                                                 end else begin
2511                                                         subfragments_bankmachine2_next_state <= 1'd1;
2512                                                 end
2513                                         end else begin
2514                                                 subfragments_bankmachine2_next_state <= 2'd3;
2515                                         end
2516                                 end
2517                         end
2518                 end
2519         endcase
2520 end
2521 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = sdram_bankmachine3_req_valid;
2522 assign sdram_bankmachine3_req_ready = sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
2523 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine3_req_we;
2524 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine3_req_addr;
2525 assign sdram_bankmachine3_cmd_buffer_sink_valid = sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
2526 assign sdram_bankmachine3_cmd_buffer_lookahead_source_ready = sdram_bankmachine3_cmd_buffer_sink_ready;
2527 assign sdram_bankmachine3_cmd_buffer_sink_first = sdram_bankmachine3_cmd_buffer_lookahead_source_first;
2528 assign sdram_bankmachine3_cmd_buffer_sink_last = sdram_bankmachine3_cmd_buffer_lookahead_source_last;
2529 assign sdram_bankmachine3_cmd_buffer_sink_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
2530 assign sdram_bankmachine3_cmd_buffer_sink_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
2531 assign sdram_bankmachine3_cmd_buffer_source_ready = (sdram_bankmachine3_req_wdata_ready | sdram_bankmachine3_req_rdata_valid);
2532 assign sdram_bankmachine3_req_lock = (sdram_bankmachine3_cmd_buffer_lookahead_source_valid | sdram_bankmachine3_cmd_buffer_source_valid);
2533 assign sdram_bankmachine3_row_hit = (sdram_bankmachine3_row == sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]);
2534 assign sdram_bankmachine3_cmd_payload_ba = 2'd3;
2535 always @(*) begin
2536         sdram_bankmachine3_cmd_payload_a <= 13'd0;
2537         if (sdram_bankmachine3_row_col_n_addr_sel) begin
2538                 sdram_bankmachine3_cmd_payload_a <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
2539         end else begin
2540                 sdram_bankmachine3_cmd_payload_a <= ((sdram_bankmachine3_auto_precharge <<< 4'd10) | {sdram_bankmachine3_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2541         end
2542 end
2543 assign sdram_bankmachine3_twtpcon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_cmd_payload_is_write);
2544 assign sdram_bankmachine3_trccon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open);
2545 assign sdram_bankmachine3_trascon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open);
2546 always @(*) begin
2547         sdram_bankmachine3_auto_precharge <= 1'd0;
2548         if ((sdram_bankmachine3_cmd_buffer_lookahead_source_valid & sdram_bankmachine3_cmd_buffer_source_valid)) begin
2549                 if ((sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9])) begin
2550                         sdram_bankmachine3_auto_precharge <= (sdram_bankmachine3_row_close == 1'd0);
2551                 end
2552         end
2553 end
2554 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
2555 assign {sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
2556 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
2557 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
2558 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
2559 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
2560 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
2561 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
2562 assign sdram_bankmachine3_cmd_buffer_lookahead_source_valid = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
2563 assign sdram_bankmachine3_cmd_buffer_lookahead_source_first = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
2564 assign sdram_bankmachine3_cmd_buffer_lookahead_source_last = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
2565 assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
2566 assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
2567 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
2568 always @(*) begin
2569         sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2570         if (sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
2571                 sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
2572         end else begin
2573                 sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine3_cmd_buffer_lookahead_produce;
2574         end
2575 end
2576 assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
2577 assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | sdram_bankmachine3_cmd_buffer_lookahead_replace));
2578 assign sdram_bankmachine3_cmd_buffer_lookahead_do_read = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
2579 assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine3_cmd_buffer_lookahead_consume;
2580 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
2581 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8);
2582 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
2583 assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready);
2584 always @(*) begin
2585         subfragments_bankmachine3_next_state <= 3'd0;
2586         sdram_bankmachine3_row_open <= 1'd0;
2587         sdram_bankmachine3_row_close <= 1'd0;
2588         sdram_bankmachine3_cmd_payload_cas <= 1'd0;
2589         sdram_bankmachine3_cmd_payload_ras <= 1'd0;
2590         sdram_bankmachine3_cmd_payload_we <= 1'd0;
2591         sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
2592         sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
2593         sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
2594         sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
2595         sdram_bankmachine3_req_wdata_ready <= 1'd0;
2596         sdram_bankmachine3_req_rdata_valid <= 1'd0;
2597         sdram_bankmachine3_refresh_gnt <= 1'd0;
2598         sdram_bankmachine3_cmd_valid <= 1'd0;
2599         subfragments_bankmachine3_next_state <= subfragments_bankmachine3_state;
2600         case (subfragments_bankmachine3_state)
2601                 1'd1: begin
2602                         if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin
2603                                 sdram_bankmachine3_cmd_valid <= 1'd1;
2604                                 if (sdram_bankmachine3_cmd_ready) begin
2605                                         subfragments_bankmachine3_next_state <= 3'd5;
2606                                 end
2607                                 sdram_bankmachine3_cmd_payload_ras <= 1'd1;
2608                                 sdram_bankmachine3_cmd_payload_we <= 1'd1;
2609                                 sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2610                         end
2611                         sdram_bankmachine3_row_close <= 1'd1;
2612                 end
2613                 2'd2: begin
2614                         if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin
2615                                 subfragments_bankmachine3_next_state <= 3'd5;
2616                         end
2617                         sdram_bankmachine3_row_close <= 1'd1;
2618                 end
2619                 2'd3: begin
2620                         if (sdram_bankmachine3_trccon_ready) begin
2621                                 sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
2622                                 sdram_bankmachine3_row_open <= 1'd1;
2623                                 sdram_bankmachine3_cmd_valid <= 1'd1;
2624                                 sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2625                                 if (sdram_bankmachine3_cmd_ready) begin
2626                                         subfragments_bankmachine3_next_state <= 3'd6;
2627                                 end
2628                                 sdram_bankmachine3_cmd_payload_ras <= 1'd1;
2629                         end
2630                 end
2631                 3'd4: begin
2632                         if (sdram_bankmachine3_twtpcon_ready) begin
2633                                 sdram_bankmachine3_refresh_gnt <= 1'd1;
2634                         end
2635                         sdram_bankmachine3_row_close <= 1'd1;
2636                         sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2637                         if ((~sdram_bankmachine3_refresh_req)) begin
2638                                 subfragments_bankmachine3_next_state <= 1'd0;
2639                         end
2640                 end
2641                 3'd5: begin
2642                         subfragments_bankmachine3_next_state <= 2'd3;
2643                 end
2644                 3'd6: begin
2645                         subfragments_bankmachine3_next_state <= 1'd0;
2646                 end
2647                 default: begin
2648                         if (sdram_bankmachine3_refresh_req) begin
2649                                 subfragments_bankmachine3_next_state <= 3'd4;
2650                         end else begin
2651                                 if (sdram_bankmachine3_cmd_buffer_source_valid) begin
2652                                         if (sdram_bankmachine3_row_opened) begin
2653                                                 if (sdram_bankmachine3_row_hit) begin
2654                                                         sdram_bankmachine3_cmd_valid <= 1'd1;
2655                                                         if (sdram_bankmachine3_cmd_buffer_source_payload_we) begin
2656                                                                 sdram_bankmachine3_req_wdata_ready <= sdram_bankmachine3_cmd_ready;
2657                                                                 sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
2658                                                                 sdram_bankmachine3_cmd_payload_we <= 1'd1;
2659                                                         end else begin
2660                                                                 sdram_bankmachine3_req_rdata_valid <= sdram_bankmachine3_cmd_ready;
2661                                                                 sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
2662                                                         end
2663                                                         sdram_bankmachine3_cmd_payload_cas <= 1'd1;
2664                                                         if ((sdram_bankmachine3_cmd_ready & sdram_bankmachine3_auto_precharge)) begin
2665                                                                 subfragments_bankmachine3_next_state <= 2'd2;
2666                                                         end
2667                                                 end else begin
2668                                                         subfragments_bankmachine3_next_state <= 1'd1;
2669                                                 end
2670                                         end else begin
2671                                                 subfragments_bankmachine3_next_state <= 2'd3;
2672                                         end
2673                                 end
2674                         end
2675                 end
2676         endcase
2677 end
2678 assign sdram_choose_req_want_cmds = 1'd1;
2679 assign sdram_trrdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we)));
2680 assign sdram_tfawcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we)));
2681 assign sdram_ras_allowed = (sdram_trrdcon_ready & sdram_tfawcon_ready);
2682 assign sdram_tccdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_cmd_payload_is_write | sdram_choose_req_cmd_payload_is_read));
2683 assign sdram_cas_allowed = sdram_tccdcon_ready;
2684 assign sdram_twtrcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write);
2685 assign sdram_read_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_read) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_read)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_read)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_read));
2686 assign sdram_write_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_write) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_write)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_write)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_write));
2687 assign sdram_max_time0 = (sdram_time0 == 1'd0);
2688 assign sdram_max_time1 = (sdram_time1 == 1'd0);
2689 assign sdram_bankmachine0_refresh_req = sdram_cmd_valid;
2690 assign sdram_bankmachine1_refresh_req = sdram_cmd_valid;
2691 assign sdram_bankmachine2_refresh_req = sdram_cmd_valid;
2692 assign sdram_bankmachine3_refresh_req = sdram_cmd_valid;
2693 assign sdram_go_to_refresh = (((sdram_bankmachine0_refresh_gnt & sdram_bankmachine1_refresh_gnt) & sdram_bankmachine2_refresh_gnt) & sdram_bankmachine3_refresh_gnt);
2694 assign sdram_interface_rdata = {sdram_dfi_p0_rddata};
2695 assign {sdram_dfi_p0_wrdata} = sdram_interface_wdata;
2696 assign {sdram_dfi_p0_wrdata_mask} = (~sdram_interface_wdata_we);
2697 always @(*) begin
2698         sdram_choose_cmd_valids <= 4'd0;
2699         sdram_choose_cmd_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2700         sdram_choose_cmd_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2701         sdram_choose_cmd_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2702         sdram_choose_cmd_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2703 end
2704 assign sdram_choose_cmd_request = sdram_choose_cmd_valids;
2705 assign sdram_choose_cmd_cmd_valid = rhs_array_muxed0;
2706 assign sdram_choose_cmd_cmd_payload_a = rhs_array_muxed1;
2707 assign sdram_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
2708 assign sdram_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
2709 assign sdram_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
2710 assign sdram_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
2711 always @(*) begin
2712         sdram_choose_cmd_cmd_payload_cas <= 1'd0;
2713         if (sdram_choose_cmd_cmd_valid) begin
2714                 sdram_choose_cmd_cmd_payload_cas <= t_array_muxed0;
2715         end
2716 end
2717 always @(*) begin
2718         sdram_choose_cmd_cmd_payload_ras <= 1'd0;
2719         if (sdram_choose_cmd_cmd_valid) begin
2720                 sdram_choose_cmd_cmd_payload_ras <= t_array_muxed1;
2721         end
2722 end
2723 always @(*) begin
2724         sdram_choose_cmd_cmd_payload_we <= 1'd0;
2725         if (sdram_choose_cmd_cmd_valid) begin
2726                 sdram_choose_cmd_cmd_payload_we <= t_array_muxed2;
2727         end
2728 end
2729 assign sdram_choose_cmd_ce = (sdram_choose_cmd_cmd_ready | (~sdram_choose_cmd_cmd_valid));
2730 always @(*) begin
2731         sdram_choose_req_valids <= 4'd0;
2732         sdram_choose_req_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_req_want_writes))));
2733         sdram_choose_req_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_req_want_writes))));
2734         sdram_choose_req_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_req_want_writes))));
2735         sdram_choose_req_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_req_want_writes))));
2736 end
2737 assign sdram_choose_req_request = sdram_choose_req_valids;
2738 assign sdram_choose_req_cmd_valid = rhs_array_muxed6;
2739 assign sdram_choose_req_cmd_payload_a = rhs_array_muxed7;
2740 assign sdram_choose_req_cmd_payload_ba = rhs_array_muxed8;
2741 assign sdram_choose_req_cmd_payload_is_read = rhs_array_muxed9;
2742 assign sdram_choose_req_cmd_payload_is_write = rhs_array_muxed10;
2743 assign sdram_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
2744 always @(*) begin
2745         sdram_choose_req_cmd_payload_cas <= 1'd0;
2746         if (sdram_choose_req_cmd_valid) begin
2747                 sdram_choose_req_cmd_payload_cas <= t_array_muxed3;
2748         end
2749 end
2750 always @(*) begin
2751         sdram_choose_req_cmd_payload_ras <= 1'd0;
2752         if (sdram_choose_req_cmd_valid) begin
2753                 sdram_choose_req_cmd_payload_ras <= t_array_muxed4;
2754         end
2755 end
2756 always @(*) begin
2757         sdram_choose_req_cmd_payload_we <= 1'd0;
2758         if (sdram_choose_req_cmd_valid) begin
2759                 sdram_choose_req_cmd_payload_we <= t_array_muxed5;
2760         end
2761 end
2762 always @(*) begin
2763         sdram_bankmachine0_cmd_ready <= 1'd0;
2764         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd0))) begin
2765                 sdram_bankmachine0_cmd_ready <= 1'd1;
2766         end
2767         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd0))) begin
2768                 sdram_bankmachine0_cmd_ready <= 1'd1;
2769         end
2770 end
2771 always @(*) begin
2772         sdram_bankmachine1_cmd_ready <= 1'd0;
2773         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd1))) begin
2774                 sdram_bankmachine1_cmd_ready <= 1'd1;
2775         end
2776         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd1))) begin
2777                 sdram_bankmachine1_cmd_ready <= 1'd1;
2778         end
2779 end
2780 always @(*) begin
2781         sdram_bankmachine2_cmd_ready <= 1'd0;
2782         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd2))) begin
2783                 sdram_bankmachine2_cmd_ready <= 1'd1;
2784         end
2785         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd2))) begin
2786                 sdram_bankmachine2_cmd_ready <= 1'd1;
2787         end
2788 end
2789 always @(*) begin
2790         sdram_bankmachine3_cmd_ready <= 1'd0;
2791         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd3))) begin
2792                 sdram_bankmachine3_cmd_ready <= 1'd1;
2793         end
2794         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd3))) begin
2795                 sdram_bankmachine3_cmd_ready <= 1'd1;
2796         end
2797 end
2798 assign sdram_choose_req_ce = (sdram_choose_req_cmd_ready | (~sdram_choose_req_cmd_valid));
2799 assign sdram_dfi_p0_reset_n = 1'd1;
2800 assign sdram_dfi_p0_cke = {1{sdram_steerer0}};
2801 assign sdram_dfi_p0_odt = {1{sdram_steerer1}};
2802 always @(*) begin
2803         sdram_en0 <= 1'd0;
2804         subfragments_multiplexer_next_state <= 3'd0;
2805         sdram_choose_req_want_writes <= 1'd0;
2806         sdram_en1 <= 1'd0;
2807         sdram_choose_req_want_reads <= 1'd0;
2808         sdram_choose_req_cmd_ready <= 1'd0;
2809         sdram_cmd_ready <= 1'd0;
2810         sdram_choose_req_want_activates <= 1'd0;
2811         sdram_steerer_sel <= 2'd0;
2812         sdram_choose_req_want_activates <= sdram_ras_allowed;
2813         subfragments_multiplexer_next_state <= subfragments_multiplexer_state;
2814         case (subfragments_multiplexer_state)
2815                 1'd1: begin
2816                         sdram_en1 <= 1'd1;
2817                         sdram_choose_req_want_writes <= 1'd1;
2818                         if (1'd1) begin
2819                                 sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed));
2820                         end else begin
2821                                 sdram_choose_req_want_activates <= sdram_ras_allowed;
2822                                 sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed);
2823                                 sdram_choose_req_cmd_ready <= sdram_cas_allowed;
2824                         end
2825                         sdram_steerer_sel <= 2'd2;
2826                         if (sdram_read_available) begin
2827                                 if (((~sdram_write_available) | sdram_max_time1)) begin
2828                                         subfragments_multiplexer_next_state <= 2'd3;
2829                                 end
2830                         end
2831                         if (sdram_go_to_refresh) begin
2832                                 subfragments_multiplexer_next_state <= 2'd2;
2833                         end
2834                 end
2835                 2'd2: begin
2836                         sdram_steerer_sel <= 2'd3;
2837                         sdram_cmd_ready <= 1'd1;
2838                         if (sdram_cmd_last) begin
2839                                 subfragments_multiplexer_next_state <= 1'd0;
2840                         end
2841                 end
2842                 2'd3: begin
2843                         if (sdram_twtrcon_ready) begin
2844                                 subfragments_multiplexer_next_state <= 1'd0;
2845                         end
2846                 end
2847                 3'd4: begin
2848                         subfragments_multiplexer_next_state <= 3'd5;
2849                 end
2850                 3'd5: begin
2851                         subfragments_multiplexer_next_state <= 1'd1;
2852                 end
2853                 default: begin
2854                         sdram_en0 <= 1'd1;
2855                         sdram_choose_req_want_reads <= 1'd1;
2856                         if (1'd1) begin
2857                                 sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed));
2858                         end else begin
2859                                 sdram_choose_req_want_activates <= sdram_ras_allowed;
2860                                 sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed);
2861                                 sdram_choose_req_cmd_ready <= sdram_cas_allowed;
2862                         end
2863                         sdram_steerer_sel <= 2'd2;
2864                         if (sdram_write_available) begin
2865                                 if (((~sdram_read_available) | sdram_max_time0)) begin
2866                                         subfragments_multiplexer_next_state <= 3'd4;
2867                                 end
2868                         end
2869                         if (sdram_go_to_refresh) begin
2870                                 subfragments_multiplexer_next_state <= 2'd2;
2871                         end
2872                 end
2873         endcase
2874 end
2875 assign subfragments_roundrobin0_request = {(((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)};
2876 assign subfragments_roundrobin0_ce = ((~sdram_interface_bank0_valid) & (~sdram_interface_bank0_lock));
2877 assign sdram_interface_bank0_addr = rhs_array_muxed12;
2878 assign sdram_interface_bank0_we = rhs_array_muxed13;
2879 assign sdram_interface_bank0_valid = rhs_array_muxed14;
2880 assign subfragments_roundrobin1_request = {(((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)};
2881 assign subfragments_roundrobin1_ce = ((~sdram_interface_bank1_valid) & (~sdram_interface_bank1_lock));
2882 assign sdram_interface_bank1_addr = rhs_array_muxed15;
2883 assign sdram_interface_bank1_we = rhs_array_muxed16;
2884 assign sdram_interface_bank1_valid = rhs_array_muxed17;
2885 assign subfragments_roundrobin2_request = {(((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)};
2886 assign subfragments_roundrobin2_ce = ((~sdram_interface_bank2_valid) & (~sdram_interface_bank2_lock));
2887 assign sdram_interface_bank2_addr = rhs_array_muxed18;
2888 assign sdram_interface_bank2_we = rhs_array_muxed19;
2889 assign sdram_interface_bank2_valid = rhs_array_muxed20;
2890 assign subfragments_roundrobin3_request = {(((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid)};
2891 assign subfragments_roundrobin3_ce = ((~sdram_interface_bank3_valid) & (~sdram_interface_bank3_lock));
2892 assign sdram_interface_bank3_addr = rhs_array_muxed21;
2893 assign sdram_interface_bank3_we = rhs_array_muxed22;
2894 assign sdram_interface_bank3_valid = rhs_array_muxed23;
2895 assign port_cmd_ready = ((((1'd0 | (((subfragments_roundrobin0_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank0_ready)) | (((subfragments_roundrobin1_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank1_ready)) | (((subfragments_roundrobin2_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank2_ready)) | (((subfragments_roundrobin3_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0)))))) & sdram_interface_bank3_ready));
2896 assign port_wdata_ready = subfragments_new_master_wdata_ready;
2897 assign port_rdata_valid = subfragments_new_master_rdata_valid3;
2898 always @(*) begin
2899         sdram_interface_wdata <= 16'd0;
2900         sdram_interface_wdata_we <= 2'd0;
2901         case ({subfragments_new_master_wdata_ready})
2902                 1'd1: begin
2903                         sdram_interface_wdata <= port_wdata_payload_data;
2904                         sdram_interface_wdata_we <= port_wdata_payload_we;
2905                 end
2906                 default: begin
2907                         sdram_interface_wdata <= 1'd0;
2908                         sdram_interface_wdata_we <= 1'd0;
2909                 end
2910         endcase
2911 end
2912 assign port_rdata_payload_data = sdram_interface_rdata;
2913 assign subfragments_roundrobin0_grant = 1'd0;
2914 assign subfragments_roundrobin1_grant = 1'd0;
2915 assign subfragments_roundrobin2_grant = 1'd0;
2916 assign subfragments_roundrobin3_grant = 1'd0;
2917 assign converter_reset = (~wb_sdram_cyc);
2918 always @(*) begin
2919         litedram_wb_dat_w <= 16'd0;
2920         case (converter_counter)
2921                 1'd0: begin
2922                         litedram_wb_dat_w <= wb_sdram_dat_w[31:0];
2923                 end
2924                 1'd1: begin
2925                         litedram_wb_dat_w <= wb_sdram_dat_w[31:16];
2926                 end
2927         endcase
2928 end
2929 assign wb_sdram_dat_r = {litedram_wb_dat_r, converter_dat_r[31:16]};
2930 always @(*) begin
2931         converter_skip <= 1'd0;
2932         wb_sdram_ack <= 1'd0;
2933         subfragments_next_state <= 1'd0;
2934         converter_counter_subfragments_next_value <= 1'd0;
2935         converter_counter_subfragments_next_value_ce <= 1'd0;
2936         litedram_wb_adr <= 30'd0;
2937         litedram_wb_sel <= 2'd0;
2938         litedram_wb_cyc <= 1'd0;
2939         litedram_wb_stb <= 1'd0;
2940         litedram_wb_we <= 1'd0;
2941         subfragments_next_state <= subfragments_state;
2942         case (subfragments_state)
2943                 1'd1: begin
2944                         litedram_wb_adr <= {wb_sdram_adr, converter_counter};
2945                         case (converter_counter)
2946                                 1'd0: begin
2947                                         litedram_wb_sel <= wb_sdram_sel[3:0];
2948                                 end
2949                                 1'd1: begin
2950                                         litedram_wb_sel <= wb_sdram_sel[3:2];
2951                                 end
2952                         endcase
2953                         if ((wb_sdram_stb & wb_sdram_cyc)) begin
2954                                 converter_skip <= (litedram_wb_sel == 1'd0);
2955                                 litedram_wb_we <= wb_sdram_we;
2956                                 litedram_wb_cyc <= (~converter_skip);
2957                                 litedram_wb_stb <= (~converter_skip);
2958                                 if ((litedram_wb_ack | converter_skip)) begin
2959                                         converter_counter_subfragments_next_value <= (converter_counter + 1'd1);
2960                                         converter_counter_subfragments_next_value_ce <= 1'd1;
2961                                         if ((converter_counter == 1'd1)) begin
2962                                                 wb_sdram_ack <= 1'd1;
2963                                                 subfragments_next_state <= 1'd0;
2964                                         end
2965                                 end
2966                         end
2967                 end
2968                 default: begin
2969                         converter_counter_subfragments_next_value <= 1'd0;
2970                         converter_counter_subfragments_next_value_ce <= 1'd1;
2971                         if ((wb_sdram_stb & wb_sdram_cyc)) begin
2972                                 subfragments_next_state <= 1'd1;
2973                         end
2974                 end
2975         endcase
2976 end
2977 assign port_cmd_payload_addr = (litedram_wb_adr - 31'd1207959552);
2978 assign port_cmd_payload_we = litedram_wb_we;
2979 assign port_wdata_payload_data = litedram_wb_dat_w;
2980 assign port_wdata_payload_we = litedram_wb_sel;
2981 assign litedram_wb_dat_r = port_rdata_payload_data;
2982 assign port_flush = (~litedram_wb_cyc);
2983 assign port_cmd_last = (~litedram_wb_we);
2984 assign port_cmd_valid = ((litedram_wb_cyc & litedram_wb_stb) & (~cmd_consumed));
2985 assign port_wdata_valid = (((port_cmd_valid | cmd_consumed) & port_cmd_payload_we) & (~wdata_consumed));
2986 assign port_rdata_ready = ((port_cmd_valid | cmd_consumed) & (~port_cmd_payload_we));
2987 assign litedram_wb_ack = (ack_cmd & ((litedram_wb_we & ack_wdata) | ((~litedram_wb_we) & ack_rdata)));
2988 assign ack_cmd = ((port_cmd_valid & port_cmd_ready) | cmd_consumed);
2989 assign ack_wdata = ((port_wdata_valid & port_wdata_ready) | wdata_consumed);
2990 assign ack_rdata = (port_rdata_valid & port_rdata_ready);
2991 assign uart_sink_valid = uart_phy_source_valid;
2992 assign uart_phy_source_ready = uart_sink_ready;
2993 assign uart_sink_first = uart_phy_source_first;
2994 assign uart_sink_last = uart_phy_source_last;
2995 assign uart_sink_payload_data = uart_phy_source_payload_data;
2996 assign uart_phy_sink_valid = uart_source_valid;
2997 assign uart_source_ready = uart_phy_sink_ready;
2998 assign uart_phy_sink_first = uart_source_first;
2999 assign uart_phy_sink_last = uart_source_last;
3000 assign uart_phy_sink_payload_data = uart_source_payload_data;
3001 assign tx_fifo_sink_valid = rxtx_re;
3002 assign tx_fifo_sink_payload_data = rxtx_r;
3003 assign txfull_status = (~tx_fifo_sink_ready);
3004 assign txempty_status = (~tx_fifo_source_valid);
3005 assign uart_source_valid = tx_fifo_source_valid;
3006 assign tx_fifo_source_ready = uart_source_ready;
3007 assign uart_source_first = tx_fifo_source_first;
3008 assign uart_source_last = tx_fifo_source_last;
3009 assign uart_source_payload_data = tx_fifo_source_payload_data;
3010 assign tx_trigger = (~tx_fifo_sink_ready);
3011 assign rx_fifo_sink_valid = uart_sink_valid;
3012 assign uart_sink_ready = rx_fifo_sink_ready;
3013 assign rx_fifo_sink_first = uart_sink_first;
3014 assign rx_fifo_sink_last = uart_sink_last;
3015 assign rx_fifo_sink_payload_data = uart_sink_payload_data;
3016 assign rxempty_status = (~rx_fifo_source_valid);
3017 assign rxfull_status = (~rx_fifo_sink_ready);
3018 assign rxtx_w = rx_fifo_source_payload_data;
3019 assign rx_fifo_source_ready = (rx_clear | (1'd0 & rxtx_we));
3020 assign rx_trigger = (~rx_fifo_source_valid);
3021 always @(*) begin
3022         tx_clear <= 1'd0;
3023         if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin
3024                 tx_clear <= 1'd1;
3025         end
3026 end
3027 always @(*) begin
3028         eventmanager_status_w <= 2'd0;
3029         eventmanager_status_w[0] <= tx_status;
3030         eventmanager_status_w[1] <= rx_status;
3031 end
3032 always @(*) begin
3033         rx_clear <= 1'd0;
3034         if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin
3035                 rx_clear <= 1'd1;
3036         end
3037 end
3038 always @(*) begin
3039         eventmanager_pending_w <= 2'd0;
3040         eventmanager_pending_w[0] <= tx_pending;
3041         eventmanager_pending_w[1] <= rx_pending;
3042 end
3043 assign irq = ((eventmanager_pending_w[0] & eventmanager_storage[0]) | (eventmanager_pending_w[1] & eventmanager_storage[1]));
3044 assign tx_status = tx_trigger;
3045 assign rx_status = rx_trigger;
3046 assign tx_fifo_syncfifo_din = {tx_fifo_fifo_in_last, tx_fifo_fifo_in_first, tx_fifo_fifo_in_payload_data};
3047 assign {tx_fifo_fifo_out_last, tx_fifo_fifo_out_first, tx_fifo_fifo_out_payload_data} = tx_fifo_syncfifo_dout;
3048 assign tx_fifo_sink_ready = tx_fifo_syncfifo_writable;
3049 assign tx_fifo_syncfifo_we = tx_fifo_sink_valid;
3050 assign tx_fifo_fifo_in_first = tx_fifo_sink_first;
3051 assign tx_fifo_fifo_in_last = tx_fifo_sink_last;
3052 assign tx_fifo_fifo_in_payload_data = tx_fifo_sink_payload_data;
3053 assign tx_fifo_source_valid = tx_fifo_readable;
3054 assign tx_fifo_source_first = tx_fifo_fifo_out_first;
3055 assign tx_fifo_source_last = tx_fifo_fifo_out_last;
3056 assign tx_fifo_source_payload_data = tx_fifo_fifo_out_payload_data;
3057 assign tx_fifo_re = tx_fifo_source_ready;
3058 assign tx_fifo_syncfifo_re = (tx_fifo_syncfifo_readable & ((~tx_fifo_readable) | tx_fifo_re));
3059 assign tx_fifo_level1 = (tx_fifo_level0 + tx_fifo_readable);
3060 always @(*) begin
3061         tx_fifo_wrport_adr <= 4'd0;
3062         if (tx_fifo_replace) begin
3063                 tx_fifo_wrport_adr <= (tx_fifo_produce - 1'd1);
3064         end else begin
3065                 tx_fifo_wrport_adr <= tx_fifo_produce;
3066         end
3067 end
3068 assign tx_fifo_wrport_dat_w = tx_fifo_syncfifo_din;
3069 assign tx_fifo_wrport_we = (tx_fifo_syncfifo_we & (tx_fifo_syncfifo_writable | tx_fifo_replace));
3070 assign tx_fifo_do_read = (tx_fifo_syncfifo_readable & tx_fifo_syncfifo_re);
3071 assign tx_fifo_rdport_adr = tx_fifo_consume;
3072 assign tx_fifo_syncfifo_dout = tx_fifo_rdport_dat_r;
3073 assign tx_fifo_rdport_re = tx_fifo_do_read;
3074 assign tx_fifo_syncfifo_writable = (tx_fifo_level0 != 5'd16);
3075 assign tx_fifo_syncfifo_readable = (tx_fifo_level0 != 1'd0);
3076 assign rx_fifo_syncfifo_din = {rx_fifo_fifo_in_last, rx_fifo_fifo_in_first, rx_fifo_fifo_in_payload_data};
3077 assign {rx_fifo_fifo_out_last, rx_fifo_fifo_out_first, rx_fifo_fifo_out_payload_data} = rx_fifo_syncfifo_dout;
3078 assign rx_fifo_sink_ready = rx_fifo_syncfifo_writable;
3079 assign rx_fifo_syncfifo_we = rx_fifo_sink_valid;
3080 assign rx_fifo_fifo_in_first = rx_fifo_sink_first;
3081 assign rx_fifo_fifo_in_last = rx_fifo_sink_last;
3082 assign rx_fifo_fifo_in_payload_data = rx_fifo_sink_payload_data;
3083 assign rx_fifo_source_valid = rx_fifo_readable;
3084 assign rx_fifo_source_first = rx_fifo_fifo_out_first;
3085 assign rx_fifo_source_last = rx_fifo_fifo_out_last;
3086 assign rx_fifo_source_payload_data = rx_fifo_fifo_out_payload_data;
3087 assign rx_fifo_re = rx_fifo_source_ready;
3088 assign rx_fifo_syncfifo_re = (rx_fifo_syncfifo_readable & ((~rx_fifo_readable) | rx_fifo_re));
3089 assign rx_fifo_level1 = (rx_fifo_level0 + rx_fifo_readable);
3090 always @(*) begin
3091         rx_fifo_wrport_adr <= 4'd0;
3092         if (rx_fifo_replace) begin
3093                 rx_fifo_wrport_adr <= (rx_fifo_produce - 1'd1);
3094         end else begin
3095                 rx_fifo_wrport_adr <= rx_fifo_produce;
3096         end
3097 end
3098 assign rx_fifo_wrport_dat_w = rx_fifo_syncfifo_din;
3099 assign rx_fifo_wrport_we = (rx_fifo_syncfifo_we & (rx_fifo_syncfifo_writable | rx_fifo_replace));
3100 assign rx_fifo_do_read = (rx_fifo_syncfifo_readable & rx_fifo_syncfifo_re);
3101 assign rx_fifo_rdport_adr = rx_fifo_consume;
3102 assign rx_fifo_syncfifo_dout = rx_fifo_rdport_dat_r;
3103 assign rx_fifo_rdport_re = rx_fifo_do_read;
3104 assign rx_fifo_syncfifo_writable = (rx_fifo_level0 != 5'd16);
3105 assign rx_fifo_syncfifo_readable = (rx_fifo_level0 != 1'd0);
3106 always @(*) begin
3107         gpio0_pads_gpio0i <= 8'd0;
3108         gpio0_pads_gpio0i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[0];
3109         gpio0_pads_gpio0i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[1];
3110         gpio0_pads_gpio0i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[2];
3111         gpio0_pads_gpio0i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[3];
3112         gpio0_pads_gpio0i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[4];
3113         gpio0_pads_gpio0i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[5];
3114         gpio0_pads_gpio0i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[6];
3115         gpio0_pads_gpio0i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[7];
3116 end
3117 always @(*) begin
3118         gpio1_pads_gpio1i <= 8'd0;
3119         gpio1_pads_gpio1i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[8];
3120         gpio1_pads_gpio1i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[9];
3121         gpio1_pads_gpio1i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[10];
3122         gpio1_pads_gpio1i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[11];
3123         gpio1_pads_gpio1i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[12];
3124         gpio1_pads_gpio1i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[13];
3125         gpio1_pads_gpio1i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[14];
3126         gpio1_pads_gpio1i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[15];
3127 end
3128 always @(*) begin
3129         libresocsim_libresoc_constraintmanager_gpio_o <= 16'd0;
3130         libresocsim_libresoc_constraintmanager_gpio_o[0] <= gpio0_pads_gpio0o[0];
3131         libresocsim_libresoc_constraintmanager_gpio_o[1] <= gpio0_pads_gpio0o[1];
3132         libresocsim_libresoc_constraintmanager_gpio_o[2] <= gpio0_pads_gpio0o[2];
3133         libresocsim_libresoc_constraintmanager_gpio_o[3] <= gpio0_pads_gpio0o[3];
3134         libresocsim_libresoc_constraintmanager_gpio_o[4] <= gpio0_pads_gpio0o[4];
3135         libresocsim_libresoc_constraintmanager_gpio_o[5] <= gpio0_pads_gpio0o[5];
3136         libresocsim_libresoc_constraintmanager_gpio_o[6] <= gpio0_pads_gpio0o[6];
3137         libresocsim_libresoc_constraintmanager_gpio_o[7] <= gpio0_pads_gpio0o[7];
3138         libresocsim_libresoc_constraintmanager_gpio_o[8] <= gpio1_pads_gpio1o[0];
3139         libresocsim_libresoc_constraintmanager_gpio_o[9] <= gpio1_pads_gpio1o[1];
3140         libresocsim_libresoc_constraintmanager_gpio_o[10] <= gpio1_pads_gpio1o[2];
3141         libresocsim_libresoc_constraintmanager_gpio_o[11] <= gpio1_pads_gpio1o[3];
3142         libresocsim_libresoc_constraintmanager_gpio_o[12] <= gpio1_pads_gpio1o[4];
3143         libresocsim_libresoc_constraintmanager_gpio_o[13] <= gpio1_pads_gpio1o[5];
3144         libresocsim_libresoc_constraintmanager_gpio_o[14] <= gpio1_pads_gpio1o[6];
3145         libresocsim_libresoc_constraintmanager_gpio_o[15] <= gpio1_pads_gpio1o[7];
3146 end
3147 always @(*) begin
3148         libresocsim_libresoc_constraintmanager_gpio_oe <= 16'd0;
3149         libresocsim_libresoc_constraintmanager_gpio_oe[0] <= gpio0_pads_gpio0oe[0];
3150         libresocsim_libresoc_constraintmanager_gpio_oe[1] <= gpio0_pads_gpio0oe[1];
3151         libresocsim_libresoc_constraintmanager_gpio_oe[2] <= gpio0_pads_gpio0oe[2];
3152         libresocsim_libresoc_constraintmanager_gpio_oe[3] <= gpio0_pads_gpio0oe[3];
3153         libresocsim_libresoc_constraintmanager_gpio_oe[4] <= gpio0_pads_gpio0oe[4];
3154         libresocsim_libresoc_constraintmanager_gpio_oe[5] <= gpio0_pads_gpio0oe[5];
3155         libresocsim_libresoc_constraintmanager_gpio_oe[6] <= gpio0_pads_gpio0oe[6];
3156         libresocsim_libresoc_constraintmanager_gpio_oe[7] <= gpio0_pads_gpio0oe[7];
3157         libresocsim_libresoc_constraintmanager_gpio_oe[8] <= gpio1_pads_gpio1oe[0];
3158         libresocsim_libresoc_constraintmanager_gpio_oe[9] <= gpio1_pads_gpio1oe[1];
3159         libresocsim_libresoc_constraintmanager_gpio_oe[10] <= gpio1_pads_gpio1oe[2];
3160         libresocsim_libresoc_constraintmanager_gpio_oe[11] <= gpio1_pads_gpio1oe[3];
3161         libresocsim_libresoc_constraintmanager_gpio_oe[12] <= gpio1_pads_gpio1oe[4];
3162         libresocsim_libresoc_constraintmanager_gpio_oe[13] <= gpio1_pads_gpio1oe[5];
3163         libresocsim_libresoc_constraintmanager_gpio_oe[14] <= gpio1_pads_gpio1oe[6];
3164         libresocsim_libresoc_constraintmanager_gpio_oe[15] <= gpio1_pads_gpio1oe[7];
3165 end
3166 assign libresocsim_libresoc_constraintmanager_i2c_scl = i2c_scl_1;
3167 assign libresocsim_libresoc_constraintmanager_i2c_sda_oe = i2c_oe;
3168 assign libresocsim_libresoc_constraintmanager_i2c_sda_o = i2c_sda0;
3169 assign i2c_sda1 = libresocsim_libresoc_constraintmanager_i2c_sda_i;
3170 always @(*) begin
3171         libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0;
3172         libresocsim_libresocsim_wishbone_dat_r <= 32'd0;
3173         libresocsim_next_state <= 2'd0;
3174         libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= 8'd0;
3175         libresocsim_libresocsim_wishbone_ack <= 1'd0;
3176         libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd0;
3177         libresocsim_libresocsim_adr_libresocsim_next_value1 <= 13'd0;
3178         libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0;
3179         libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0;
3180         libresocsim_next_state <= libresocsim_state;
3181         case (libresocsim_state)
3182                 1'd1: begin
3183                         libresocsim_libresocsim_adr_libresocsim_next_value1 <= 1'd0;
3184                         libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1;
3185                         libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0;
3186                         libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1;
3187                         libresocsim_next_state <= 2'd2;
3188                 end
3189                 2'd2: begin
3190                         libresocsim_libresocsim_wishbone_ack <= 1'd1;
3191                         libresocsim_libresocsim_wishbone_dat_r <= libresocsim_libresocsim_dat_r;
3192                         libresocsim_next_state <= 1'd0;
3193                 end
3194                 default: begin
3195                         libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= libresocsim_libresocsim_wishbone_dat_w;
3196                         libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd1;
3197                         if ((libresocsim_libresocsim_wishbone_cyc & libresocsim_libresocsim_wishbone_stb)) begin
3198                                 libresocsim_libresocsim_adr_libresocsim_next_value1 <= libresocsim_libresocsim_wishbone_adr;
3199                                 libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1;
3200                                 libresocsim_libresocsim_we_libresocsim_next_value2 <= (libresocsim_libresocsim_wishbone_we & (libresocsim_libresocsim_wishbone_sel != 1'd0));
3201                                 libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1;
3202                                 libresocsim_next_state <= 1'd1;
3203                         end
3204                 end
3205         endcase
3206 end
3207 assign libresocsim_shared_adr = rhs_array_muxed24;
3208 assign libresocsim_shared_dat_w = rhs_array_muxed25;
3209 assign libresocsim_shared_sel = rhs_array_muxed26;
3210 assign libresocsim_shared_cyc = rhs_array_muxed27;
3211 assign libresocsim_shared_stb = rhs_array_muxed28;
3212 assign libresocsim_shared_we = rhs_array_muxed29;
3213 assign libresocsim_shared_cti = rhs_array_muxed30;
3214 assign libresocsim_shared_bte = rhs_array_muxed31;
3215 assign libresocsim_interface0_converted_interface_dat_r = libresocsim_shared_dat_r;
3216 assign libresocsim_interface1_converted_interface_dat_r = libresocsim_shared_dat_r;
3217 assign libresocsim_libresoc_jtag_wb_dat_r = libresocsim_shared_dat_r;
3218 assign libresocsim_interface0_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd0));
3219 assign libresocsim_interface1_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd1));
3220 assign libresocsim_libresoc_jtag_wb_ack = (libresocsim_shared_ack & (libresocsim_grant == 2'd2));
3221 assign libresocsim_interface0_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd0));
3222 assign libresocsim_interface1_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd1));
3223 assign libresocsim_libresoc_jtag_wb_err = (libresocsim_shared_err & (libresocsim_grant == 2'd2));
3224 assign libresocsim_request = {libresocsim_libresoc_jtag_wb_cyc, libresocsim_interface1_converted_interface_cyc, libresocsim_interface0_converted_interface_cyc};
3225 always @(*) begin
3226         libresocsim_slave_sel <= 10'd0;
3227         libresocsim_slave_sel[0] <= (libresocsim_shared_adr[29:5] == 1'd0);
3228         libresocsim_slave_sel[1] <= (libresocsim_shared_adr[29:5] == 4'd14);
3229         libresocsim_slave_sel[2] <= (libresocsim_shared_adr[29:3] == 27'd100665344);
3230         libresocsim_slave_sel[3] <= (libresocsim_shared_adr[29:10] == 20'd786449);
3231         libresocsim_slave_sel[4] <= (libresocsim_shared_adr[29:10] == 1'd1);
3232         libresocsim_slave_sel[5] <= (libresocsim_shared_adr[29:10] == 2'd2);
3233         libresocsim_slave_sel[6] <= (libresocsim_shared_adr[29:10] == 2'd3);
3234         libresocsim_slave_sel[7] <= (libresocsim_shared_adr[29:10] == 3'd4);
3235         libresocsim_slave_sel[8] <= (libresocsim_shared_adr[29:23] == 7'd72);
3236         libresocsim_slave_sel[9] <= (libresocsim_shared_adr[29:13] == 17'd98304);
3237 end
3238 assign libresocsim_ram_bus_adr = libresocsim_shared_adr;
3239 assign libresocsim_ram_bus_dat_w = libresocsim_shared_dat_w;
3240 assign libresocsim_ram_bus_sel = libresocsim_shared_sel;
3241 assign libresocsim_ram_bus_stb = libresocsim_shared_stb;
3242 assign libresocsim_ram_bus_we = libresocsim_shared_we;
3243 assign libresocsim_ram_bus_cti = libresocsim_shared_cti;
3244 assign libresocsim_ram_bus_bte = libresocsim_shared_bte;
3245 assign ram_bus_ram_bus_adr = libresocsim_shared_adr;
3246 assign ram_bus_ram_bus_dat_w = libresocsim_shared_dat_w;
3247 assign ram_bus_ram_bus_sel = libresocsim_shared_sel;
3248 assign ram_bus_ram_bus_stb = libresocsim_shared_stb;
3249 assign ram_bus_ram_bus_we = libresocsim_shared_we;
3250 assign ram_bus_ram_bus_cti = libresocsim_shared_cti;
3251 assign ram_bus_ram_bus_bte = libresocsim_shared_bte;
3252 assign libresocsim_libresoc_xics_icp_adr = libresocsim_shared_adr;
3253 assign libresocsim_libresoc_xics_icp_dat_w = libresocsim_shared_dat_w;
3254 assign libresocsim_libresoc_xics_icp_sel = libresocsim_shared_sel;
3255 assign libresocsim_libresoc_xics_icp_stb = libresocsim_shared_stb;
3256 assign libresocsim_libresoc_xics_icp_we = libresocsim_shared_we;
3257 assign libresocsim_libresoc_xics_icp_cti = libresocsim_shared_cti;
3258 assign libresocsim_libresoc_xics_icp_bte = libresocsim_shared_bte;
3259 assign libresocsim_libresoc_xics_ics_adr = libresocsim_shared_adr;
3260 assign libresocsim_libresoc_xics_ics_dat_w = libresocsim_shared_dat_w;
3261 assign libresocsim_libresoc_xics_ics_sel = libresocsim_shared_sel;
3262 assign libresocsim_libresoc_xics_ics_stb = libresocsim_shared_stb;
3263 assign libresocsim_libresoc_xics_ics_we = libresocsim_shared_we;
3264 assign libresocsim_libresoc_xics_ics_cti = libresocsim_shared_cti;
3265 assign libresocsim_libresoc_xics_ics_bte = libresocsim_shared_bte;
3266 assign interface0_converted_interface_adr = libresocsim_shared_adr;
3267 assign interface0_converted_interface_dat_w = libresocsim_shared_dat_w;
3268 assign interface0_converted_interface_sel = libresocsim_shared_sel;
3269 assign interface0_converted_interface_stb = libresocsim_shared_stb;
3270 assign interface0_converted_interface_we = libresocsim_shared_we;
3271 assign interface0_converted_interface_cti = libresocsim_shared_cti;
3272 assign interface0_converted_interface_bte = libresocsim_shared_bte;
3273 assign interface1_converted_interface_adr = libresocsim_shared_adr;
3274 assign interface1_converted_interface_dat_w = libresocsim_shared_dat_w;
3275 assign interface1_converted_interface_sel = libresocsim_shared_sel;
3276 assign interface1_converted_interface_stb = libresocsim_shared_stb;
3277 assign interface1_converted_interface_we = libresocsim_shared_we;
3278 assign interface1_converted_interface_cti = libresocsim_shared_cti;
3279 assign interface1_converted_interface_bte = libresocsim_shared_bte;
3280 assign interface2_converted_interface_adr = libresocsim_shared_adr;
3281 assign interface2_converted_interface_dat_w = libresocsim_shared_dat_w;
3282 assign interface2_converted_interface_sel = libresocsim_shared_sel;
3283 assign interface2_converted_interface_stb = libresocsim_shared_stb;
3284 assign interface2_converted_interface_we = libresocsim_shared_we;
3285 assign interface2_converted_interface_cti = libresocsim_shared_cti;
3286 assign interface2_converted_interface_bte = libresocsim_shared_bte;
3287 assign interface3_converted_interface_adr = libresocsim_shared_adr;
3288 assign interface3_converted_interface_dat_w = libresocsim_shared_dat_w;
3289 assign interface3_converted_interface_sel = libresocsim_shared_sel;
3290 assign interface3_converted_interface_stb = libresocsim_shared_stb;
3291 assign interface3_converted_interface_we = libresocsim_shared_we;
3292 assign interface3_converted_interface_cti = libresocsim_shared_cti;
3293 assign interface3_converted_interface_bte = libresocsim_shared_bte;
3294 assign wb_sdram_adr = libresocsim_shared_adr;
3295 assign wb_sdram_dat_w = libresocsim_shared_dat_w;
3296 assign wb_sdram_sel = libresocsim_shared_sel;
3297 assign wb_sdram_stb = libresocsim_shared_stb;
3298 assign wb_sdram_we = libresocsim_shared_we;
3299 assign wb_sdram_cti = libresocsim_shared_cti;
3300 assign wb_sdram_bte = libresocsim_shared_bte;
3301 assign libresocsim_libresocsim_wishbone_adr = libresocsim_shared_adr;
3302 assign libresocsim_libresocsim_wishbone_dat_w = libresocsim_shared_dat_w;
3303 assign libresocsim_libresocsim_wishbone_sel = libresocsim_shared_sel;
3304 assign libresocsim_libresocsim_wishbone_stb = libresocsim_shared_stb;
3305 assign libresocsim_libresocsim_wishbone_we = libresocsim_shared_we;
3306 assign libresocsim_libresocsim_wishbone_cti = libresocsim_shared_cti;
3307 assign libresocsim_libresocsim_wishbone_bte = libresocsim_shared_bte;
3308 assign libresocsim_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[0]);
3309 assign ram_bus_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[1]);
3310 assign libresocsim_libresoc_xics_icp_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[2]);
3311 assign libresocsim_libresoc_xics_ics_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[3]);
3312 assign interface0_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[4]);
3313 assign interface1_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[5]);
3314 assign interface2_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[6]);
3315 assign interface3_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[7]);
3316 assign wb_sdram_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[8]);
3317 assign libresocsim_libresocsim_wishbone_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[9]);
3318 assign libresocsim_shared_err = (((((((((libresocsim_ram_bus_err | ram_bus_ram_bus_err) | libresocsim_libresoc_xics_icp_err) | libresocsim_libresoc_xics_ics_err) | interface0_converted_interface_err) | interface1_converted_interface_err) | interface2_converted_interface_err) | interface3_converted_interface_err) | wb_sdram_err) | libresocsim_libresocsim_wishbone_err);
3319 assign libresocsim_wait = ((libresocsim_shared_stb & libresocsim_shared_cyc) & (~libresocsim_shared_ack));
3320 always @(*) begin
3321         libresocsim_shared_dat_r <= 32'd0;
3322         libresocsim_shared_ack <= 1'd0;
3323         libresocsim_error <= 1'd0;
3324         libresocsim_shared_ack <= (((((((((libresocsim_ram_bus_ack | ram_bus_ram_bus_ack) | libresocsim_libresoc_xics_icp_ack) | libresocsim_libresoc_xics_ics_ack) | interface0_converted_interface_ack) | interface1_converted_interface_ack) | interface2_converted_interface_ack) | interface3_converted_interface_ack) | wb_sdram_ack) | libresocsim_libresocsim_wishbone_ack);
3325         libresocsim_shared_dat_r <= (((((((((({32{libresocsim_slave_sel_r[0]}} & libresocsim_ram_bus_dat_r) | ({32{libresocsim_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{libresocsim_slave_sel_r[2]}} & libresocsim_libresoc_xics_icp_dat_r)) | ({32{libresocsim_slave_sel_r[3]}} & libresocsim_libresoc_xics_ics_dat_r)) | ({32{libresocsim_slave_sel_r[4]}} & interface0_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[5]}} & interface1_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[6]}} & interface2_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[7]}} & interface3_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[8]}} & wb_sdram_dat_r)) | ({32{libresocsim_slave_sel_r[9]}} & libresocsim_libresocsim_wishbone_dat_r));
3326         if (libresocsim_done) begin
3327                 libresocsim_shared_dat_r <= 32'd4294967295;
3328                 libresocsim_shared_ack <= 1'd1;
3329                 libresocsim_error <= 1'd1;
3330         end
3331 end
3332 assign libresocsim_done = (libresocsim_count == 1'd0);
3333 assign libresocsim_csrbank0_sel = (libresocsim_interface0_bank_bus_adr[12:9] == 1'd0);
3334 assign libresocsim_csrbank0_reset0_r = libresocsim_interface0_bank_bus_dat_w[0];
3335 assign libresocsim_csrbank0_reset0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0));
3336 assign libresocsim_csrbank0_reset0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0));
3337 assign libresocsim_csrbank0_scratch3_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3338 assign libresocsim_csrbank0_scratch3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1));
3339 assign libresocsim_csrbank0_scratch3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1));
3340 assign libresocsim_csrbank0_scratch2_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3341 assign libresocsim_csrbank0_scratch2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2));
3342 assign libresocsim_csrbank0_scratch2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2));
3343 assign libresocsim_csrbank0_scratch1_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3344 assign libresocsim_csrbank0_scratch1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3));
3345 assign libresocsim_csrbank0_scratch1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3));
3346 assign libresocsim_csrbank0_scratch0_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3347 assign libresocsim_csrbank0_scratch0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4));
3348 assign libresocsim_csrbank0_scratch0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4));
3349 assign libresocsim_csrbank0_bus_errors3_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3350 assign libresocsim_csrbank0_bus_errors3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5));
3351 assign libresocsim_csrbank0_bus_errors3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5));
3352 assign libresocsim_csrbank0_bus_errors2_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3353 assign libresocsim_csrbank0_bus_errors2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6));
3354 assign libresocsim_csrbank0_bus_errors2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6));
3355 assign libresocsim_csrbank0_bus_errors1_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3356 assign libresocsim_csrbank0_bus_errors1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7));
3357 assign libresocsim_csrbank0_bus_errors1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7));
3358 assign libresocsim_csrbank0_bus_errors0_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3359 assign libresocsim_csrbank0_bus_errors0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8));
3360 assign libresocsim_csrbank0_bus_errors0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8));
3361 assign libresocsim_csrbank0_reset0_w = libresocsim_reset_storage;
3362 assign libresocsim_csrbank0_scratch3_w = libresocsim_scratch_storage[31:24];
3363 assign libresocsim_csrbank0_scratch2_w = libresocsim_scratch_storage[23:16];
3364 assign libresocsim_csrbank0_scratch1_w = libresocsim_scratch_storage[15:8];
3365 assign libresocsim_csrbank0_scratch0_w = libresocsim_scratch_storage[7:0];
3366 assign libresocsim_csrbank0_bus_errors3_w = libresocsim_bus_errors_status[31:24];
3367 assign libresocsim_csrbank0_bus_errors2_w = libresocsim_bus_errors_status[23:16];
3368 assign libresocsim_csrbank0_bus_errors1_w = libresocsim_bus_errors_status[15:8];
3369 assign libresocsim_csrbank0_bus_errors0_w = libresocsim_bus_errors_status[7:0];
3370 assign libresocsim_bus_errors_we = libresocsim_csrbank0_bus_errors0_we;
3371 assign libresocsim_csrbank1_sel = (libresocsim_interface1_bank_bus_adr[12:9] == 3'd6);
3372 assign libresocsim_csrbank1_oe0_r = libresocsim_interface1_bank_bus_dat_w[7:0];
3373 assign libresocsim_csrbank1_oe0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0));
3374 assign libresocsim_csrbank1_oe0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0));
3375 assign libresocsim_csrbank1_in_r = libresocsim_interface1_bank_bus_dat_w[7:0];
3376 assign libresocsim_csrbank1_in_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1));
3377 assign libresocsim_csrbank1_in_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1));
3378 assign libresocsim_csrbank1_out0_r = libresocsim_interface1_bank_bus_dat_w[7:0];
3379 assign libresocsim_csrbank1_out0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2));
3380 assign libresocsim_csrbank1_out0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2));
3381 assign libresocsim_csrbank1_oe0_w = gpio0_oe_storage[7:0];
3382 assign libresocsim_csrbank1_in_w = gpio0_status[7:0];
3383 assign gpio0_we = libresocsim_csrbank1_in_we;
3384 assign libresocsim_csrbank1_out0_w = gpio0_out_storage[7:0];
3385 assign libresocsim_csrbank2_sel = (libresocsim_interface2_bank_bus_adr[12:9] == 3'd7);
3386 assign libresocsim_csrbank2_oe0_r = libresocsim_interface2_bank_bus_dat_w[7:0];
3387 assign libresocsim_csrbank2_oe0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0));
3388 assign libresocsim_csrbank2_oe0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0));
3389 assign libresocsim_csrbank2_in_r = libresocsim_interface2_bank_bus_dat_w[7:0];
3390 assign libresocsim_csrbank2_in_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1));
3391 assign libresocsim_csrbank2_in_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1));
3392 assign libresocsim_csrbank2_out0_r = libresocsim_interface2_bank_bus_dat_w[7:0];
3393 assign libresocsim_csrbank2_out0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2));
3394 assign libresocsim_csrbank2_out0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2));
3395 assign libresocsim_csrbank2_oe0_w = gpio1_oe_storage[7:0];
3396 assign libresocsim_csrbank2_in_w = gpio1_status[7:0];
3397 assign gpio1_we = libresocsim_csrbank2_in_we;
3398 assign libresocsim_csrbank2_out0_w = gpio1_out_storage[7:0];
3399 assign libresocsim_csrbank3_sel = (libresocsim_interface3_bank_bus_adr[12:9] == 4'd8);
3400 assign libresocsim_csrbank3_w0_r = libresocsim_interface3_bank_bus_dat_w[2:0];
3401 assign libresocsim_csrbank3_w0_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0));
3402 assign libresocsim_csrbank3_w0_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0));
3403 assign libresocsim_csrbank3_r_r = libresocsim_interface3_bank_bus_dat_w[0];
3404 assign libresocsim_csrbank3_r_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1));
3405 assign libresocsim_csrbank3_r_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1));
3406 assign i2c_scl_1 = i2c_storage[0];
3407 assign i2c_oe = i2c_storage[1];
3408 assign i2c_sda0 = i2c_storage[2];
3409 assign libresocsim_csrbank3_w0_w = i2c_storage[2:0];
3410 assign i2c_status = i2c_sda1;
3411 assign libresocsim_csrbank3_r_w = i2c_status;
3412 assign i2c_we = libresocsim_csrbank3_r_we;
3413 assign libresocsim_csrbank4_sel = (libresocsim_interface4_bank_bus_adr[12:9] == 2'd3);
3414 assign libresocsim_csrbank4_dfii_control0_r = libresocsim_interface4_bank_bus_dat_w[3:0];
3415 assign libresocsim_csrbank4_dfii_control0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0));
3416 assign libresocsim_csrbank4_dfii_control0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0));
3417 assign libresocsim_csrbank4_dfii_pi0_command0_r = libresocsim_interface4_bank_bus_dat_w[5:0];
3418 assign libresocsim_csrbank4_dfii_pi0_command0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1));
3419 assign libresocsim_csrbank4_dfii_pi0_command0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1));
3420 assign sdram_command_issue_r = libresocsim_interface4_bank_bus_dat_w[0];
3421 assign sdram_command_issue_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2));
3422 assign sdram_command_issue_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2));
3423 assign libresocsim_csrbank4_dfii_pi0_address1_r = libresocsim_interface4_bank_bus_dat_w[4:0];
3424 assign libresocsim_csrbank4_dfii_pi0_address1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3));
3425 assign libresocsim_csrbank4_dfii_pi0_address1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3));
3426 assign libresocsim_csrbank4_dfii_pi0_address0_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3427 assign libresocsim_csrbank4_dfii_pi0_address0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4));
3428 assign libresocsim_csrbank4_dfii_pi0_address0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4));
3429 assign libresocsim_csrbank4_dfii_pi0_baddress0_r = libresocsim_interface4_bank_bus_dat_w[1:0];
3430 assign libresocsim_csrbank4_dfii_pi0_baddress0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5));
3431 assign libresocsim_csrbank4_dfii_pi0_baddress0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5));
3432 assign libresocsim_csrbank4_dfii_pi0_wrdata1_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3433 assign libresocsim_csrbank4_dfii_pi0_wrdata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6));
3434 assign libresocsim_csrbank4_dfii_pi0_wrdata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6));
3435 assign libresocsim_csrbank4_dfii_pi0_wrdata0_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3436 assign libresocsim_csrbank4_dfii_pi0_wrdata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7));
3437 assign libresocsim_csrbank4_dfii_pi0_wrdata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7));
3438 assign libresocsim_csrbank4_dfii_pi0_rddata1_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3439 assign libresocsim_csrbank4_dfii_pi0_rddata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8));
3440 assign libresocsim_csrbank4_dfii_pi0_rddata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8));
3441 assign libresocsim_csrbank4_dfii_pi0_rddata0_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3442 assign libresocsim_csrbank4_dfii_pi0_rddata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9));
3443 assign libresocsim_csrbank4_dfii_pi0_rddata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9));
3444 assign sdram_sel = sdram_storage[0];
3445 assign sdram_cke_1 = sdram_storage[1];
3446 assign sdram_odt = sdram_storage[2];
3447 assign sdram_reset_n = sdram_storage[3];
3448 assign libresocsim_csrbank4_dfii_control0_w = sdram_storage[3:0];
3449 assign libresocsim_csrbank4_dfii_pi0_command0_w = sdram_command_storage[5:0];
3450 assign libresocsim_csrbank4_dfii_pi0_address1_w = sdram_address_storage[12:8];
3451 assign libresocsim_csrbank4_dfii_pi0_address0_w = sdram_address_storage[7:0];
3452 assign libresocsim_csrbank4_dfii_pi0_baddress0_w = sdram_baddress_storage[1:0];
3453 assign libresocsim_csrbank4_dfii_pi0_wrdata1_w = sdram_wrdata_storage[15:8];
3454 assign libresocsim_csrbank4_dfii_pi0_wrdata0_w = sdram_wrdata_storage[7:0];
3455 assign libresocsim_csrbank4_dfii_pi0_rddata1_w = sdram_status[15:8];
3456 assign libresocsim_csrbank4_dfii_pi0_rddata0_w = sdram_status[7:0];
3457 assign sdram_we = libresocsim_csrbank4_dfii_pi0_rddata0_we;
3458 assign libresocsim_csrbank5_sel = (libresocsim_interface5_bank_bus_adr[12:9] == 2'd2);
3459 assign libresocsim_csrbank5_load3_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3460 assign libresocsim_csrbank5_load3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0));
3461 assign libresocsim_csrbank5_load3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0));
3462 assign libresocsim_csrbank5_load2_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3463 assign libresocsim_csrbank5_load2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1));
3464 assign libresocsim_csrbank5_load2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1));
3465 assign libresocsim_csrbank5_load1_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3466 assign libresocsim_csrbank5_load1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2));
3467 assign libresocsim_csrbank5_load1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2));
3468 assign libresocsim_csrbank5_load0_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3469 assign libresocsim_csrbank5_load0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3));
3470 assign libresocsim_csrbank5_load0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3));
3471 assign libresocsim_csrbank5_reload3_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3472 assign libresocsim_csrbank5_reload3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4));
3473 assign libresocsim_csrbank5_reload3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4));
3474 assign libresocsim_csrbank5_reload2_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3475 assign libresocsim_csrbank5_reload2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5));
3476 assign libresocsim_csrbank5_reload2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5));
3477 assign libresocsim_csrbank5_reload1_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3478 assign libresocsim_csrbank5_reload1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6));
3479 assign libresocsim_csrbank5_reload1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6));
3480 assign libresocsim_csrbank5_reload0_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3481 assign libresocsim_csrbank5_reload0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7));
3482 assign libresocsim_csrbank5_reload0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7));
3483 assign libresocsim_csrbank5_en0_r = libresocsim_interface5_bank_bus_dat_w[0];
3484 assign libresocsim_csrbank5_en0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8));
3485 assign libresocsim_csrbank5_en0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8));
3486 assign libresocsim_csrbank5_update_value0_r = libresocsim_interface5_bank_bus_dat_w[0];
3487 assign libresocsim_csrbank5_update_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9));
3488 assign libresocsim_csrbank5_update_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9));
3489 assign libresocsim_csrbank5_value3_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3490 assign libresocsim_csrbank5_value3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10));
3491 assign libresocsim_csrbank5_value3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10));
3492 assign libresocsim_csrbank5_value2_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3493 assign libresocsim_csrbank5_value2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11));
3494 assign libresocsim_csrbank5_value2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11));
3495 assign libresocsim_csrbank5_value1_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3496 assign libresocsim_csrbank5_value1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12));
3497 assign libresocsim_csrbank5_value1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12));
3498 assign libresocsim_csrbank5_value0_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3499 assign libresocsim_csrbank5_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13));
3500 assign libresocsim_csrbank5_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13));
3501 assign libresocsim_eventmanager_status_r = libresocsim_interface5_bank_bus_dat_w[0];
3502 assign libresocsim_eventmanager_status_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14));
3503 assign libresocsim_eventmanager_status_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14));
3504 assign libresocsim_eventmanager_pending_r = libresocsim_interface5_bank_bus_dat_w[0];
3505 assign libresocsim_eventmanager_pending_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15));
3506 assign libresocsim_eventmanager_pending_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15));
3507 assign libresocsim_csrbank5_ev_enable0_r = libresocsim_interface5_bank_bus_dat_w[0];
3508 assign libresocsim_csrbank5_ev_enable0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16));
3509 assign libresocsim_csrbank5_ev_enable0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16));
3510 assign libresocsim_csrbank5_load3_w = libresocsim_load_storage[31:24];
3511 assign libresocsim_csrbank5_load2_w = libresocsim_load_storage[23:16];
3512 assign libresocsim_csrbank5_load1_w = libresocsim_load_storage[15:8];
3513 assign libresocsim_csrbank5_load0_w = libresocsim_load_storage[7:0];
3514 assign libresocsim_csrbank5_reload3_w = libresocsim_reload_storage[31:24];
3515 assign libresocsim_csrbank5_reload2_w = libresocsim_reload_storage[23:16];
3516 assign libresocsim_csrbank5_reload1_w = libresocsim_reload_storage[15:8];
3517 assign libresocsim_csrbank5_reload0_w = libresocsim_reload_storage[7:0];
3518 assign libresocsim_csrbank5_en0_w = libresocsim_en_storage;
3519 assign libresocsim_csrbank5_update_value0_w = libresocsim_update_value_storage;
3520 assign libresocsim_csrbank5_value3_w = libresocsim_value_status[31:24];
3521 assign libresocsim_csrbank5_value2_w = libresocsim_value_status[23:16];
3522 assign libresocsim_csrbank5_value1_w = libresocsim_value_status[15:8];
3523 assign libresocsim_csrbank5_value0_w = libresocsim_value_status[7:0];
3524 assign libresocsim_value_we = libresocsim_csrbank5_value0_we;
3525 assign libresocsim_csrbank5_ev_enable0_w = libresocsim_eventmanager_storage;
3526 assign libresocsim_csrbank6_sel = (libresocsim_interface6_bank_bus_adr[12:9] == 3'd5);
3527 assign rxtx_r = libresocsim_interface6_bank_bus_dat_w[7:0];
3528 assign rxtx_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0));
3529 assign rxtx_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0));
3530 assign libresocsim_csrbank6_txfull_r = libresocsim_interface6_bank_bus_dat_w[0];
3531 assign libresocsim_csrbank6_txfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1));
3532 assign libresocsim_csrbank6_txfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1));
3533 assign libresocsim_csrbank6_rxempty_r = libresocsim_interface6_bank_bus_dat_w[0];
3534 assign libresocsim_csrbank6_rxempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2));
3535 assign libresocsim_csrbank6_rxempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2));
3536 assign eventmanager_status_r = libresocsim_interface6_bank_bus_dat_w[1:0];
3537 assign eventmanager_status_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3));
3538 assign eventmanager_status_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3));
3539 assign eventmanager_pending_r = libresocsim_interface6_bank_bus_dat_w[1:0];
3540 assign eventmanager_pending_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4));
3541 assign eventmanager_pending_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4));
3542 assign libresocsim_csrbank6_ev_enable0_r = libresocsim_interface6_bank_bus_dat_w[1:0];
3543 assign libresocsim_csrbank6_ev_enable0_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5));
3544 assign libresocsim_csrbank6_ev_enable0_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5));
3545 assign libresocsim_csrbank6_txempty_r = libresocsim_interface6_bank_bus_dat_w[0];
3546 assign libresocsim_csrbank6_txempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6));
3547 assign libresocsim_csrbank6_txempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6));
3548 assign libresocsim_csrbank6_rxfull_r = libresocsim_interface6_bank_bus_dat_w[0];
3549 assign libresocsim_csrbank6_rxfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7));
3550 assign libresocsim_csrbank6_rxfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7));
3551 assign libresocsim_csrbank6_txfull_w = txfull_status;
3552 assign txfull_we = libresocsim_csrbank6_txfull_we;
3553 assign libresocsim_csrbank6_rxempty_w = rxempty_status;
3554 assign rxempty_we = libresocsim_csrbank6_rxempty_we;
3555 assign libresocsim_csrbank6_ev_enable0_w = eventmanager_storage[1:0];
3556 assign libresocsim_csrbank6_txempty_w = txempty_status;
3557 assign txempty_we = libresocsim_csrbank6_txempty_we;
3558 assign libresocsim_csrbank6_rxfull_w = rxfull_status;
3559 assign rxfull_we = libresocsim_csrbank6_rxfull_we;
3560 assign libresocsim_csrbank7_sel = (libresocsim_interface7_bank_bus_adr[12:9] == 3'd4);
3561 assign libresocsim_csrbank7_tuning_word3_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3562 assign libresocsim_csrbank7_tuning_word3_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0));
3563 assign libresocsim_csrbank7_tuning_word3_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0));
3564 assign libresocsim_csrbank7_tuning_word2_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3565 assign libresocsim_csrbank7_tuning_word2_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1));
3566 assign libresocsim_csrbank7_tuning_word2_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1));
3567 assign libresocsim_csrbank7_tuning_word1_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3568 assign libresocsim_csrbank7_tuning_word1_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2));
3569 assign libresocsim_csrbank7_tuning_word1_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2));
3570 assign libresocsim_csrbank7_tuning_word0_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3571 assign libresocsim_csrbank7_tuning_word0_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3));
3572 assign libresocsim_csrbank7_tuning_word0_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3));
3573 assign libresocsim_csrbank7_tuning_word3_w = uart_phy_storage[31:24];
3574 assign libresocsim_csrbank7_tuning_word2_w = uart_phy_storage[23:16];
3575 assign libresocsim_csrbank7_tuning_word1_w = uart_phy_storage[15:8];
3576 assign libresocsim_csrbank7_tuning_word0_w = uart_phy_storage[7:0];
3577 assign libresocsim_csr_interconnect_adr = libresocsim_libresocsim_adr;
3578 assign libresocsim_csr_interconnect_we = libresocsim_libresocsim_we;
3579 assign libresocsim_csr_interconnect_dat_w = libresocsim_libresocsim_dat_w;
3580 assign libresocsim_libresocsim_dat_r = libresocsim_csr_interconnect_dat_r;
3581 assign libresocsim_interface0_bank_bus_adr = libresocsim_csr_interconnect_adr;
3582 assign libresocsim_interface1_bank_bus_adr = libresocsim_csr_interconnect_adr;
3583 assign libresocsim_interface2_bank_bus_adr = libresocsim_csr_interconnect_adr;
3584 assign libresocsim_interface3_bank_bus_adr = libresocsim_csr_interconnect_adr;
3585 assign libresocsim_interface4_bank_bus_adr = libresocsim_csr_interconnect_adr;
3586 assign libresocsim_interface5_bank_bus_adr = libresocsim_csr_interconnect_adr;
3587 assign libresocsim_interface6_bank_bus_adr = libresocsim_csr_interconnect_adr;
3588 assign libresocsim_interface7_bank_bus_adr = libresocsim_csr_interconnect_adr;
3589 assign libresocsim_interface0_bank_bus_we = libresocsim_csr_interconnect_we;
3590 assign libresocsim_interface1_bank_bus_we = libresocsim_csr_interconnect_we;
3591 assign libresocsim_interface2_bank_bus_we = libresocsim_csr_interconnect_we;
3592 assign libresocsim_interface3_bank_bus_we = libresocsim_csr_interconnect_we;
3593 assign libresocsim_interface4_bank_bus_we = libresocsim_csr_interconnect_we;
3594 assign libresocsim_interface5_bank_bus_we = libresocsim_csr_interconnect_we;
3595 assign libresocsim_interface6_bank_bus_we = libresocsim_csr_interconnect_we;
3596 assign libresocsim_interface7_bank_bus_we = libresocsim_csr_interconnect_we;
3597 assign libresocsim_interface0_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3598 assign libresocsim_interface1_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3599 assign libresocsim_interface2_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3600 assign libresocsim_interface3_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3601 assign libresocsim_interface4_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3602 assign libresocsim_interface5_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3603 assign libresocsim_interface6_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3604 assign libresocsim_interface7_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3605 assign libresocsim_csr_interconnect_dat_r = (((((((libresocsim_interface0_bank_bus_dat_r | libresocsim_interface1_bank_bus_dat_r) | libresocsim_interface2_bank_bus_dat_r) | libresocsim_interface3_bank_bus_dat_r) | libresocsim_interface4_bank_bus_dat_r) | libresocsim_interface5_bank_bus_dat_r) | libresocsim_interface6_bank_bus_dat_r) | libresocsim_interface7_bank_bus_dat_r);
3606 always @(*) begin
3607         rhs_array_muxed0 <= 1'd0;
3608         case (sdram_choose_cmd_grant)
3609                 1'd0: begin
3610                         rhs_array_muxed0 <= sdram_choose_cmd_valids[0];
3611                 end
3612                 1'd1: begin
3613                         rhs_array_muxed0 <= sdram_choose_cmd_valids[1];
3614                 end
3615                 2'd2: begin
3616                         rhs_array_muxed0 <= sdram_choose_cmd_valids[2];
3617                 end
3618                 default: begin
3619                         rhs_array_muxed0 <= sdram_choose_cmd_valids[3];
3620                 end
3621         endcase
3622 end
3623 always @(*) begin
3624         rhs_array_muxed1 <= 13'd0;
3625         case (sdram_choose_cmd_grant)
3626                 1'd0: begin
3627                         rhs_array_muxed1 <= sdram_bankmachine0_cmd_payload_a;
3628                 end
3629                 1'd1: begin
3630                         rhs_array_muxed1 <= sdram_bankmachine1_cmd_payload_a;
3631                 end
3632                 2'd2: begin
3633                         rhs_array_muxed1 <= sdram_bankmachine2_cmd_payload_a;
3634                 end
3635                 default: begin
3636                         rhs_array_muxed1 <= sdram_bankmachine3_cmd_payload_a;
3637                 end
3638         endcase
3639 end
3640 always @(*) begin
3641         rhs_array_muxed2 <= 2'd0;
3642         case (sdram_choose_cmd_grant)
3643                 1'd0: begin
3644                         rhs_array_muxed2 <= sdram_bankmachine0_cmd_payload_ba;
3645                 end
3646                 1'd1: begin
3647                         rhs_array_muxed2 <= sdram_bankmachine1_cmd_payload_ba;
3648                 end
3649                 2'd2: begin
3650                         rhs_array_muxed2 <= sdram_bankmachine2_cmd_payload_ba;
3651                 end
3652                 default: begin
3653                         rhs_array_muxed2 <= sdram_bankmachine3_cmd_payload_ba;
3654                 end
3655         endcase
3656 end
3657 always @(*) begin
3658         rhs_array_muxed3 <= 1'd0;
3659         case (sdram_choose_cmd_grant)
3660                 1'd0: begin
3661                         rhs_array_muxed3 <= sdram_bankmachine0_cmd_payload_is_read;
3662                 end
3663                 1'd1: begin
3664                         rhs_array_muxed3 <= sdram_bankmachine1_cmd_payload_is_read;
3665                 end
3666                 2'd2: begin
3667                         rhs_array_muxed3 <= sdram_bankmachine2_cmd_payload_is_read;
3668                 end
3669                 default: begin
3670                         rhs_array_muxed3 <= sdram_bankmachine3_cmd_payload_is_read;
3671                 end
3672         endcase
3673 end
3674 always @(*) begin
3675         rhs_array_muxed4 <= 1'd0;
3676         case (sdram_choose_cmd_grant)
3677                 1'd0: begin
3678                         rhs_array_muxed4 <= sdram_bankmachine0_cmd_payload_is_write;
3679                 end
3680                 1'd1: begin
3681                         rhs_array_muxed4 <= sdram_bankmachine1_cmd_payload_is_write;
3682                 end
3683                 2'd2: begin
3684                         rhs_array_muxed4 <= sdram_bankmachine2_cmd_payload_is_write;
3685                 end
3686                 default: begin
3687                         rhs_array_muxed4 <= sdram_bankmachine3_cmd_payload_is_write;
3688                 end
3689         endcase
3690 end
3691 always @(*) begin
3692         rhs_array_muxed5 <= 1'd0;
3693         case (sdram_choose_cmd_grant)
3694                 1'd0: begin
3695                         rhs_array_muxed5 <= sdram_bankmachine0_cmd_payload_is_cmd;
3696                 end
3697                 1'd1: begin
3698                         rhs_array_muxed5 <= sdram_bankmachine1_cmd_payload_is_cmd;
3699                 end
3700                 2'd2: begin
3701                         rhs_array_muxed5 <= sdram_bankmachine2_cmd_payload_is_cmd;
3702                 end
3703                 default: begin
3704                         rhs_array_muxed5 <= sdram_bankmachine3_cmd_payload_is_cmd;
3705                 end
3706         endcase
3707 end
3708 always @(*) begin
3709         t_array_muxed0 <= 1'd0;
3710         case (sdram_choose_cmd_grant)
3711                 1'd0: begin
3712                         t_array_muxed0 <= sdram_bankmachine0_cmd_payload_cas;
3713                 end
3714                 1'd1: begin
3715                         t_array_muxed0 <= sdram_bankmachine1_cmd_payload_cas;
3716                 end
3717                 2'd2: begin
3718                         t_array_muxed0 <= sdram_bankmachine2_cmd_payload_cas;
3719                 end
3720                 default: begin
3721                         t_array_muxed0 <= sdram_bankmachine3_cmd_payload_cas;
3722                 end
3723         endcase
3724 end
3725 always @(*) begin
3726         t_array_muxed1 <= 1'd0;
3727         case (sdram_choose_cmd_grant)
3728                 1'd0: begin
3729                         t_array_muxed1 <= sdram_bankmachine0_cmd_payload_ras;
3730                 end
3731                 1'd1: begin
3732                         t_array_muxed1 <= sdram_bankmachine1_cmd_payload_ras;
3733                 end
3734                 2'd2: begin
3735                         t_array_muxed1 <= sdram_bankmachine2_cmd_payload_ras;
3736                 end
3737                 default: begin
3738                         t_array_muxed1 <= sdram_bankmachine3_cmd_payload_ras;
3739                 end
3740         endcase
3741 end
3742 always @(*) begin
3743         t_array_muxed2 <= 1'd0;
3744         case (sdram_choose_cmd_grant)
3745                 1'd0: begin
3746                         t_array_muxed2 <= sdram_bankmachine0_cmd_payload_we;
3747                 end
3748                 1'd1: begin
3749                         t_array_muxed2 <= sdram_bankmachine1_cmd_payload_we;
3750                 end
3751                 2'd2: begin
3752                         t_array_muxed2 <= sdram_bankmachine2_cmd_payload_we;
3753                 end
3754                 default: begin
3755                         t_array_muxed2 <= sdram_bankmachine3_cmd_payload_we;
3756                 end
3757         endcase
3758 end
3759 always @(*) begin
3760         rhs_array_muxed6 <= 1'd0;
3761         case (sdram_choose_req_grant)
3762                 1'd0: begin
3763                         rhs_array_muxed6 <= sdram_choose_req_valids[0];
3764                 end
3765                 1'd1: begin
3766                         rhs_array_muxed6 <= sdram_choose_req_valids[1];
3767                 end
3768                 2'd2: begin
3769                         rhs_array_muxed6 <= sdram_choose_req_valids[2];
3770                 end
3771                 default: begin
3772                         rhs_array_muxed6 <= sdram_choose_req_valids[3];
3773                 end
3774         endcase
3775 end
3776 always @(*) begin
3777         rhs_array_muxed7 <= 13'd0;
3778         case (sdram_choose_req_grant)
3779                 1'd0: begin
3780                         rhs_array_muxed7 <= sdram_bankmachine0_cmd_payload_a;
3781                 end
3782                 1'd1: begin
3783                         rhs_array_muxed7 <= sdram_bankmachine1_cmd_payload_a;
3784                 end
3785                 2'd2: begin
3786                         rhs_array_muxed7 <= sdram_bankmachine2_cmd_payload_a;
3787                 end
3788                 default: begin
3789                         rhs_array_muxed7 <= sdram_bankmachine3_cmd_payload_a;
3790                 end
3791         endcase
3792 end
3793 always @(*) begin
3794         rhs_array_muxed8 <= 2'd0;
3795         case (sdram_choose_req_grant)
3796                 1'd0: begin
3797                         rhs_array_muxed8 <= sdram_bankmachine0_cmd_payload_ba;
3798                 end
3799                 1'd1: begin
3800                         rhs_array_muxed8 <= sdram_bankmachine1_cmd_payload_ba;
3801                 end
3802                 2'd2: begin
3803                         rhs_array_muxed8 <= sdram_bankmachine2_cmd_payload_ba;
3804                 end
3805                 default: begin
3806                         rhs_array_muxed8 <= sdram_bankmachine3_cmd_payload_ba;
3807                 end
3808         endcase
3809 end
3810 always @(*) begin
3811         rhs_array_muxed9 <= 1'd0;
3812         case (sdram_choose_req_grant)
3813                 1'd0: begin
3814                         rhs_array_muxed9 <= sdram_bankmachine0_cmd_payload_is_read;
3815                 end
3816                 1'd1: begin
3817                         rhs_array_muxed9 <= sdram_bankmachine1_cmd_payload_is_read;
3818                 end
3819                 2'd2: begin
3820                         rhs_array_muxed9 <= sdram_bankmachine2_cmd_payload_is_read;
3821                 end
3822                 default: begin
3823                         rhs_array_muxed9 <= sdram_bankmachine3_cmd_payload_is_read;
3824                 end
3825         endcase
3826 end
3827 always @(*) begin
3828         rhs_array_muxed10 <= 1'd0;
3829         case (sdram_choose_req_grant)
3830                 1'd0: begin
3831                         rhs_array_muxed10 <= sdram_bankmachine0_cmd_payload_is_write;
3832                 end
3833                 1'd1: begin
3834                         rhs_array_muxed10 <= sdram_bankmachine1_cmd_payload_is_write;
3835                 end
3836                 2'd2: begin
3837                         rhs_array_muxed10 <= sdram_bankmachine2_cmd_payload_is_write;
3838                 end
3839                 default: begin
3840                         rhs_array_muxed10 <= sdram_bankmachine3_cmd_payload_is_write;
3841                 end
3842         endcase
3843 end
3844 always @(*) begin
3845         rhs_array_muxed11 <= 1'd0;
3846         case (sdram_choose_req_grant)
3847                 1'd0: begin
3848                         rhs_array_muxed11 <= sdram_bankmachine0_cmd_payload_is_cmd;
3849                 end
3850                 1'd1: begin
3851                         rhs_array_muxed11 <= sdram_bankmachine1_cmd_payload_is_cmd;
3852                 end
3853                 2'd2: begin
3854                         rhs_array_muxed11 <= sdram_bankmachine2_cmd_payload_is_cmd;
3855                 end
3856                 default: begin
3857                         rhs_array_muxed11 <= sdram_bankmachine3_cmd_payload_is_cmd;
3858                 end
3859         endcase
3860 end
3861 always @(*) begin
3862         t_array_muxed3 <= 1'd0;
3863         case (sdram_choose_req_grant)
3864                 1'd0: begin
3865                         t_array_muxed3 <= sdram_bankmachine0_cmd_payload_cas;
3866                 end
3867                 1'd1: begin
3868                         t_array_muxed3 <= sdram_bankmachine1_cmd_payload_cas;
3869                 end
3870                 2'd2: begin
3871                         t_array_muxed3 <= sdram_bankmachine2_cmd_payload_cas;
3872                 end
3873                 default: begin
3874                         t_array_muxed3 <= sdram_bankmachine3_cmd_payload_cas;
3875                 end
3876         endcase
3877 end
3878 always @(*) begin
3879         t_array_muxed4 <= 1'd0;
3880         case (sdram_choose_req_grant)
3881                 1'd0: begin
3882                         t_array_muxed4 <= sdram_bankmachine0_cmd_payload_ras;
3883                 end
3884                 1'd1: begin
3885                         t_array_muxed4 <= sdram_bankmachine1_cmd_payload_ras;
3886                 end
3887                 2'd2: begin
3888                         t_array_muxed4 <= sdram_bankmachine2_cmd_payload_ras;
3889                 end
3890                 default: begin
3891                         t_array_muxed4 <= sdram_bankmachine3_cmd_payload_ras;
3892                 end
3893         endcase
3894 end
3895 always @(*) begin
3896         t_array_muxed5 <= 1'd0;
3897         case (sdram_choose_req_grant)
3898                 1'd0: begin
3899                         t_array_muxed5 <= sdram_bankmachine0_cmd_payload_we;
3900                 end
3901                 1'd1: begin
3902                         t_array_muxed5 <= sdram_bankmachine1_cmd_payload_we;
3903                 end
3904                 2'd2: begin
3905                         t_array_muxed5 <= sdram_bankmachine2_cmd_payload_we;
3906                 end
3907                 default: begin
3908                         t_array_muxed5 <= sdram_bankmachine3_cmd_payload_we;
3909                 end
3910         endcase
3911 end
3912 always @(*) begin
3913         rhs_array_muxed12 <= 22'd0;
3914         case (subfragments_roundrobin0_grant)
3915                 default: begin
3916                         rhs_array_muxed12 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3917                 end
3918         endcase
3919 end
3920 always @(*) begin
3921         rhs_array_muxed13 <= 1'd0;
3922         case (subfragments_roundrobin0_grant)
3923                 default: begin
3924                         rhs_array_muxed13 <= port_cmd_payload_we;
3925                 end
3926         endcase
3927 end
3928 always @(*) begin
3929         rhs_array_muxed14 <= 1'd0;
3930         case (subfragments_roundrobin0_grant)
3931                 default: begin
3932                         rhs_array_muxed14 <= (((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid);
3933                 end
3934         endcase
3935 end
3936 always @(*) begin
3937         rhs_array_muxed15 <= 22'd0;
3938         case (subfragments_roundrobin1_grant)
3939                 default: begin
3940                         rhs_array_muxed15 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3941                 end
3942         endcase
3943 end
3944 always @(*) begin
3945         rhs_array_muxed16 <= 1'd0;
3946         case (subfragments_roundrobin1_grant)
3947                 default: begin
3948                         rhs_array_muxed16 <= port_cmd_payload_we;
3949                 end
3950         endcase
3951 end
3952 always @(*) begin
3953         rhs_array_muxed17 <= 1'd0;
3954         case (subfragments_roundrobin1_grant)
3955                 default: begin
3956                         rhs_array_muxed17 <= (((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid);
3957                 end
3958         endcase
3959 end
3960 always @(*) begin
3961         rhs_array_muxed18 <= 22'd0;
3962         case (subfragments_roundrobin2_grant)
3963                 default: begin
3964                         rhs_array_muxed18 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3965                 end
3966         endcase
3967 end
3968 always @(*) begin
3969         rhs_array_muxed19 <= 1'd0;
3970         case (subfragments_roundrobin2_grant)
3971                 default: begin
3972                         rhs_array_muxed19 <= port_cmd_payload_we;
3973                 end
3974         endcase
3975 end
3976 always @(*) begin
3977         rhs_array_muxed20 <= 1'd0;
3978         case (subfragments_roundrobin2_grant)
3979                 default: begin
3980                         rhs_array_muxed20 <= (((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid);
3981                 end
3982         endcase
3983 end
3984 always @(*) begin
3985         rhs_array_muxed21 <= 22'd0;
3986         case (subfragments_roundrobin3_grant)
3987                 default: begin
3988                         rhs_array_muxed21 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3989                 end
3990         endcase
3991 end
3992 always @(*) begin
3993         rhs_array_muxed22 <= 1'd0;
3994         case (subfragments_roundrobin3_grant)
3995                 default: begin
3996                         rhs_array_muxed22 <= port_cmd_payload_we;
3997                 end
3998         endcase
3999 end
4000 always @(*) begin
4001         rhs_array_muxed23 <= 1'd0;
4002         case (subfragments_roundrobin3_grant)
4003                 default: begin
4004                         rhs_array_muxed23 <= (((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid);
4005                 end
4006         endcase
4007 end
4008 always @(*) begin
4009         rhs_array_muxed24 <= 30'd0;
4010         case (libresocsim_grant)
4011                 1'd0: begin
4012                         rhs_array_muxed24 <= libresocsim_interface0_converted_interface_adr;
4013                 end
4014                 1'd1: begin
4015                         rhs_array_muxed24 <= libresocsim_interface1_converted_interface_adr;
4016                 end
4017                 default: begin
4018                         rhs_array_muxed24 <= libresocsim_libresoc_jtag_wb_adr;
4019                 end
4020         endcase
4021 end
4022 always @(*) begin
4023         rhs_array_muxed25 <= 32'd0;
4024         case (libresocsim_grant)
4025                 1'd0: begin
4026                         rhs_array_muxed25 <= libresocsim_interface0_converted_interface_dat_w;
4027                 end
4028                 1'd1: begin
4029                         rhs_array_muxed25 <= libresocsim_interface1_converted_interface_dat_w;
4030                 end
4031                 default: begin
4032                         rhs_array_muxed25 <= libresocsim_libresoc_jtag_wb_dat_w;
4033                 end
4034         endcase
4035 end
4036 always @(*) begin
4037         rhs_array_muxed26 <= 4'd0;
4038         case (libresocsim_grant)
4039                 1'd0: begin
4040                         rhs_array_muxed26 <= libresocsim_interface0_converted_interface_sel;
4041                 end
4042                 1'd1: begin
4043                         rhs_array_muxed26 <= libresocsim_interface1_converted_interface_sel;
4044                 end
4045                 default: begin
4046                         rhs_array_muxed26 <= libresocsim_libresoc_jtag_wb_sel;
4047                 end
4048         endcase
4049 end
4050 always @(*) begin
4051         rhs_array_muxed27 <= 1'd0;
4052         case (libresocsim_grant)
4053                 1'd0: begin
4054                         rhs_array_muxed27 <= libresocsim_interface0_converted_interface_cyc;
4055                 end
4056                 1'd1: begin
4057                         rhs_array_muxed27 <= libresocsim_interface1_converted_interface_cyc;
4058                 end
4059                 default: begin
4060                         rhs_array_muxed27 <= libresocsim_libresoc_jtag_wb_cyc;
4061                 end
4062         endcase
4063 end
4064 always @(*) begin
4065         rhs_array_muxed28 <= 1'd0;
4066         case (libresocsim_grant)
4067                 1'd0: begin
4068                         rhs_array_muxed28 <= libresocsim_interface0_converted_interface_stb;
4069                 end
4070                 1'd1: begin
4071                         rhs_array_muxed28 <= libresocsim_interface1_converted_interface_stb;
4072                 end
4073                 default: begin
4074                         rhs_array_muxed28 <= libresocsim_libresoc_jtag_wb_stb;
4075                 end
4076         endcase
4077 end
4078 always @(*) begin
4079         rhs_array_muxed29 <= 1'd0;
4080         case (libresocsim_grant)
4081                 1'd0: begin
4082                         rhs_array_muxed29 <= libresocsim_interface0_converted_interface_we;
4083                 end
4084                 1'd1: begin
4085                         rhs_array_muxed29 <= libresocsim_interface1_converted_interface_we;
4086                 end
4087                 default: begin
4088                         rhs_array_muxed29 <= libresocsim_libresoc_jtag_wb_we;
4089                 end
4090         endcase
4091 end
4092 always @(*) begin
4093         rhs_array_muxed30 <= 3'd0;
4094         case (libresocsim_grant)
4095                 1'd0: begin
4096                         rhs_array_muxed30 <= libresocsim_interface0_converted_interface_cti;
4097                 end
4098                 1'd1: begin
4099                         rhs_array_muxed30 <= libresocsim_interface1_converted_interface_cti;
4100                 end
4101                 default: begin
4102                         rhs_array_muxed30 <= libresocsim_libresoc_jtag_wb_cti;
4103                 end
4104         endcase
4105 end
4106 always @(*) begin
4107         rhs_array_muxed31 <= 2'd0;
4108         case (libresocsim_grant)
4109                 1'd0: begin
4110                         rhs_array_muxed31 <= libresocsim_interface0_converted_interface_bte;
4111                 end
4112                 1'd1: begin
4113                         rhs_array_muxed31 <= libresocsim_interface1_converted_interface_bte;
4114                 end
4115                 default: begin
4116                         rhs_array_muxed31 <= libresocsim_libresoc_jtag_wb_bte;
4117                 end
4118         endcase
4119 end
4120 always @(*) begin
4121         array_muxed0 <= 2'd0;
4122         case (sdram_steerer_sel)
4123                 1'd0: begin
4124                         array_muxed0 <= sdram_nop_ba[1:0];
4125                 end
4126                 1'd1: begin
4127                         array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0];
4128                 end
4129                 2'd2: begin
4130                         array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0];
4131                 end
4132                 default: begin
4133                         array_muxed0 <= sdram_cmd_payload_ba[1:0];
4134                 end
4135         endcase
4136 end
4137 always @(*) begin
4138         array_muxed1 <= 13'd0;
4139         case (sdram_steerer_sel)
4140                 1'd0: begin
4141                         array_muxed1 <= sdram_nop_a;
4142                 end
4143                 1'd1: begin
4144                         array_muxed1 <= sdram_choose_req_cmd_payload_a;
4145                 end
4146                 2'd2: begin
4147                         array_muxed1 <= sdram_choose_req_cmd_payload_a;
4148                 end
4149                 default: begin
4150                         array_muxed1 <= sdram_cmd_payload_a;
4151                 end
4152         endcase
4153 end
4154 always @(*) begin
4155         array_muxed2 <= 1'd0;
4156         case (sdram_steerer_sel)
4157                 1'd0: begin
4158                         array_muxed2 <= 1'd0;
4159                 end
4160                 1'd1: begin
4161                         array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas);
4162                 end
4163                 2'd2: begin
4164                         array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas);
4165                 end
4166                 default: begin
4167                         array_muxed2 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas);
4168                 end
4169         endcase
4170 end
4171 always @(*) begin
4172         array_muxed3 <= 1'd0;
4173         case (sdram_steerer_sel)
4174                 1'd0: begin
4175                         array_muxed3 <= 1'd0;
4176                 end
4177                 1'd1: begin
4178                         array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras);
4179                 end
4180                 2'd2: begin
4181                         array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras);
4182                 end
4183                 default: begin
4184                         array_muxed3 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras);
4185                 end
4186         endcase
4187 end
4188 always @(*) begin
4189         array_muxed4 <= 1'd0;
4190         case (sdram_steerer_sel)
4191                 1'd0: begin
4192                         array_muxed4 <= 1'd0;
4193                 end
4194                 1'd1: begin
4195                         array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we);
4196                 end
4197                 2'd2: begin
4198                         array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we);
4199                 end
4200                 default: begin
4201                         array_muxed4 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we);
4202                 end
4203         endcase
4204 end
4205 always @(*) begin
4206         array_muxed5 <= 1'd0;
4207         case (sdram_steerer_sel)
4208                 1'd0: begin
4209                         array_muxed5 <= 1'd0;
4210                 end
4211                 1'd1: begin
4212                         array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read);
4213                 end
4214                 2'd2: begin
4215                         array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read);
4216                 end
4217                 default: begin
4218                         array_muxed5 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read);
4219                 end
4220         endcase
4221 end
4222 always @(*) begin
4223         array_muxed6 <= 1'd0;
4224         case (sdram_steerer_sel)
4225                 1'd0: begin
4226                         array_muxed6 <= 1'd0;
4227                 end
4228                 1'd1: begin
4229                         array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write);
4230                 end
4231                 2'd2: begin
4232                         array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write);
4233                 end
4234                 default: begin
4235                         array_muxed6 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write);
4236                 end
4237         endcase
4238 end
4239 assign sdrio_clk = sys_clk_1;
4240 assign sdrio_clk_1 = sys_clk_1;
4241 assign sdrio_clk_2 = sys_clk_1;
4242 assign sdrio_clk_3 = sys_clk_1;
4243 assign sdrio_clk_4 = sys_clk_1;
4244 assign sdrio_clk_5 = sys_clk_1;
4245 assign sdrio_clk_6 = sys_clk_1;
4246 assign sdrio_clk_7 = sys_clk_1;
4247 assign sdrio_clk_8 = sys_clk_1;
4248 assign sdrio_clk_9 = sys_clk_1;
4249 assign sdrio_clk_10 = sys_clk_1;
4250 assign sdrio_clk_11 = sys_clk_1;
4251 assign sdrio_clk_12 = sys_clk_1;
4252 assign sdrio_clk_13 = sys_clk_1;
4253 assign sdrio_clk_14 = sys_clk_1;
4254 assign sdrio_clk_15 = sys_clk_1;
4255 assign sdrio_clk_16 = sys_clk_1;
4256 assign sdrio_clk_17 = sys_clk_1;
4257 assign sdrio_clk_18 = sys_clk_1;
4258 assign sdrio_clk_19 = sys_clk_1;
4259 assign sdrio_clk_20 = sys_clk_1;
4260 assign sdrio_clk_21 = sys_clk_1;
4261 assign sdrio_clk_22 = sys_clk_1;
4262 assign sdrio_clk_23 = sys_clk_1;
4263 assign sdrio_clk_24 = sys_clk_1;
4264 assign sdrio_clk_25 = sys_clk_1;
4265 assign sdrio_clk_26 = sys_clk_1;
4266 assign sdrio_clk_27 = sys_clk_1;
4267 assign sdrio_clk_28 = sys_clk_1;
4268 assign sdrio_clk_29 = sys_clk_1;
4269 assign sdrio_clk_30 = sys_clk_1;
4270 assign sdrio_clk_31 = sys_clk_1;
4271 assign sdrio_clk_32 = sys_clk_1;
4272 assign sdrio_clk_33 = sys_clk_1;
4273 assign sdrio_clk_34 = sys_clk_1;
4274 assign sdrio_clk_35 = sys_clk_1;
4275 assign sdrio_clk_36 = sys_clk_1;
4276 assign sdrio_clk_37 = sys_clk_1;
4277 assign sdrio_clk_38 = sys_clk_1;
4278 assign sdrio_clk_39 = sys_clk_1;
4279 assign sdrio_clk_40 = sys_clk_1;
4280 assign sdrio_clk_41 = sys_clk_1;
4281 assign sdrio_clk_42 = sys_clk_1;
4282 assign sdrio_clk_43 = sys_clk_1;
4283 assign sdrio_clk_44 = sys_clk_1;
4284 assign sdrio_clk_45 = sys_clk_1;
4285 assign sdrio_clk_46 = sys_clk_1;
4286 assign sdrio_clk_47 = sys_clk_1;
4287 assign sdrio_clk_48 = sys_clk_1;
4288 assign sdrio_clk_49 = sys_clk_1;
4289 assign sdrio_clk_50 = sys_clk_1;
4290 assign sdrio_clk_51 = sys_clk_1;
4291 assign sdrio_clk_52 = sys_clk_1;
4292 assign sdrio_clk_53 = sys_clk_1;
4293 assign sdrio_clk_54 = sys_clk_1;
4294 assign sdrio_clk_55 = sys_clk_1;
4295 assign sdrio_clk_56 = sys_clk_1;
4296 assign sdrio_clk_57 = sys_clk_1;
4297 assign sdrio_clk_58 = sys_clk_1;
4298 assign sdrio_clk_59 = sys_clk_1;
4299 assign sdrio_clk_60 = sys_clk_1;
4300 assign sdrio_clk_61 = sys_clk_1;
4301 assign sdrio_clk_62 = sys_clk_1;
4302 assign sdrio_clk_63 = sys_clk_1;
4303 assign sdrio_clk_64 = sys_clk_1;
4304 assign sdrio_clk_65 = sys_clk_1;
4305 assign sdrio_clk_66 = sys_clk_1;
4306 assign sdrio_clk_67 = sys_clk_1;
4307 assign sdrio_clk_68 = sys_clk_1;
4308 assign sdrio_clk_69 = sys_clk_1;
4309 assign sdrio_clk_70 = sys_clk_1;
4310 assign uart_phy_rx = regs1;
4311 assign sdrio_clk_71 = sys_clk_1;
4312 assign sdrio_clk_72 = sys_clk_1;
4313 assign sdrio_clk_73 = sys_clk_1;
4314 assign sdrio_clk_74 = sys_clk_1;
4315 assign sdrio_clk_75 = sys_clk_1;
4316 assign sdrio_clk_76 = sys_clk_1;
4317 assign sdrio_clk_77 = sys_clk_1;
4318 assign sdrio_clk_78 = sys_clk_1;
4319 assign sdrio_clk_79 = sys_clk_1;
4320 assign sdrio_clk_80 = sys_clk_1;
4321 assign sdrio_clk_81 = sys_clk_1;
4322 assign sdrio_clk_82 = sys_clk_1;
4323 assign sdrio_clk_83 = sys_clk_1;
4324 assign sdrio_clk_84 = sys_clk_1;
4325 assign sdrio_clk_85 = sys_clk_1;
4326 assign sdrio_clk_86 = sys_clk_1;
4327 assign sdrio_clk_87 = sys_clk_1;
4328 assign sdrio_clk_88 = sys_clk_1;
4329 assign sdrio_clk_89 = sys_clk_1;
4330 assign sdrio_clk_90 = sys_clk_1;
4331 assign sdrio_clk_91 = sys_clk_1;
4332 assign sdrio_clk_92 = sys_clk_1;
4333 assign sdrio_clk_93 = sys_clk_1;
4334 assign sdrio_clk_94 = sys_clk_1;
4335 assign sdrio_clk_95 = sys_clk_1;
4336 assign sdrio_clk_96 = sys_clk_1;
4337 assign sdrio_clk_97 = sys_clk_1;
4338 assign sdrio_clk_98 = sys_clk_1;
4339 assign sdrio_clk_99 = sys_clk_1;
4340 assign sdrio_clk_100 = sys_clk_1;
4341 assign sdrio_clk_101 = sys_clk_1;
4342 assign sdrio_clk_102 = sys_clk_1;
4343 assign sdrio_clk_103 = sys_clk_1;
4344 assign sdrio_clk_104 = sys_clk_1;
4345 assign sdrio_clk_105 = sys_clk_1;
4346 assign sdrio_clk_106 = sys_clk_1;
4347 assign sdrio_clk_107 = sys_clk_1;
4348 assign sdrio_clk_108 = sys_clk_1;
4349 assign sdrio_clk_109 = sys_clk_1;
4350 assign sdrio_clk_110 = sys_clk_1;
4351 assign sdrio_clk_111 = sys_clk_1;
4352 assign sdrio_clk_112 = sys_clk_1;
4353 assign sdrio_clk_113 = sys_clk_1;
4354 assign sdrio_clk_114 = sys_clk_1;
4355 assign sdrio_clk_115 = sys_clk_1;
4356 assign sdrio_clk_116 = sys_clk_1;
4357 assign sdrio_clk_117 = sys_clk_1;
4358 assign sdrio_clk_118 = sys_clk_1;
4359
4360 always @(posedge por_clk) begin
4361         int_rst <= sys_rst;
4362 end
4363
4364 always @(posedge sdrio_clk) begin
4365         libresocsim_libresoc_constraintmanager_sdram_a[0] <= dfi_p0_address[0];
4366         libresocsim_libresoc_constraintmanager_sdram_a[1] <= dfi_p0_address[1];
4367         libresocsim_libresoc_constraintmanager_sdram_a[2] <= dfi_p0_address[2];
4368         libresocsim_libresoc_constraintmanager_sdram_a[3] <= dfi_p0_address[3];
4369         libresocsim_libresoc_constraintmanager_sdram_a[4] <= dfi_p0_address[4];
4370         libresocsim_libresoc_constraintmanager_sdram_a[5] <= dfi_p0_address[5];
4371         libresocsim_libresoc_constraintmanager_sdram_a[6] <= dfi_p0_address[6];
4372         libresocsim_libresoc_constraintmanager_sdram_a[7] <= dfi_p0_address[7];
4373         libresocsim_libresoc_constraintmanager_sdram_a[8] <= dfi_p0_address[8];
4374         libresocsim_libresoc_constraintmanager_sdram_a[9] <= dfi_p0_address[9];
4375         libresocsim_libresoc_constraintmanager_sdram_a[10] <= dfi_p0_address[10];
4376         libresocsim_libresoc_constraintmanager_sdram_a[11] <= dfi_p0_address[11];
4377         libresocsim_libresoc_constraintmanager_sdram_a[12] <= dfi_p0_address[12];
4378         libresocsim_libresoc_constraintmanager_sdram_ba[0] <= dfi_p0_bank[0];
4379         libresocsim_libresoc_constraintmanager_sdram_ba[1] <= dfi_p0_bank[1];
4380         libresocsim_libresoc_constraintmanager_sdram_cas_n <= dfi_p0_cas_n;
4381         libresocsim_libresoc_constraintmanager_sdram_ras_n <= dfi_p0_ras_n;
4382         libresocsim_libresoc_constraintmanager_sdram_we_n <= dfi_p0_we_n;
4383         libresocsim_libresoc_constraintmanager_sdram_cke <= dfi_p0_cke;
4384         libresocsim_libresoc_constraintmanager_sdram_cs_n <= dfi_p0_cs_n;
4385         libresocsim_libresoc_constraintmanager_sdram_dq_oe[0] <= dfi_p0_wrdata_en;
4386         libresocsim_libresoc_constraintmanager_sdram_dq_o[0] <= dfi_p0_wrdata[0];
4387         dfi_p0_rddata[0] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[0];
4388         libresocsim_libresoc_constraintmanager_sdram_dq_oe[1] <= dfi_p0_wrdata_en;
4389         libresocsim_libresoc_constraintmanager_sdram_dq_o[1] <= dfi_p0_wrdata[1];
4390         dfi_p0_rddata[1] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[1];
4391         libresocsim_libresoc_constraintmanager_sdram_dq_oe[2] <= dfi_p0_wrdata_en;
4392         libresocsim_libresoc_constraintmanager_sdram_dq_o[2] <= dfi_p0_wrdata[2];
4393         dfi_p0_rddata[2] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[2];
4394         libresocsim_libresoc_constraintmanager_sdram_dq_oe[3] <= dfi_p0_wrdata_en;
4395         libresocsim_libresoc_constraintmanager_sdram_dq_o[3] <= dfi_p0_wrdata[3];
4396         dfi_p0_rddata[3] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[3];
4397         libresocsim_libresoc_constraintmanager_sdram_dq_oe[4] <= dfi_p0_wrdata_en;
4398         libresocsim_libresoc_constraintmanager_sdram_dq_o[4] <= dfi_p0_wrdata[4];
4399         dfi_p0_rddata[4] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[4];
4400         libresocsim_libresoc_constraintmanager_sdram_dq_oe[5] <= dfi_p0_wrdata_en;
4401         libresocsim_libresoc_constraintmanager_sdram_dq_o[5] <= dfi_p0_wrdata[5];
4402         dfi_p0_rddata[5] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[5];
4403         libresocsim_libresoc_constraintmanager_sdram_dq_oe[6] <= dfi_p0_wrdata_en;
4404         libresocsim_libresoc_constraintmanager_sdram_dq_o[6] <= dfi_p0_wrdata[6];
4405         dfi_p0_rddata[6] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[6];
4406         libresocsim_libresoc_constraintmanager_sdram_dq_oe[7] <= dfi_p0_wrdata_en;
4407         libresocsim_libresoc_constraintmanager_sdram_dq_o[7] <= dfi_p0_wrdata[7];
4408         dfi_p0_rddata[7] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[7];
4409         libresocsim_libresoc_constraintmanager_sdram_dq_oe[8] <= dfi_p0_wrdata_en;
4410         libresocsim_libresoc_constraintmanager_sdram_dq_o[8] <= dfi_p0_wrdata[8];
4411         dfi_p0_rddata[8] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[8];
4412         libresocsim_libresoc_constraintmanager_sdram_dq_oe[9] <= dfi_p0_wrdata_en;
4413         libresocsim_libresoc_constraintmanager_sdram_dq_o[9] <= dfi_p0_wrdata[9];
4414         dfi_p0_rddata[9] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[9];
4415         libresocsim_libresoc_constraintmanager_sdram_dq_oe[10] <= dfi_p0_wrdata_en;
4416         libresocsim_libresoc_constraintmanager_sdram_dq_o[10] <= dfi_p0_wrdata[10];
4417         dfi_p0_rddata[10] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[10];
4418         libresocsim_libresoc_constraintmanager_sdram_dq_oe[11] <= dfi_p0_wrdata_en;
4419         libresocsim_libresoc_constraintmanager_sdram_dq_o[11] <= dfi_p0_wrdata[11];
4420         dfi_p0_rddata[11] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[11];
4421         libresocsim_libresoc_constraintmanager_sdram_dq_oe[12] <= dfi_p0_wrdata_en;
4422         libresocsim_libresoc_constraintmanager_sdram_dq_o[12] <= dfi_p0_wrdata[12];
4423         dfi_p0_rddata[12] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[12];
4424         libresocsim_libresoc_constraintmanager_sdram_dq_oe[13] <= dfi_p0_wrdata_en;
4425         libresocsim_libresoc_constraintmanager_sdram_dq_o[13] <= dfi_p0_wrdata[13];
4426         dfi_p0_rddata[13] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[13];
4427         libresocsim_libresoc_constraintmanager_sdram_dq_oe[14] <= dfi_p0_wrdata_en;
4428         libresocsim_libresoc_constraintmanager_sdram_dq_o[14] <= dfi_p0_wrdata[14];
4429         dfi_p0_rddata[14] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[14];
4430         libresocsim_libresoc_constraintmanager_sdram_dq_oe[15] <= dfi_p0_wrdata_en;
4431         libresocsim_libresoc_constraintmanager_sdram_dq_o[15] <= dfi_p0_wrdata[15];
4432         dfi_p0_rddata[15] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[15];
4433         libresocsim_libresoc_constraintmanager_sdram_dm[0] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[0]);
4434         libresocsim_libresoc_constraintmanager_sdram_dm[1] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[1]);
4435         libresocsim_libresoc_constraintmanager_sdram_clock <= sys_clk_1;
4436         gpio0_pads_gpio0oe[0] <= gpio0_oe_storage[0];
4437         gpio0_pads_gpio0o[0] <= gpio0_out_storage[0];
4438         gpio0_status[0] <= gpio0_pads_gpio0i[0];
4439         gpio0_pads_gpio0oe[1] <= gpio0_oe_storage[1];
4440         gpio0_pads_gpio0o[1] <= gpio0_out_storage[1];
4441         gpio0_status[1] <= gpio0_pads_gpio0i[1];
4442         gpio0_pads_gpio0oe[2] <= gpio0_oe_storage[2];
4443         gpio0_pads_gpio0o[2] <= gpio0_out_storage[2];
4444         gpio0_status[2] <= gpio0_pads_gpio0i[2];
4445         gpio0_pads_gpio0oe[3] <= gpio0_oe_storage[3];
4446         gpio0_pads_gpio0o[3] <= gpio0_out_storage[3];
4447         gpio0_status[3] <= gpio0_pads_gpio0i[3];
4448         gpio0_pads_gpio0oe[4] <= gpio0_oe_storage[4];
4449         gpio0_pads_gpio0o[4] <= gpio0_out_storage[4];
4450         gpio0_status[4] <= gpio0_pads_gpio0i[4];
4451         gpio0_pads_gpio0oe[5] <= gpio0_oe_storage[5];
4452         gpio0_pads_gpio0o[5] <= gpio0_out_storage[5];
4453         gpio0_status[5] <= gpio0_pads_gpio0i[5];
4454         gpio0_pads_gpio0oe[6] <= gpio0_oe_storage[6];
4455         gpio0_pads_gpio0o[6] <= gpio0_out_storage[6];
4456         gpio0_status[6] <= gpio0_pads_gpio0i[6];
4457         gpio0_pads_gpio0oe[7] <= gpio0_oe_storage[7];
4458         gpio0_pads_gpio0o[7] <= gpio0_out_storage[7];
4459         gpio0_status[7] <= gpio0_pads_gpio0i[7];
4460         gpio1_pads_gpio1oe[0] <= gpio1_oe_storage[0];
4461         gpio1_pads_gpio1o[0] <= gpio1_out_storage[0];
4462         gpio1_status[0] <= gpio1_pads_gpio1i[0];
4463         gpio1_pads_gpio1oe[1] <= gpio1_oe_storage[1];
4464         gpio1_pads_gpio1o[1] <= gpio1_out_storage[1];
4465         gpio1_status[1] <= gpio1_pads_gpio1i[1];
4466         gpio1_pads_gpio1oe[2] <= gpio1_oe_storage[2];
4467         gpio1_pads_gpio1o[2] <= gpio1_out_storage[2];
4468         gpio1_status[2] <= gpio1_pads_gpio1i[2];
4469         gpio1_pads_gpio1oe[3] <= gpio1_oe_storage[3];
4470         gpio1_pads_gpio1o[3] <= gpio1_out_storage[3];
4471         gpio1_status[3] <= gpio1_pads_gpio1i[3];
4472         gpio1_pads_gpio1oe[4] <= gpio1_oe_storage[4];
4473         gpio1_pads_gpio1o[4] <= gpio1_out_storage[4];
4474         gpio1_status[4] <= gpio1_pads_gpio1i[4];
4475         gpio1_pads_gpio1oe[5] <= gpio1_oe_storage[5];
4476         gpio1_pads_gpio1o[5] <= gpio1_out_storage[5];
4477         gpio1_status[5] <= gpio1_pads_gpio1i[5];
4478         gpio1_pads_gpio1oe[6] <= gpio1_oe_storage[6];
4479         gpio1_pads_gpio1o[6] <= gpio1_out_storage[6];
4480         gpio1_status[6] <= gpio1_pads_gpio1i[6];
4481         gpio1_pads_gpio1oe[7] <= gpio1_oe_storage[7];
4482         gpio1_pads_gpio1o[7] <= gpio1_out_storage[7];
4483         gpio1_status[7] <= gpio1_pads_gpio1i[7];
4484 end
4485
4486 always @(posedge sys_clk_1) begin
4487         dummy[0] <= (nc_1[0] | libresocsim_libresoc_interrupt[0]);
4488         dummy[1] <= (nc_1[1] | libresocsim_libresoc_interrupt[0]);
4489         dummy[2] <= (nc_1[2] | libresocsim_libresoc_interrupt[0]);
4490         dummy[3] <= (nc_1[3] | libresocsim_libresoc_interrupt[0]);
4491         dummy[4] <= (nc_1[4] | libresocsim_libresoc_interrupt[0]);
4492         dummy[5] <= (nc_1[5] | libresocsim_libresoc_interrupt[0]);
4493         dummy[6] <= (nc_1[6] | libresocsim_libresoc_interrupt[0]);
4494         dummy[7] <= (nc_1[7] | libresocsim_libresoc_interrupt[0]);
4495         dummy[8] <= (nc_1[8] | libresocsim_libresoc_interrupt[0]);
4496         dummy[9] <= (nc_1[9] | libresocsim_libresoc_interrupt[0]);
4497         dummy[10] <= (nc_1[10] | libresocsim_libresoc_interrupt[0]);
4498         dummy[11] <= (nc_1[11] | libresocsim_libresoc_interrupt[0]);
4499         dummy[12] <= (nc_1[12] | libresocsim_libresoc_interrupt[0]);
4500         dummy[13] <= (nc_1[13] | libresocsim_libresoc_interrupt[0]);
4501         dummy[14] <= (nc_1[14] | libresocsim_libresoc_interrupt[0]);
4502         dummy[15] <= (nc_1[15] | libresocsim_libresoc_interrupt[0]);
4503         dummy[16] <= (nc_1[16] | libresocsim_libresoc_interrupt[0]);
4504         dummy[17] <= (nc_1[17] | libresocsim_libresoc_interrupt[0]);
4505         dummy[18] <= (nc_1[18] | libresocsim_libresoc_interrupt[0]);
4506         dummy[19] <= (nc_1[19] | libresocsim_libresoc_interrupt[0]);
4507         dummy[20] <= (nc_1[20] | libresocsim_libresoc_interrupt[0]);
4508         dummy[21] <= (nc_1[21] | libresocsim_libresoc_interrupt[0]);
4509         dummy[22] <= (nc_1[22] | libresocsim_libresoc_interrupt[0]);
4510         dummy[23] <= (nc_1[23] | libresocsim_libresoc_interrupt[0]);
4511         dummy[24] <= (nc_1[24] | libresocsim_libresoc_interrupt[0]);
4512         dummy[25] <= (nc_1[25] | libresocsim_libresoc_interrupt[0]);
4513         dummy[26] <= (nc_1[26] | libresocsim_libresoc_interrupt[0]);
4514         dummy[27] <= (nc_1[27] | libresocsim_libresoc_interrupt[0]);
4515         dummy[28] <= (nc_1[28] | libresocsim_libresoc_interrupt[0]);
4516         dummy[29] <= (nc_1[29] | libresocsim_libresoc_interrupt[0]);
4517         dummy[30] <= (nc_1[30] | libresocsim_libresoc_interrupt[0]);
4518         dummy[31] <= (nc_1[31] | libresocsim_libresoc_interrupt[0]);
4519         dummy[32] <= (nc_1[32] | libresocsim_libresoc_interrupt[0]);
4520         dummy[33] <= (nc_1[33] | libresocsim_libresoc_interrupt[0]);
4521         dummy[34] <= (nc_1[34] | libresocsim_libresoc_interrupt[0]);
4522         if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin
4523                 libresocsim_converter0_dat_r <= libresocsim_libresoc_ibus_dat_r;
4524         end
4525         subfragments_converter0_state <= subfragments_converter0_next_state;
4526         if (libresocsim_converter0_counter_subfragments_converter0_next_value_ce) begin
4527                 libresocsim_converter0_counter <= libresocsim_converter0_counter_subfragments_converter0_next_value;
4528         end
4529         if (libresocsim_converter0_reset) begin
4530                 libresocsim_converter0_counter <= 1'd0;
4531                 subfragments_converter0_state <= 1'd0;
4532         end
4533         if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin
4534                 libresocsim_converter1_dat_r <= libresocsim_libresoc_dbus_dat_r;
4535         end
4536         subfragments_converter1_state <= subfragments_converter1_next_state;
4537         if (libresocsim_converter1_counter_subfragments_converter1_next_value_ce) begin
4538                 libresocsim_converter1_counter <= libresocsim_converter1_counter_subfragments_converter1_next_value;
4539         end
4540         if (libresocsim_converter1_reset) begin
4541                 libresocsim_converter1_counter <= 1'd0;
4542                 subfragments_converter1_state <= 1'd0;
4543         end
4544         if ((libresocsim_bus_errors != 32'd4294967295)) begin
4545                 if (libresocsim_bus_error) begin
4546                         libresocsim_bus_errors <= (libresocsim_bus_errors + 1'd1);
4547                 end
4548         end
4549         libresocsim_ram_bus_ack <= 1'd0;
4550         if (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & (~libresocsim_ram_bus_ack))) begin
4551                 libresocsim_ram_bus_ack <= 1'd1;
4552         end
4553         if (libresocsim_en_storage) begin
4554                 if ((libresocsim_value == 1'd0)) begin
4555                         libresocsim_value <= libresocsim_reload_storage;
4556                 end else begin
4557                         libresocsim_value <= (libresocsim_value - 1'd1);
4558                 end
4559         end else begin
4560                 libresocsim_value <= libresocsim_load_storage;
4561         end
4562         if (libresocsim_update_value_re) begin
4563                 libresocsim_value_status <= libresocsim_value;
4564         end
4565         if (libresocsim_zero_clear) begin
4566                 libresocsim_zero_pending <= 1'd0;
4567         end
4568         libresocsim_zero_old_trigger <= libresocsim_zero_trigger;
4569         if (((~libresocsim_zero_trigger) & libresocsim_zero_old_trigger)) begin
4570                 libresocsim_zero_pending <= 1'd1;
4571         end
4572         ram_bus_ram_bus_ack <= 1'd0;
4573         if (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & (~ram_bus_ram_bus_ack))) begin
4574                 ram_bus_ram_bus_ack <= 1'd1;
4575         end
4576         rddata_en <= {rddata_en, dfi_p0_rddata_en};
4577         dfi_p0_rddata_valid <= rddata_en[2];
4578         if (sdram_inti_p0_rddata_valid) begin
4579                 sdram_status <= sdram_inti_p0_rddata;
4580         end
4581         if ((sdram_timer_wait & (~sdram_timer_done0))) begin
4582                 sdram_timer_count1 <= (sdram_timer_count1 - 1'd1);
4583         end else begin
4584                 sdram_timer_count1 <= 10'd781;
4585         end
4586         sdram_postponer_req_o <= 1'd0;
4587         if (sdram_postponer_req_i) begin
4588                 sdram_postponer_count <= (sdram_postponer_count - 1'd1);
4589                 if ((sdram_postponer_count == 1'd0)) begin
4590                         sdram_postponer_count <= 1'd0;
4591                         sdram_postponer_req_o <= 1'd1;
4592                 end
4593         end
4594         if (sdram_sequencer_start0) begin
4595                 sdram_sequencer_count <= 1'd0;
4596         end else begin
4597                 if (sdram_sequencer_done1) begin
4598                         if ((sdram_sequencer_count != 1'd0)) begin
4599                                 sdram_sequencer_count <= (sdram_sequencer_count - 1'd1);
4600                         end
4601                 end
4602         end
4603         sdram_cmd_payload_a <= 1'd0;
4604         sdram_cmd_payload_ba <= 1'd0;
4605         sdram_cmd_payload_cas <= 1'd0;
4606         sdram_cmd_payload_ras <= 1'd0;
4607         sdram_cmd_payload_we <= 1'd0;
4608         sdram_sequencer_done1 <= 1'd0;
4609         if ((sdram_sequencer_start1 & (sdram_sequencer_counter == 1'd0))) begin
4610                 sdram_cmd_payload_a <= 11'd1024;
4611                 sdram_cmd_payload_ba <= 1'd0;
4612                 sdram_cmd_payload_cas <= 1'd0;
4613                 sdram_cmd_payload_ras <= 1'd1;
4614                 sdram_cmd_payload_we <= 1'd1;
4615         end
4616         if ((sdram_sequencer_counter == 2'd2)) begin
4617                 sdram_cmd_payload_a <= 1'd0;
4618                 sdram_cmd_payload_ba <= 1'd0;
4619                 sdram_cmd_payload_cas <= 1'd1;
4620                 sdram_cmd_payload_ras <= 1'd1;
4621                 sdram_cmd_payload_we <= 1'd0;
4622         end
4623         if ((sdram_sequencer_counter == 4'd8)) begin
4624                 sdram_cmd_payload_a <= 1'd0;
4625                 sdram_cmd_payload_ba <= 1'd0;
4626                 sdram_cmd_payload_cas <= 1'd0;
4627                 sdram_cmd_payload_ras <= 1'd0;
4628                 sdram_cmd_payload_we <= 1'd0;
4629                 sdram_sequencer_done1 <= 1'd1;
4630         end
4631         if ((sdram_sequencer_counter == 4'd8)) begin
4632                 sdram_sequencer_counter <= 1'd0;
4633         end else begin
4634                 if ((sdram_sequencer_counter != 1'd0)) begin
4635                         sdram_sequencer_counter <= (sdram_sequencer_counter + 1'd1);
4636                 end else begin
4637                         if (sdram_sequencer_start1) begin
4638                                 sdram_sequencer_counter <= 1'd1;
4639                         end
4640                 end
4641         end
4642         subfragments_refresher_state <= subfragments_refresher_next_state;
4643         if (sdram_bankmachine0_row_close) begin
4644                 sdram_bankmachine0_row_opened <= 1'd0;
4645         end else begin
4646                 if (sdram_bankmachine0_row_open) begin
4647                         sdram_bankmachine0_row_opened <= 1'd1;
4648                         sdram_bankmachine0_row <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
4649                 end
4650         end
4651         if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
4652                 sdram_bankmachine0_cmd_buffer_lookahead_produce <= (sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
4653         end
4654         if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
4655                 sdram_bankmachine0_cmd_buffer_lookahead_consume <= (sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
4656         end
4657         if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
4658                 if ((~sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
4659                         sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
4660                 end
4661         end else begin
4662                 if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
4663                         sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
4664                 end
4665         end
4666         if (((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready)) begin
4667                 sdram_bankmachine0_cmd_buffer_source_valid <= sdram_bankmachine0_cmd_buffer_sink_valid;
4668                 sdram_bankmachine0_cmd_buffer_source_first <= sdram_bankmachine0_cmd_buffer_sink_first;
4669                 sdram_bankmachine0_cmd_buffer_source_last <= sdram_bankmachine0_cmd_buffer_sink_last;
4670                 sdram_bankmachine0_cmd_buffer_source_payload_we <= sdram_bankmachine0_cmd_buffer_sink_payload_we;
4671                 sdram_bankmachine0_cmd_buffer_source_payload_addr <= sdram_bankmachine0_cmd_buffer_sink_payload_addr;
4672         end
4673         if (sdram_bankmachine0_twtpcon_valid) begin
4674                 sdram_bankmachine0_twtpcon_count <= 3'd4;
4675                 if (1'd0) begin
4676                         sdram_bankmachine0_twtpcon_ready <= 1'd1;
4677                 end else begin
4678                         sdram_bankmachine0_twtpcon_ready <= 1'd0;
4679                 end
4680         end else begin
4681                 if ((~sdram_bankmachine0_twtpcon_ready)) begin
4682                         sdram_bankmachine0_twtpcon_count <= (sdram_bankmachine0_twtpcon_count - 1'd1);
4683                         if ((sdram_bankmachine0_twtpcon_count == 1'd1)) begin
4684                                 sdram_bankmachine0_twtpcon_ready <= 1'd1;
4685                         end
4686                 end
4687         end
4688         subfragments_bankmachine0_state <= subfragments_bankmachine0_next_state;
4689         if (sdram_bankmachine1_row_close) begin
4690                 sdram_bankmachine1_row_opened <= 1'd0;
4691         end else begin
4692                 if (sdram_bankmachine1_row_open) begin
4693                         sdram_bankmachine1_row_opened <= 1'd1;
4694                         sdram_bankmachine1_row <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
4695                 end
4696         end
4697         if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
4698                 sdram_bankmachine1_cmd_buffer_lookahead_produce <= (sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
4699         end
4700         if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
4701                 sdram_bankmachine1_cmd_buffer_lookahead_consume <= (sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
4702         end
4703         if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
4704                 if ((~sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
4705                         sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
4706                 end
4707         end else begin
4708                 if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
4709                         sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
4710                 end
4711         end
4712         if (((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready)) begin
4713                 sdram_bankmachine1_cmd_buffer_source_valid <= sdram_bankmachine1_cmd_buffer_sink_valid;
4714                 sdram_bankmachine1_cmd_buffer_source_first <= sdram_bankmachine1_cmd_buffer_sink_first;
4715                 sdram_bankmachine1_cmd_buffer_source_last <= sdram_bankmachine1_cmd_buffer_sink_last;
4716                 sdram_bankmachine1_cmd_buffer_source_payload_we <= sdram_bankmachine1_cmd_buffer_sink_payload_we;
4717                 sdram_bankmachine1_cmd_buffer_source_payload_addr <= sdram_bankmachine1_cmd_buffer_sink_payload_addr;
4718         end
4719         if (sdram_bankmachine1_twtpcon_valid) begin
4720                 sdram_bankmachine1_twtpcon_count <= 3'd4;
4721                 if (1'd0) begin
4722                         sdram_bankmachine1_twtpcon_ready <= 1'd1;
4723                 end else begin
4724                         sdram_bankmachine1_twtpcon_ready <= 1'd0;
4725                 end
4726         end else begin
4727                 if ((~sdram_bankmachine1_twtpcon_ready)) begin
4728                         sdram_bankmachine1_twtpcon_count <= (sdram_bankmachine1_twtpcon_count - 1'd1);
4729                         if ((sdram_bankmachine1_twtpcon_count == 1'd1)) begin
4730                                 sdram_bankmachine1_twtpcon_ready <= 1'd1;
4731                         end
4732                 end
4733         end
4734         subfragments_bankmachine1_state <= subfragments_bankmachine1_next_state;
4735         if (sdram_bankmachine2_row_close) begin
4736                 sdram_bankmachine2_row_opened <= 1'd0;
4737         end else begin
4738                 if (sdram_bankmachine2_row_open) begin
4739                         sdram_bankmachine2_row_opened <= 1'd1;
4740                         sdram_bankmachine2_row <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
4741                 end
4742         end
4743         if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
4744                 sdram_bankmachine2_cmd_buffer_lookahead_produce <= (sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
4745         end
4746         if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
4747                 sdram_bankmachine2_cmd_buffer_lookahead_consume <= (sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
4748         end
4749         if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
4750                 if ((~sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
4751                         sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
4752                 end
4753         end else begin
4754                 if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
4755                         sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
4756                 end
4757         end
4758         if (((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready)) begin
4759                 sdram_bankmachine2_cmd_buffer_source_valid <= sdram_bankmachine2_cmd_buffer_sink_valid;
4760                 sdram_bankmachine2_cmd_buffer_source_first <= sdram_bankmachine2_cmd_buffer_sink_first;
4761                 sdram_bankmachine2_cmd_buffer_source_last <= sdram_bankmachine2_cmd_buffer_sink_last;
4762                 sdram_bankmachine2_cmd_buffer_source_payload_we <= sdram_bankmachine2_cmd_buffer_sink_payload_we;
4763                 sdram_bankmachine2_cmd_buffer_source_payload_addr <= sdram_bankmachine2_cmd_buffer_sink_payload_addr;
4764         end
4765         if (sdram_bankmachine2_twtpcon_valid) begin
4766                 sdram_bankmachine2_twtpcon_count <= 3'd4;
4767                 if (1'd0) begin
4768                         sdram_bankmachine2_twtpcon_ready <= 1'd1;
4769                 end else begin
4770                         sdram_bankmachine2_twtpcon_ready <= 1'd0;
4771                 end
4772         end else begin
4773                 if ((~sdram_bankmachine2_twtpcon_ready)) begin
4774                         sdram_bankmachine2_twtpcon_count <= (sdram_bankmachine2_twtpcon_count - 1'd1);
4775                         if ((sdram_bankmachine2_twtpcon_count == 1'd1)) begin
4776                                 sdram_bankmachine2_twtpcon_ready <= 1'd1;
4777                         end
4778                 end
4779         end
4780         subfragments_bankmachine2_state <= subfragments_bankmachine2_next_state;
4781         if (sdram_bankmachine3_row_close) begin
4782                 sdram_bankmachine3_row_opened <= 1'd0;
4783         end else begin
4784                 if (sdram_bankmachine3_row_open) begin
4785                         sdram_bankmachine3_row_opened <= 1'd1;
4786                         sdram_bankmachine3_row <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
4787                 end
4788         end
4789         if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
4790                 sdram_bankmachine3_cmd_buffer_lookahead_produce <= (sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
4791         end
4792         if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
4793                 sdram_bankmachine3_cmd_buffer_lookahead_consume <= (sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
4794         end
4795         if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
4796                 if ((~sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
4797                         sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
4798                 end
4799         end else begin
4800                 if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
4801                         sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
4802                 end
4803         end
4804         if (((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready)) begin
4805                 sdram_bankmachine3_cmd_buffer_source_valid <= sdram_bankmachine3_cmd_buffer_sink_valid;
4806                 sdram_bankmachine3_cmd_buffer_source_first <= sdram_bankmachine3_cmd_buffer_sink_first;
4807                 sdram_bankmachine3_cmd_buffer_source_last <= sdram_bankmachine3_cmd_buffer_sink_last;
4808                 sdram_bankmachine3_cmd_buffer_source_payload_we <= sdram_bankmachine3_cmd_buffer_sink_payload_we;
4809                 sdram_bankmachine3_cmd_buffer_source_payload_addr <= sdram_bankmachine3_cmd_buffer_sink_payload_addr;
4810         end
4811         if (sdram_bankmachine3_twtpcon_valid) begin
4812                 sdram_bankmachine3_twtpcon_count <= 3'd4;
4813                 if (1'd0) begin
4814                         sdram_bankmachine3_twtpcon_ready <= 1'd1;
4815                 end else begin
4816                         sdram_bankmachine3_twtpcon_ready <= 1'd0;
4817                 end
4818         end else begin
4819                 if ((~sdram_bankmachine3_twtpcon_ready)) begin
4820                         sdram_bankmachine3_twtpcon_count <= (sdram_bankmachine3_twtpcon_count - 1'd1);
4821                         if ((sdram_bankmachine3_twtpcon_count == 1'd1)) begin
4822                                 sdram_bankmachine3_twtpcon_ready <= 1'd1;
4823                         end
4824                 end
4825         end
4826         subfragments_bankmachine3_state <= subfragments_bankmachine3_next_state;
4827         if ((~sdram_en0)) begin
4828                 sdram_time0 <= 5'd31;
4829         end else begin
4830                 if ((~sdram_max_time0)) begin
4831                         sdram_time0 <= (sdram_time0 - 1'd1);
4832                 end
4833         end
4834         if ((~sdram_en1)) begin
4835                 sdram_time1 <= 4'd15;
4836         end else begin
4837                 if ((~sdram_max_time1)) begin
4838                         sdram_time1 <= (sdram_time1 - 1'd1);
4839                 end
4840         end
4841         if (sdram_choose_cmd_ce) begin
4842                 case (sdram_choose_cmd_grant)
4843                         1'd0: begin
4844                                 if (sdram_choose_cmd_request[1]) begin
4845                                         sdram_choose_cmd_grant <= 1'd1;
4846                                 end else begin
4847                                         if (sdram_choose_cmd_request[2]) begin
4848                                                 sdram_choose_cmd_grant <= 2'd2;
4849                                         end else begin
4850                                                 if (sdram_choose_cmd_request[3]) begin
4851                                                         sdram_choose_cmd_grant <= 2'd3;
4852                                                 end
4853                                         end
4854                                 end
4855                         end
4856                         1'd1: begin
4857                                 if (sdram_choose_cmd_request[2]) begin
4858                                         sdram_choose_cmd_grant <= 2'd2;
4859                                 end else begin
4860                                         if (sdram_choose_cmd_request[3]) begin
4861                                                 sdram_choose_cmd_grant <= 2'd3;
4862                                         end else begin
4863                                                 if (sdram_choose_cmd_request[0]) begin
4864                                                         sdram_choose_cmd_grant <= 1'd0;
4865                                                 end
4866                                         end
4867                                 end
4868                         end
4869                         2'd2: begin
4870                                 if (sdram_choose_cmd_request[3]) begin
4871                                         sdram_choose_cmd_grant <= 2'd3;
4872                                 end else begin
4873                                         if (sdram_choose_cmd_request[0]) begin
4874                                                 sdram_choose_cmd_grant <= 1'd0;
4875                                         end else begin
4876                                                 if (sdram_choose_cmd_request[1]) begin
4877                                                         sdram_choose_cmd_grant <= 1'd1;
4878                                                 end
4879                                         end
4880                                 end
4881                         end
4882                         2'd3: begin
4883                                 if (sdram_choose_cmd_request[0]) begin
4884                                         sdram_choose_cmd_grant <= 1'd0;
4885                                 end else begin
4886                                         if (sdram_choose_cmd_request[1]) begin
4887                                                 sdram_choose_cmd_grant <= 1'd1;
4888                                         end else begin
4889                                                 if (sdram_choose_cmd_request[2]) begin
4890                                                         sdram_choose_cmd_grant <= 2'd2;
4891                                                 end
4892                                         end
4893                                 end
4894                         end
4895                 endcase
4896         end
4897         if (sdram_choose_req_ce) begin
4898                 case (sdram_choose_req_grant)
4899                         1'd0: begin
4900                                 if (sdram_choose_req_request[1]) begin
4901                                         sdram_choose_req_grant <= 1'd1;
4902                                 end else begin
4903                                         if (sdram_choose_req_request[2]) begin
4904                                                 sdram_choose_req_grant <= 2'd2;
4905                                         end else begin
4906                                                 if (sdram_choose_req_request[3]) begin
4907                                                         sdram_choose_req_grant <= 2'd3;
4908                                                 end
4909                                         end
4910                                 end
4911                         end
4912                         1'd1: begin
4913                                 if (sdram_choose_req_request[2]) begin
4914                                         sdram_choose_req_grant <= 2'd2;
4915                                 end else begin
4916                                         if (sdram_choose_req_request[3]) begin
4917                                                 sdram_choose_req_grant <= 2'd3;
4918                                         end else begin
4919                                                 if (sdram_choose_req_request[0]) begin
4920                                                         sdram_choose_req_grant <= 1'd0;
4921                                                 end
4922                                         end
4923                                 end
4924                         end
4925                         2'd2: begin
4926                                 if (sdram_choose_req_request[3]) begin
4927                                         sdram_choose_req_grant <= 2'd3;
4928                                 end else begin
4929                                         if (sdram_choose_req_request[0]) begin
4930                                                 sdram_choose_req_grant <= 1'd0;
4931                                         end else begin
4932                                                 if (sdram_choose_req_request[1]) begin
4933                                                         sdram_choose_req_grant <= 1'd1;
4934                                                 end
4935                                         end
4936                                 end
4937                         end
4938                         2'd3: begin
4939                                 if (sdram_choose_req_request[0]) begin
4940                                         sdram_choose_req_grant <= 1'd0;
4941                                 end else begin
4942                                         if (sdram_choose_req_request[1]) begin
4943                                                 sdram_choose_req_grant <= 1'd1;
4944                                         end else begin
4945                                                 if (sdram_choose_req_request[2]) begin
4946                                                         sdram_choose_req_grant <= 2'd2;
4947                                                 end
4948                                         end
4949                                 end
4950                         end
4951                 endcase
4952         end
4953         sdram_dfi_p0_cs_n <= 1'd0;
4954         sdram_dfi_p0_bank <= array_muxed0;
4955         sdram_dfi_p0_address <= array_muxed1;
4956         sdram_dfi_p0_cas_n <= (~array_muxed2);
4957         sdram_dfi_p0_ras_n <= (~array_muxed3);
4958         sdram_dfi_p0_we_n <= (~array_muxed4);
4959         sdram_dfi_p0_rddata_en <= array_muxed5;
4960         sdram_dfi_p0_wrdata_en <= array_muxed6;
4961         if (sdram_tccdcon_valid) begin
4962                 sdram_tccdcon_count <= 1'd0;
4963                 if (1'd1) begin
4964                         sdram_tccdcon_ready <= 1'd1;
4965                 end else begin
4966                         sdram_tccdcon_ready <= 1'd0;
4967                 end
4968         end else begin
4969                 if ((~sdram_tccdcon_ready)) begin
4970                         sdram_tccdcon_count <= (sdram_tccdcon_count - 1'd1);
4971                         if ((sdram_tccdcon_count == 1'd1)) begin
4972                                 sdram_tccdcon_ready <= 1'd1;
4973                         end
4974                 end
4975         end
4976         if (sdram_twtrcon_valid) begin
4977                 sdram_twtrcon_count <= 3'd4;
4978                 if (1'd0) begin
4979                         sdram_twtrcon_ready <= 1'd1;
4980                 end else begin
4981                         sdram_twtrcon_ready <= 1'd0;
4982                 end
4983         end else begin
4984                 if ((~sdram_twtrcon_ready)) begin
4985                         sdram_twtrcon_count <= (sdram_twtrcon_count - 1'd1);
4986                         if ((sdram_twtrcon_count == 1'd1)) begin
4987                                 sdram_twtrcon_ready <= 1'd1;
4988                         end
4989                 end
4990         end
4991         subfragments_multiplexer_state <= subfragments_multiplexer_next_state;
4992         subfragments_new_master_wdata_ready <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_wdata_ready)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_wdata_ready)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_wdata_ready)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_wdata_ready));
4993         subfragments_new_master_rdata_valid0 <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_rdata_valid)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_rdata_valid)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_rdata_valid)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_rdata_valid));
4994         subfragments_new_master_rdata_valid1 <= subfragments_new_master_rdata_valid0;
4995         subfragments_new_master_rdata_valid2 <= subfragments_new_master_rdata_valid1;
4996         subfragments_new_master_rdata_valid3 <= subfragments_new_master_rdata_valid2;
4997         if ((litedram_wb_ack | converter_skip)) begin
4998                 converter_dat_r <= wb_sdram_dat_r;
4999         end
5000         subfragments_state <= subfragments_next_state;
5001         if (converter_counter_subfragments_next_value_ce) begin
5002                 converter_counter <= converter_counter_subfragments_next_value;
5003         end
5004         if (converter_reset) begin
5005                 converter_counter <= 1'd0;
5006                 subfragments_state <= 1'd0;
5007         end
5008         if (litedram_wb_ack) begin
5009                 cmd_consumed <= 1'd0;
5010                 wdata_consumed <= 1'd0;
5011         end else begin
5012                 if ((port_cmd_valid & port_cmd_ready)) begin
5013                         cmd_consumed <= 1'd1;
5014                 end
5015                 if ((port_wdata_valid & port_wdata_ready)) begin
5016                         wdata_consumed <= 1'd1;
5017                 end
5018         end
5019         uart_phy_sink_ready <= 1'd0;
5020         if (((uart_phy_sink_valid & (~uart_phy_tx_busy)) & (~uart_phy_sink_ready))) begin
5021                 uart_phy_tx_reg <= uart_phy_sink_payload_data;
5022                 uart_phy_tx_bitcount <= 1'd0;
5023                 uart_phy_tx_busy <= 1'd1;
5024                 libresocsim_libresoc_constraintmanager_uart_tx <= 1'd0;
5025         end else begin
5026                 if ((uart_phy_uart_clk_txen & uart_phy_tx_busy)) begin
5027                         uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1);
5028                         if ((uart_phy_tx_bitcount == 4'd8)) begin
5029                                 libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5030                         end else begin
5031                                 if ((uart_phy_tx_bitcount == 4'd9)) begin
5032                                         libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5033                                         uart_phy_tx_busy <= 1'd0;
5034                                         uart_phy_sink_ready <= 1'd1;
5035                                 end else begin
5036                                         libresocsim_libresoc_constraintmanager_uart_tx <= uart_phy_tx_reg[0];
5037                                         uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]};
5038                                 end
5039                         end
5040                 end
5041         end
5042         if (uart_phy_tx_busy) begin
5043                 {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= (uart_phy_phase_accumulator_tx + uart_phy_storage);
5044         end else begin
5045                 {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= uart_phy_storage;
5046         end
5047         uart_phy_source_valid <= 1'd0;
5048         uart_phy_rx_r <= uart_phy_rx;
5049         if ((~uart_phy_rx_busy)) begin
5050                 if (((~uart_phy_rx) & uart_phy_rx_r)) begin
5051                         uart_phy_rx_busy <= 1'd1;
5052                         uart_phy_rx_bitcount <= 1'd0;
5053                 end
5054         end else begin
5055                 if (uart_phy_uart_clk_rxen) begin
5056                         uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1);
5057                         if ((uart_phy_rx_bitcount == 1'd0)) begin
5058                                 if (uart_phy_rx) begin
5059                                         uart_phy_rx_busy <= 1'd0;
5060                                 end
5061                         end else begin
5062                                 if ((uart_phy_rx_bitcount == 4'd9)) begin
5063                                         uart_phy_rx_busy <= 1'd0;
5064                                         if (uart_phy_rx) begin
5065                                                 uart_phy_source_payload_data <= uart_phy_rx_reg;
5066                                                 uart_phy_source_valid <= 1'd1;
5067                                         end
5068                                 end else begin
5069                                         uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]};
5070                                 end
5071                         end
5072                 end
5073         end
5074         if (uart_phy_rx_busy) begin
5075                 {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= (uart_phy_phase_accumulator_rx + uart_phy_storage);
5076         end else begin
5077                 {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= 32'd2147483648;
5078         end
5079         if (tx_clear) begin
5080                 tx_pending <= 1'd0;
5081         end
5082         tx_old_trigger <= tx_trigger;
5083         if (((~tx_trigger) & tx_old_trigger)) begin
5084                 tx_pending <= 1'd1;
5085         end
5086         if (rx_clear) begin
5087                 rx_pending <= 1'd0;
5088         end
5089         rx_old_trigger <= rx_trigger;
5090         if (((~rx_trigger) & rx_old_trigger)) begin
5091                 rx_pending <= 1'd1;
5092         end
5093         if (tx_fifo_syncfifo_re) begin
5094                 tx_fifo_readable <= 1'd1;
5095         end else begin
5096                 if (tx_fifo_re) begin
5097                         tx_fifo_readable <= 1'd0;
5098                 end
5099         end
5100         if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin
5101                 tx_fifo_produce <= (tx_fifo_produce + 1'd1);
5102         end
5103         if (tx_fifo_do_read) begin
5104                 tx_fifo_consume <= (tx_fifo_consume + 1'd1);
5105         end
5106         if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin
5107                 if ((~tx_fifo_do_read)) begin
5108                         tx_fifo_level0 <= (tx_fifo_level0 + 1'd1);
5109                 end
5110         end else begin
5111                 if (tx_fifo_do_read) begin
5112                         tx_fifo_level0 <= (tx_fifo_level0 - 1'd1);
5113                 end
5114         end
5115         if (rx_fifo_syncfifo_re) begin
5116                 rx_fifo_readable <= 1'd1;
5117         end else begin
5118                 if (rx_fifo_re) begin
5119                         rx_fifo_readable <= 1'd0;
5120                 end
5121         end
5122         if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin
5123                 rx_fifo_produce <= (rx_fifo_produce + 1'd1);
5124         end
5125         if (rx_fifo_do_read) begin
5126                 rx_fifo_consume <= (rx_fifo_consume + 1'd1);
5127         end
5128         if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin
5129                 if ((~rx_fifo_do_read)) begin
5130                         rx_fifo_level0 <= (rx_fifo_level0 + 1'd1);
5131                 end
5132         end else begin
5133                 if (rx_fifo_do_read) begin
5134                         rx_fifo_level0 <= (rx_fifo_level0 - 1'd1);
5135                 end
5136         end
5137         if (reset) begin
5138                 tx_pending <= 1'd0;
5139                 tx_old_trigger <= 1'd0;
5140                 rx_pending <= 1'd0;
5141                 rx_old_trigger <= 1'd0;
5142                 tx_fifo_readable <= 1'd0;
5143                 tx_fifo_level0 <= 5'd0;
5144                 tx_fifo_produce <= 4'd0;
5145                 tx_fifo_consume <= 4'd0;
5146                 rx_fifo_readable <= 1'd0;
5147                 rx_fifo_level0 <= 5'd0;
5148                 rx_fifo_produce <= 4'd0;
5149                 rx_fifo_consume <= 4'd0;
5150         end
5151         libresocsim_state <= libresocsim_next_state;
5152         if (libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0) begin
5153                 libresocsim_libresocsim_dat_w <= libresocsim_libresocsim_dat_w_libresocsim_next_value0;
5154         end
5155         if (libresocsim_libresocsim_adr_libresocsim_next_value_ce1) begin
5156                 libresocsim_libresocsim_adr <= libresocsim_libresocsim_adr_libresocsim_next_value1;
5157         end
5158         if (libresocsim_libresocsim_we_libresocsim_next_value_ce2) begin
5159                 libresocsim_libresocsim_we <= libresocsim_libresocsim_we_libresocsim_next_value2;
5160         end
5161         case (libresocsim_grant)
5162                 1'd0: begin
5163                         if ((~libresocsim_request[0])) begin
5164                                 if (libresocsim_request[1]) begin
5165                                         libresocsim_grant <= 1'd1;
5166                                 end else begin
5167                                         if (libresocsim_request[2]) begin
5168                                                 libresocsim_grant <= 2'd2;
5169                                         end
5170                                 end
5171                         end
5172                 end
5173                 1'd1: begin
5174                         if ((~libresocsim_request[1])) begin
5175                                 if (libresocsim_request[2]) begin
5176                                         libresocsim_grant <= 2'd2;
5177                                 end else begin
5178                                         if (libresocsim_request[0]) begin
5179                                                 libresocsim_grant <= 1'd0;
5180                                         end
5181                                 end
5182                         end
5183                 end
5184                 2'd2: begin
5185                         if ((~libresocsim_request[2])) begin
5186                                 if (libresocsim_request[0]) begin
5187                                         libresocsim_grant <= 1'd0;
5188                                 end else begin
5189                                         if (libresocsim_request[1]) begin
5190                                                 libresocsim_grant <= 1'd1;
5191                                         end
5192                                 end
5193                         end
5194                 end
5195         endcase
5196         libresocsim_slave_sel_r <= libresocsim_slave_sel;
5197         if (libresocsim_wait) begin
5198                 if ((~libresocsim_done)) begin
5199                         libresocsim_count <= (libresocsim_count - 1'd1);
5200                 end
5201         end else begin
5202                 libresocsim_count <= 20'd1000000;
5203         end
5204         libresocsim_interface0_bank_bus_dat_r <= 1'd0;
5205         if (libresocsim_csrbank0_sel) begin
5206                 case (libresocsim_interface0_bank_bus_adr[3:0])
5207                         1'd0: begin
5208                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_reset0_w;
5209                         end
5210                         1'd1: begin
5211                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch3_w;
5212                         end
5213                         2'd2: begin
5214                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch2_w;
5215                         end
5216                         2'd3: begin
5217                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch1_w;
5218                         end
5219                         3'd4: begin
5220                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch0_w;
5221                         end
5222                         3'd5: begin
5223                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors3_w;
5224                         end
5225                         3'd6: begin
5226                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors2_w;
5227                         end
5228                         3'd7: begin
5229                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors1_w;
5230                         end
5231                         4'd8: begin
5232                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors0_w;
5233                         end
5234                 endcase
5235         end
5236         if (libresocsim_csrbank0_reset0_re) begin
5237                 libresocsim_reset_storage <= libresocsim_csrbank0_reset0_r;
5238         end
5239         libresocsim_reset_re <= libresocsim_csrbank0_reset0_re;
5240         if (libresocsim_csrbank0_scratch3_re) begin
5241                 libresocsim_scratch_storage[31:24] <= libresocsim_csrbank0_scratch3_r;
5242         end
5243         if (libresocsim_csrbank0_scratch2_re) begin
5244                 libresocsim_scratch_storage[23:16] <= libresocsim_csrbank0_scratch2_r;
5245         end
5246         if (libresocsim_csrbank0_scratch1_re) begin
5247                 libresocsim_scratch_storage[15:8] <= libresocsim_csrbank0_scratch1_r;
5248         end
5249         if (libresocsim_csrbank0_scratch0_re) begin
5250                 libresocsim_scratch_storage[7:0] <= libresocsim_csrbank0_scratch0_r;
5251         end
5252         libresocsim_scratch_re <= libresocsim_csrbank0_scratch0_re;
5253         libresocsim_interface1_bank_bus_dat_r <= 1'd0;
5254         if (libresocsim_csrbank1_sel) begin
5255                 case (libresocsim_interface1_bank_bus_adr[1:0])
5256                         1'd0: begin
5257                                 libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_oe0_w;
5258                         end
5259                         1'd1: begin
5260                                 libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_in_w;
5261                         end
5262                         2'd2: begin
5263                                 libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_out0_w;
5264                         end
5265                 endcase
5266         end
5267         if (libresocsim_csrbank1_oe0_re) begin
5268                 gpio0_oe_storage[7:0] <= libresocsim_csrbank1_oe0_r;
5269         end
5270         gpio0_oe_re <= libresocsim_csrbank1_oe0_re;
5271         if (libresocsim_csrbank1_out0_re) begin
5272                 gpio0_out_storage[7:0] <= libresocsim_csrbank1_out0_r;
5273         end
5274         gpio0_out_re <= libresocsim_csrbank1_out0_re;
5275         libresocsim_interface2_bank_bus_dat_r <= 1'd0;
5276         if (libresocsim_csrbank2_sel) begin
5277                 case (libresocsim_interface2_bank_bus_adr[1:0])
5278                         1'd0: begin
5279                                 libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_oe0_w;
5280                         end
5281                         1'd1: begin
5282                                 libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_in_w;
5283                         end
5284                         2'd2: begin
5285                                 libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_out0_w;
5286                         end
5287                 endcase
5288         end
5289         if (libresocsim_csrbank2_oe0_re) begin
5290                 gpio1_oe_storage[7:0] <= libresocsim_csrbank2_oe0_r;
5291         end
5292         gpio1_oe_re <= libresocsim_csrbank2_oe0_re;
5293         if (libresocsim_csrbank2_out0_re) begin
5294                 gpio1_out_storage[7:0] <= libresocsim_csrbank2_out0_r;
5295         end
5296         gpio1_out_re <= libresocsim_csrbank2_out0_re;
5297         libresocsim_interface3_bank_bus_dat_r <= 1'd0;
5298         if (libresocsim_csrbank3_sel) begin
5299                 case (libresocsim_interface3_bank_bus_adr[0])
5300                         1'd0: begin
5301                                 libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_w0_w;
5302                         end
5303                         1'd1: begin
5304                                 libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_r_w;
5305                         end
5306                 endcase
5307         end
5308         if (libresocsim_csrbank3_w0_re) begin
5309                 i2c_storage[2:0] <= libresocsim_csrbank3_w0_r;
5310         end
5311         i2c_re <= libresocsim_csrbank3_w0_re;
5312         libresocsim_interface4_bank_bus_dat_r <= 1'd0;
5313         if (libresocsim_csrbank4_sel) begin
5314                 case (libresocsim_interface4_bank_bus_adr[3:0])
5315                         1'd0: begin
5316                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_control0_w;
5317                         end
5318                         1'd1: begin
5319                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_command0_w;
5320                         end
5321                         2'd2: begin
5322                                 libresocsim_interface4_bank_bus_dat_r <= sdram_command_issue_w;
5323                         end
5324                         2'd3: begin
5325                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address1_w;
5326                         end
5327                         3'd4: begin
5328                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address0_w;
5329                         end
5330                         3'd5: begin
5331                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_baddress0_w;
5332                         end
5333                         3'd6: begin
5334                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata1_w;
5335                         end
5336                         3'd7: begin
5337                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata0_w;
5338                         end
5339                         4'd8: begin
5340                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata1_w;
5341                         end
5342                         4'd9: begin
5343                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata0_w;
5344                         end
5345                 endcase
5346         end
5347         if (libresocsim_csrbank4_dfii_control0_re) begin
5348                 sdram_storage[3:0] <= libresocsim_csrbank4_dfii_control0_r;
5349         end
5350         sdram_re <= libresocsim_csrbank4_dfii_control0_re;
5351         if (libresocsim_csrbank4_dfii_pi0_command0_re) begin
5352                 sdram_command_storage[5:0] <= libresocsim_csrbank4_dfii_pi0_command0_r;
5353         end
5354         sdram_command_re <= libresocsim_csrbank4_dfii_pi0_command0_re;
5355         if (libresocsim_csrbank4_dfii_pi0_address1_re) begin
5356                 sdram_address_storage[12:8] <= libresocsim_csrbank4_dfii_pi0_address1_r;
5357         end
5358         if (libresocsim_csrbank4_dfii_pi0_address0_re) begin
5359                 sdram_address_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_address0_r;
5360         end
5361         sdram_address_re <= libresocsim_csrbank4_dfii_pi0_address0_re;
5362         if (libresocsim_csrbank4_dfii_pi0_baddress0_re) begin
5363                 sdram_baddress_storage[1:0] <= libresocsim_csrbank4_dfii_pi0_baddress0_r;
5364         end
5365         sdram_baddress_re <= libresocsim_csrbank4_dfii_pi0_baddress0_re;
5366         if (libresocsim_csrbank4_dfii_pi0_wrdata1_re) begin
5367                 sdram_wrdata_storage[15:8] <= libresocsim_csrbank4_dfii_pi0_wrdata1_r;
5368         end
5369         if (libresocsim_csrbank4_dfii_pi0_wrdata0_re) begin
5370                 sdram_wrdata_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_wrdata0_r;
5371         end
5372         sdram_wrdata_re <= libresocsim_csrbank4_dfii_pi0_wrdata0_re;
5373         libresocsim_interface5_bank_bus_dat_r <= 1'd0;
5374         if (libresocsim_csrbank5_sel) begin
5375                 case (libresocsim_interface5_bank_bus_adr[4:0])
5376                         1'd0: begin
5377                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load3_w;
5378                         end
5379                         1'd1: begin
5380                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load2_w;
5381                         end
5382                         2'd2: begin
5383                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load1_w;
5384                         end
5385                         2'd3: begin
5386                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load0_w;
5387                         end
5388                         3'd4: begin
5389                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload3_w;
5390                         end
5391                         3'd5: begin
5392                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload2_w;
5393                         end
5394                         3'd6: begin
5395                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload1_w;
5396                         end
5397                         3'd7: begin
5398                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload0_w;
5399                         end
5400                         4'd8: begin
5401                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_en0_w;
5402                         end
5403                         4'd9: begin
5404                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_update_value0_w;
5405                         end
5406                         4'd10: begin
5407                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value3_w;
5408                         end
5409                         4'd11: begin
5410                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value2_w;
5411                         end
5412                         4'd12: begin
5413                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value1_w;
5414                         end
5415                         4'd13: begin
5416                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value0_w;
5417                         end
5418                         4'd14: begin
5419                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_status_w;
5420                         end
5421                         4'd15: begin
5422                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_pending_w;
5423                         end
5424                         5'd16: begin
5425                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_ev_enable0_w;
5426                         end
5427                 endcase
5428         end
5429         if (libresocsim_csrbank5_load3_re) begin
5430                 libresocsim_load_storage[31:24] <= libresocsim_csrbank5_load3_r;
5431         end
5432         if (libresocsim_csrbank5_load2_re) begin
5433                 libresocsim_load_storage[23:16] <= libresocsim_csrbank5_load2_r;
5434         end
5435         if (libresocsim_csrbank5_load1_re) begin
5436                 libresocsim_load_storage[15:8] <= libresocsim_csrbank5_load1_r;
5437         end
5438         if (libresocsim_csrbank5_load0_re) begin
5439                 libresocsim_load_storage[7:0] <= libresocsim_csrbank5_load0_r;
5440         end
5441         libresocsim_load_re <= libresocsim_csrbank5_load0_re;
5442         if (libresocsim_csrbank5_reload3_re) begin
5443                 libresocsim_reload_storage[31:24] <= libresocsim_csrbank5_reload3_r;
5444         end
5445         if (libresocsim_csrbank5_reload2_re) begin
5446                 libresocsim_reload_storage[23:16] <= libresocsim_csrbank5_reload2_r;
5447         end
5448         if (libresocsim_csrbank5_reload1_re) begin
5449                 libresocsim_reload_storage[15:8] <= libresocsim_csrbank5_reload1_r;
5450         end
5451         if (libresocsim_csrbank5_reload0_re) begin
5452                 libresocsim_reload_storage[7:0] <= libresocsim_csrbank5_reload0_r;
5453         end
5454         libresocsim_reload_re <= libresocsim_csrbank5_reload0_re;
5455         if (libresocsim_csrbank5_en0_re) begin
5456                 libresocsim_en_storage <= libresocsim_csrbank5_en0_r;
5457         end
5458         libresocsim_en_re <= libresocsim_csrbank5_en0_re;
5459         if (libresocsim_csrbank5_update_value0_re) begin
5460                 libresocsim_update_value_storage <= libresocsim_csrbank5_update_value0_r;
5461         end
5462         libresocsim_update_value_re <= libresocsim_csrbank5_update_value0_re;
5463         if (libresocsim_csrbank5_ev_enable0_re) begin
5464                 libresocsim_eventmanager_storage <= libresocsim_csrbank5_ev_enable0_r;
5465         end
5466         libresocsim_eventmanager_re <= libresocsim_csrbank5_ev_enable0_re;
5467         libresocsim_interface6_bank_bus_dat_r <= 1'd0;
5468         if (libresocsim_csrbank6_sel) begin
5469                 case (libresocsim_interface6_bank_bus_adr[2:0])
5470                         1'd0: begin
5471                                 libresocsim_interface6_bank_bus_dat_r <= rxtx_w;
5472                         end
5473                         1'd1: begin
5474                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txfull_w;
5475                         end
5476                         2'd2: begin
5477                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxempty_w;
5478                         end
5479                         2'd3: begin
5480                                 libresocsim_interface6_bank_bus_dat_r <= eventmanager_status_w;
5481                         end
5482                         3'd4: begin
5483                                 libresocsim_interface6_bank_bus_dat_r <= eventmanager_pending_w;
5484                         end
5485                         3'd5: begin
5486                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_ev_enable0_w;
5487                         end
5488                         3'd6: begin
5489                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txempty_w;
5490                         end
5491                         3'd7: begin
5492                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxfull_w;
5493                         end
5494                 endcase
5495         end
5496         if (libresocsim_csrbank6_ev_enable0_re) begin
5497                 eventmanager_storage[1:0] <= libresocsim_csrbank6_ev_enable0_r;
5498         end
5499         eventmanager_re <= libresocsim_csrbank6_ev_enable0_re;
5500         libresocsim_interface7_bank_bus_dat_r <= 1'd0;
5501         if (libresocsim_csrbank7_sel) begin
5502                 case (libresocsim_interface7_bank_bus_adr[1:0])
5503                         1'd0: begin
5504                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word3_w;
5505                         end
5506                         1'd1: begin
5507                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word2_w;
5508                         end
5509                         2'd2: begin
5510                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word1_w;
5511                         end
5512                         2'd3: begin
5513                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word0_w;
5514                         end
5515                 endcase
5516         end
5517         if (libresocsim_csrbank7_tuning_word3_re) begin
5518                 uart_phy_storage[31:24] <= libresocsim_csrbank7_tuning_word3_r;
5519         end
5520         if (libresocsim_csrbank7_tuning_word2_re) begin
5521                 uart_phy_storage[23:16] <= libresocsim_csrbank7_tuning_word2_r;
5522         end
5523         if (libresocsim_csrbank7_tuning_word1_re) begin
5524                 uart_phy_storage[15:8] <= libresocsim_csrbank7_tuning_word1_r;
5525         end
5526         if (libresocsim_csrbank7_tuning_word0_re) begin
5527                 uart_phy_storage[7:0] <= libresocsim_csrbank7_tuning_word0_r;
5528         end
5529         uart_phy_re <= libresocsim_csrbank7_tuning_word0_re;
5530         if (sys_rst_1) begin
5531                 libresocsim_reset_storage <= 1'd0;
5532                 libresocsim_reset_re <= 1'd0;
5533                 libresocsim_scratch_storage <= 32'd305419896;
5534                 libresocsim_scratch_re <= 1'd0;
5535                 libresocsim_bus_errors <= 32'd0;
5536                 libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5537                 libresocsim_converter0_counter <= 1'd0;
5538                 libresocsim_converter1_counter <= 1'd0;
5539                 libresocsim_ram_bus_ack <= 1'd0;
5540                 libresocsim_load_storage <= 32'd0;
5541                 libresocsim_load_re <= 1'd0;
5542                 libresocsim_reload_storage <= 32'd0;
5543                 libresocsim_reload_re <= 1'd0;
5544                 libresocsim_en_storage <= 1'd0;
5545                 libresocsim_en_re <= 1'd0;
5546                 libresocsim_update_value_storage <= 1'd0;
5547                 libresocsim_update_value_re <= 1'd0;
5548                 libresocsim_value_status <= 32'd0;
5549                 libresocsim_zero_pending <= 1'd0;
5550                 libresocsim_zero_old_trigger <= 1'd0;
5551                 libresocsim_eventmanager_storage <= 1'd0;
5552                 libresocsim_eventmanager_re <= 1'd0;
5553                 libresocsim_value <= 32'd0;
5554                 ram_bus_ram_bus_ack <= 1'd0;
5555                 dfi_p0_rddata_valid <= 1'd0;
5556                 rddata_en <= 3'd0;
5557                 sdram_storage <= 4'd1;
5558                 sdram_re <= 1'd0;
5559                 sdram_command_storage <= 6'd0;
5560                 sdram_command_re <= 1'd0;
5561                 sdram_address_re <= 1'd0;
5562                 sdram_baddress_re <= 1'd0;
5563                 sdram_wrdata_re <= 1'd0;
5564                 sdram_status <= 16'd0;
5565                 sdram_dfi_p0_address <= 13'd0;
5566                 sdram_dfi_p0_bank <= 2'd0;
5567                 sdram_dfi_p0_cas_n <= 1'd1;
5568                 sdram_dfi_p0_cs_n <= 1'd1;
5569                 sdram_dfi_p0_ras_n <= 1'd1;
5570                 sdram_dfi_p0_we_n <= 1'd1;
5571                 sdram_dfi_p0_wrdata_en <= 1'd0;
5572                 sdram_dfi_p0_rddata_en <= 1'd0;
5573                 sdram_timer_count1 <= 10'd781;
5574                 sdram_postponer_req_o <= 1'd0;
5575                 sdram_postponer_count <= 1'd0;
5576                 sdram_sequencer_done1 <= 1'd0;
5577                 sdram_sequencer_counter <= 4'd0;
5578                 sdram_sequencer_count <= 1'd0;
5579                 sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0;
5580                 sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0;
5581                 sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0;
5582                 sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0;
5583                 sdram_bankmachine0_row <= 13'd0;
5584                 sdram_bankmachine0_row_opened <= 1'd0;
5585                 sdram_bankmachine0_twtpcon_ready <= 1'd0;
5586                 sdram_bankmachine0_twtpcon_count <= 3'd0;
5587                 sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0;
5588                 sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0;
5589                 sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0;
5590                 sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0;
5591                 sdram_bankmachine1_row <= 13'd0;
5592                 sdram_bankmachine1_row_opened <= 1'd0;
5593                 sdram_bankmachine1_twtpcon_ready <= 1'd0;
5594                 sdram_bankmachine1_twtpcon_count <= 3'd0;
5595                 sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0;
5596                 sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0;
5597                 sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0;
5598                 sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0;
5599                 sdram_bankmachine2_row <= 13'd0;
5600                 sdram_bankmachine2_row_opened <= 1'd0;
5601                 sdram_bankmachine2_twtpcon_ready <= 1'd0;
5602                 sdram_bankmachine2_twtpcon_count <= 3'd0;
5603                 sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0;
5604                 sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0;
5605                 sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0;
5606                 sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0;
5607                 sdram_bankmachine3_row <= 13'd0;
5608                 sdram_bankmachine3_row_opened <= 1'd0;
5609                 sdram_bankmachine3_twtpcon_ready <= 1'd0;
5610                 sdram_bankmachine3_twtpcon_count <= 3'd0;
5611                 sdram_choose_cmd_grant <= 2'd0;
5612                 sdram_choose_req_grant <= 2'd0;
5613                 sdram_tccdcon_ready <= 1'd0;
5614                 sdram_tccdcon_count <= 1'd0;
5615                 sdram_twtrcon_ready <= 1'd0;
5616                 sdram_twtrcon_count <= 3'd0;
5617                 sdram_time0 <= 5'd0;
5618                 sdram_time1 <= 4'd0;
5619                 converter_counter <= 1'd0;
5620                 cmd_consumed <= 1'd0;
5621                 wdata_consumed <= 1'd0;
5622                 uart_phy_storage <= 32'd9895604;
5623                 uart_phy_re <= 1'd0;
5624                 uart_phy_sink_ready <= 1'd0;
5625                 uart_phy_uart_clk_txen <= 1'd0;
5626                 uart_phy_tx_busy <= 1'd0;
5627                 uart_phy_source_valid <= 1'd0;
5628                 uart_phy_uart_clk_rxen <= 1'd0;
5629                 uart_phy_rx_r <= 1'd0;
5630                 uart_phy_rx_busy <= 1'd0;
5631                 tx_pending <= 1'd0;
5632                 tx_old_trigger <= 1'd0;
5633                 rx_pending <= 1'd0;
5634                 rx_old_trigger <= 1'd0;
5635                 eventmanager_storage <= 2'd0;
5636                 eventmanager_re <= 1'd0;
5637                 tx_fifo_readable <= 1'd0;
5638                 tx_fifo_level0 <= 5'd0;
5639                 tx_fifo_produce <= 4'd0;
5640                 tx_fifo_consume <= 4'd0;
5641                 rx_fifo_readable <= 1'd0;
5642                 rx_fifo_level0 <= 5'd0;
5643                 rx_fifo_produce <= 4'd0;
5644                 rx_fifo_consume <= 4'd0;
5645                 gpio0_oe_storage <= 8'd0;
5646                 gpio0_oe_re <= 1'd0;
5647                 gpio0_out_storage <= 8'd0;
5648                 gpio0_out_re <= 1'd0;
5649                 gpio1_oe_storage <= 8'd0;
5650                 gpio1_oe_re <= 1'd0;
5651                 gpio1_out_storage <= 8'd0;
5652                 gpio1_out_re <= 1'd0;
5653                 dummy <= 35'd0;
5654                 i2c_storage <= 3'd0;
5655                 i2c_re <= 1'd0;
5656                 subfragments_converter0_state <= 1'd0;
5657                 subfragments_converter1_state <= 1'd0;
5658                 subfragments_refresher_state <= 2'd0;
5659                 subfragments_bankmachine0_state <= 3'd0;
5660                 subfragments_bankmachine1_state <= 3'd0;
5661                 subfragments_bankmachine2_state <= 3'd0;
5662                 subfragments_bankmachine3_state <= 3'd0;
5663                 subfragments_multiplexer_state <= 3'd0;
5664                 subfragments_new_master_wdata_ready <= 1'd0;
5665                 subfragments_new_master_rdata_valid0 <= 1'd0;
5666                 subfragments_new_master_rdata_valid1 <= 1'd0;
5667                 subfragments_new_master_rdata_valid2 <= 1'd0;
5668                 subfragments_new_master_rdata_valid3 <= 1'd0;
5669                 subfragments_state <= 1'd0;
5670                 libresocsim_libresocsim_we <= 1'd0;
5671                 libresocsim_grant <= 2'd0;
5672                 libresocsim_slave_sel_r <= 10'd0;
5673                 libresocsim_count <= 20'd1000000;
5674                 libresocsim_state <= 2'd0;
5675         end
5676         regs0 <= libresocsim_libresoc_constraintmanager_uart_rx;
5677         regs1 <= regs0;
5678 end
5679
5680 reg [31:0] mem[0:31];
5681 reg [4:0] memadr;
5682 always @(posedge sys_clk_1) begin
5683         if (libresocsim_we[0])
5684                 mem[libresocsim_adr][7:0] <= libresocsim_dat_w[7:0];
5685         if (libresocsim_we[1])
5686                 mem[libresocsim_adr][15:8] <= libresocsim_dat_w[15:8];
5687         if (libresocsim_we[2])
5688                 mem[libresocsim_adr][23:16] <= libresocsim_dat_w[23:16];
5689         if (libresocsim_we[3])
5690                 mem[libresocsim_adr][31:24] <= libresocsim_dat_w[31:24];
5691         memadr <= libresocsim_adr;
5692 end
5693
5694 assign libresocsim_dat_r = mem[memadr];
5695
5696 initial begin
5697         $readmemh("mem.init", mem);
5698 end
5699
5700 reg [31:0] mem_1[0:31];
5701 reg [4:0] memadr_1;
5702 always @(posedge sys_clk_1) begin
5703         if (ram_we[0])
5704                 mem_1[ram_adr][7:0] <= ram_dat_w[7:0];
5705         if (ram_we[1])
5706                 mem_1[ram_adr][15:8] <= ram_dat_w[15:8];
5707         if (ram_we[2])
5708                 mem_1[ram_adr][23:16] <= ram_dat_w[23:16];
5709         if (ram_we[3])
5710                 mem_1[ram_adr][31:24] <= ram_dat_w[31:24];
5711         memadr_1 <= ram_adr;
5712 end
5713
5714 assign ram_dat_r = mem_1[memadr_1];
5715
5716 initial begin
5717         $readmemh("mem_1.init", mem_1);
5718 end
5719
5720 reg [24:0] storage[0:7];
5721 reg [24:0] memdat;
5722 always @(posedge sys_clk_1) begin
5723         if (sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
5724                 storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
5725         memdat <= storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
5726 end
5727
5728 always @(posedge sys_clk_1) begin
5729 end
5730
5731 assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
5732 assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
5733
5734 reg [24:0] storage_1[0:7];
5735 reg [24:0] memdat_1;
5736 always @(posedge sys_clk_1) begin
5737         if (sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
5738                 storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
5739         memdat_1 <= storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
5740 end
5741
5742 always @(posedge sys_clk_1) begin
5743 end
5744
5745 assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
5746 assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
5747
5748 reg [24:0] storage_2[0:7];
5749 reg [24:0] memdat_2;
5750 always @(posedge sys_clk_1) begin
5751         if (sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
5752                 storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
5753         memdat_2 <= storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
5754 end
5755
5756 always @(posedge sys_clk_1) begin
5757 end
5758
5759 assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
5760 assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
5761
5762 reg [24:0] storage_3[0:7];
5763 reg [24:0] memdat_3;
5764 always @(posedge sys_clk_1) begin
5765         if (sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
5766                 storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
5767         memdat_3 <= storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
5768 end
5769
5770 always @(posedge sys_clk_1) begin
5771 end
5772
5773 assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
5774 assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
5775
5776 reg [9:0] storage_4[0:15];
5777 reg [9:0] memdat_4;
5778 reg [9:0] memdat_5;
5779 always @(posedge sys_clk_1) begin
5780         if (tx_fifo_wrport_we)
5781                 storage_4[tx_fifo_wrport_adr] <= tx_fifo_wrport_dat_w;
5782         memdat_4 <= storage_4[tx_fifo_wrport_adr];
5783 end
5784
5785 always @(posedge sys_clk_1) begin
5786         if (tx_fifo_rdport_re)
5787                 memdat_5 <= storage_4[tx_fifo_rdport_adr];
5788 end
5789
5790 assign tx_fifo_wrport_dat_r = memdat_4;
5791 assign tx_fifo_rdport_dat_r = memdat_5;
5792
5793 reg [9:0] storage_5[0:15];
5794 reg [9:0] memdat_6;
5795 reg [9:0] memdat_7;
5796 always @(posedge sys_clk_1) begin
5797         if (rx_fifo_wrport_we)
5798                 storage_5[rx_fifo_wrport_adr] <= rx_fifo_wrport_dat_w;
5799         memdat_6 <= storage_5[rx_fifo_wrport_adr];
5800 end
5801
5802 always @(posedge sys_clk_1) begin
5803         if (rx_fifo_rdport_re)
5804                 memdat_7 <= storage_5[rx_fifo_rdport_adr];
5805 end
5806
5807 assign rx_fifo_wrport_dat_r = memdat_6;
5808 assign rx_fifo_rdport_dat_r = memdat_7;
5809
5810 test_issuer test_issuer(
5811         .TAP_bus__tck(libresocsim_libresoc_jtag_tck),
5812         .TAP_bus__tdi(libresocsim_libresoc_jtag_tdi),
5813         .TAP_bus__tms(libresocsim_libresoc_jtag_tms),
5814         .clk(sys_clk_1),
5815         .clk_sel_i(libresocsim_libresoc_clk_sel),
5816         .core_bigendian_i(1'd0),
5817         .dbus__ack(libresocsim_libresoc_dbus_ack),
5818         .dbus__bte(1'd0),
5819         .dbus__cti(1'd0),
5820         .dbus__dat_r(libresocsim_libresoc_dbus_dat_r),
5821         .dbus__err(libresocsim_libresoc_dbus_err),
5822         .eint_0__pad__i(eint_0),
5823         .eint_1__pad__i(eint_1),
5824         .eint_2__pad__i(eint_2),
5825         .gpio_e10__core__o(libresocsim_libresoc_constraintmanager_gpio_o[10]),
5826         .gpio_e10__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[10]),
5827         .gpio_e10__pad__i(gpio_i[10]),
5828         .gpio_e11__core__o(libresocsim_libresoc_constraintmanager_gpio_o[11]),
5829         .gpio_e11__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[11]),
5830         .gpio_e11__pad__i(gpio_i[11]),
5831         .gpio_e12__core__o(libresocsim_libresoc_constraintmanager_gpio_o[12]),
5832         .gpio_e12__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[12]),
5833         .gpio_e12__pad__i(gpio_i[12]),
5834         .gpio_e13__core__o(libresocsim_libresoc_constraintmanager_gpio_o[13]),
5835         .gpio_e13__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[13]),
5836         .gpio_e13__pad__i(gpio_i[13]),
5837         .gpio_e14__core__o(libresocsim_libresoc_constraintmanager_gpio_o[14]),
5838         .gpio_e14__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[14]),
5839         .gpio_e14__pad__i(gpio_i[14]),
5840         .gpio_e15__core__o(libresocsim_libresoc_constraintmanager_gpio_o[15]),
5841         .gpio_e15__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[15]),
5842         .gpio_e15__pad__i(gpio_i[15]),
5843         .gpio_e8__core__o(libresocsim_libresoc_constraintmanager_gpio_o[8]),
5844         .gpio_e8__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[8]),
5845         .gpio_e8__pad__i(gpio_i[8]),
5846         .gpio_e9__core__o(libresocsim_libresoc_constraintmanager_gpio_o[9]),
5847         .gpio_e9__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[9]),
5848         .gpio_e9__pad__i(gpio_i[9]),
5849         .gpio_s0__core__o(libresocsim_libresoc_constraintmanager_gpio_o[0]),
5850         .gpio_s0__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[0]),
5851         .gpio_s0__pad__i(gpio_i[0]),
5852         .gpio_s1__core__o(libresocsim_libresoc_constraintmanager_gpio_o[1]),
5853         .gpio_s1__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[1]),
5854         .gpio_s1__pad__i(gpio_i[1]),
5855         .gpio_s2__core__o(libresocsim_libresoc_constraintmanager_gpio_o[2]),
5856         .gpio_s2__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[2]),
5857         .gpio_s2__pad__i(gpio_i[2]),
5858         .gpio_s3__core__o(libresocsim_libresoc_constraintmanager_gpio_o[3]),
5859         .gpio_s3__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[3]),
5860         .gpio_s3__pad__i(gpio_i[3]),
5861         .gpio_s4__core__o(libresocsim_libresoc_constraintmanager_gpio_o[4]),
5862         .gpio_s4__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[4]),
5863         .gpio_s4__pad__i(gpio_i[4]),
5864         .gpio_s5__core__o(libresocsim_libresoc_constraintmanager_gpio_o[5]),
5865         .gpio_s5__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[5]),
5866         .gpio_s5__pad__i(gpio_i[5]),
5867         .gpio_s6__core__o(libresocsim_libresoc_constraintmanager_gpio_o[6]),
5868         .gpio_s6__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[6]),
5869         .gpio_s6__pad__i(gpio_i[6]),
5870         .gpio_s7__core__o(libresocsim_libresoc_constraintmanager_gpio_o[7]),
5871         .gpio_s7__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[7]),
5872         .gpio_s7__pad__i(gpio_i[7]),
5873         .ibus__ack(libresocsim_libresoc_ibus_ack),
5874         .ibus__bte(1'd0),
5875         .ibus__cti(1'd0),
5876         .ibus__dat_r(libresocsim_libresoc_ibus_dat_r),
5877         .ibus__err(libresocsim_libresoc_ibus_err),
5878         .icp_wb__adr(libresocsim_libresoc_xics_icp_adr),
5879         .icp_wb__cyc(libresocsim_libresoc_xics_icp_cyc),
5880         .icp_wb__dat_w(libresocsim_libresoc_xics_icp_dat_w),
5881         .icp_wb__sel(libresocsim_libresoc_xics_icp_sel),
5882         .icp_wb__stb(libresocsim_libresoc_xics_icp_stb),
5883         .icp_wb__we(libresocsim_libresoc_xics_icp_we),
5884         .ics_wb__adr(libresocsim_libresoc_xics_ics_adr),
5885         .ics_wb__cyc(libresocsim_libresoc_xics_ics_cyc),
5886         .ics_wb__dat_w(libresocsim_libresoc_xics_ics_dat_w),
5887         .ics_wb__sel(libresocsim_libresoc_xics_ics_sel),
5888         .ics_wb__stb(libresocsim_libresoc_xics_ics_stb),
5889         .ics_wb__we(libresocsim_libresoc_xics_ics_we),
5890         .int_level_i(libresocsim_libresoc_interrupt),
5891         .jtag_wb__ack(libresocsim_libresoc_jtag_wb_ack),
5892         .jtag_wb__dat_r(libresocsim_libresoc_jtag_wb_dat_r),
5893         .jtag_wb__err(libresocsim_libresoc_jtag_wb_err),
5894         .mspi0_clk__core__o(libresocsim_libresoc_constraintmanager_spimaster_clk),
5895         .mspi0_cs_n__core__o(libresocsim_libresoc_constraintmanager_spimaster_cs_n),
5896         .mspi0_miso__pad__i(spimaster_miso),
5897         .mspi0_mosi__core__o(libresocsim_libresoc_constraintmanager_spimaster_mosi),
5898         .mtwi_scl__core__o(libresocsim_libresoc_constraintmanager_i2c_scl),
5899         .mtwi_sda__core__o(libresocsim_libresoc_constraintmanager_i2c_sda_o),
5900         .mtwi_sda__core__oe(libresocsim_libresoc_constraintmanager_i2c_sda_oe),
5901         .mtwi_sda__pad__i(i2c_sda_i),
5902         .pc_i(libresocsim_libresoc0),
5903         .pc_i_ok(1'd0),
5904         .rst((sys_rst_1 | libresocsim_libresoc_reset)),
5905         .sdr_a_0__core__o(libresocsim_libresoc_constraintmanager_sdram_a[0]),
5906         .sdr_a_10__core__o(libresocsim_libresoc_constraintmanager_sdram_a[10]),
5907         .sdr_a_11__core__o(libresocsim_libresoc_constraintmanager_sdram_a[11]),
5908         .sdr_a_12__core__o(libresocsim_libresoc_constraintmanager_sdram_a[12]),
5909         .sdr_a_1__core__o(libresocsim_libresoc_constraintmanager_sdram_a[1]),
5910         .sdr_a_2__core__o(libresocsim_libresoc_constraintmanager_sdram_a[2]),
5911         .sdr_a_3__core__o(libresocsim_libresoc_constraintmanager_sdram_a[3]),
5912         .sdr_a_4__core__o(libresocsim_libresoc_constraintmanager_sdram_a[4]),
5913         .sdr_a_5__core__o(libresocsim_libresoc_constraintmanager_sdram_a[5]),
5914         .sdr_a_6__core__o(libresocsim_libresoc_constraintmanager_sdram_a[6]),
5915         .sdr_a_7__core__o(libresocsim_libresoc_constraintmanager_sdram_a[7]),
5916         .sdr_a_8__core__o(libresocsim_libresoc_constraintmanager_sdram_a[8]),
5917         .sdr_a_9__core__o(libresocsim_libresoc_constraintmanager_sdram_a[9]),
5918         .sdr_ba_0__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[0]),
5919         .sdr_ba_1__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[1]),
5920         .sdr_cas_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cas_n),
5921         .sdr_cke__core__o(libresocsim_libresoc_constraintmanager_sdram_cke),
5922         .sdr_clock__core__o(libresocsim_libresoc_constraintmanager_sdram_clock),
5923         .sdr_cs_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cs_n),
5924         .sdr_dm_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[0]),
5925         .sdr_dm_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[1]),
5926         .sdr_dq_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[0]),
5927         .sdr_dq_0__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[0]),
5928         .sdr_dq_0__pad__i(sdram_dq_i[0]),
5929         .sdr_dq_10__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[10]),
5930         .sdr_dq_10__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[10]),
5931         .sdr_dq_10__pad__i(sdram_dq_i[10]),
5932         .sdr_dq_11__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[11]),
5933         .sdr_dq_11__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[11]),
5934         .sdr_dq_11__pad__i(sdram_dq_i[11]),
5935         .sdr_dq_12__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[12]),
5936         .sdr_dq_12__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[12]),
5937         .sdr_dq_12__pad__i(sdram_dq_i[12]),
5938         .sdr_dq_13__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[13]),
5939         .sdr_dq_13__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[13]),
5940         .sdr_dq_13__pad__i(sdram_dq_i[13]),
5941         .sdr_dq_14__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[14]),
5942         .sdr_dq_14__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[14]),
5943         .sdr_dq_14__pad__i(sdram_dq_i[14]),
5944         .sdr_dq_15__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[15]),
5945         .sdr_dq_15__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[15]),
5946         .sdr_dq_15__pad__i(sdram_dq_i[15]),
5947         .sdr_dq_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[1]),
5948         .sdr_dq_1__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[1]),
5949         .sdr_dq_1__pad__i(sdram_dq_i[1]),
5950         .sdr_dq_2__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[2]),
5951         .sdr_dq_2__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[2]),
5952         .sdr_dq_2__pad__i(sdram_dq_i[2]),
5953         .sdr_dq_3__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[3]),
5954         .sdr_dq_3__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[3]),
5955         .sdr_dq_3__pad__i(sdram_dq_i[3]),
5956         .sdr_dq_4__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[4]),
5957         .sdr_dq_4__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[4]),
5958         .sdr_dq_4__pad__i(sdram_dq_i[4]),
5959         .sdr_dq_5__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[5]),
5960         .sdr_dq_5__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[5]),
5961         .sdr_dq_5__pad__i(sdram_dq_i[5]),
5962         .sdr_dq_6__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[6]),
5963         .sdr_dq_6__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[6]),
5964         .sdr_dq_6__pad__i(sdram_dq_i[6]),
5965         .sdr_dq_7__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[7]),
5966         .sdr_dq_7__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[7]),
5967         .sdr_dq_7__pad__i(sdram_dq_i[7]),
5968         .sdr_dq_8__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[8]),
5969         .sdr_dq_8__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[8]),
5970         .sdr_dq_8__pad__i(sdram_dq_i[8]),
5971         .sdr_dq_9__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[9]),
5972         .sdr_dq_9__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[9]),
5973         .sdr_dq_9__pad__i(sdram_dq_i[9]),
5974         .sdr_ras_n__core__o(libresocsim_libresoc_constraintmanager_sdram_ras_n),
5975         .sdr_we_n__core__o(libresocsim_libresoc_constraintmanager_sdram_we_n),
5976         .sram4k_0_wb__adr(libresocsim_libresoc_interface0_adr),
5977         .sram4k_0_wb__cyc(libresocsim_libresoc_interface0_cyc),
5978         .sram4k_0_wb__dat_w(libresocsim_libresoc_interface0_dat_w),
5979         .sram4k_0_wb__sel(libresocsim_libresoc_interface0_sel),
5980         .sram4k_0_wb__stb(libresocsim_libresoc_interface0_stb),
5981         .sram4k_0_wb__we(libresocsim_libresoc_interface0_we),
5982         .sram4k_1_wb__adr(libresocsim_libresoc_interface1_adr),
5983         .sram4k_1_wb__cyc(libresocsim_libresoc_interface1_cyc),
5984         .sram4k_1_wb__dat_w(libresocsim_libresoc_interface1_dat_w),
5985         .sram4k_1_wb__sel(libresocsim_libresoc_interface1_sel),
5986         .sram4k_1_wb__stb(libresocsim_libresoc_interface1_stb),
5987         .sram4k_1_wb__we(libresocsim_libresoc_interface1_we),
5988         .sram4k_2_wb__adr(libresocsim_libresoc_interface2_adr),
5989         .sram4k_2_wb__cyc(libresocsim_libresoc_interface2_cyc),
5990         .sram4k_2_wb__dat_w(libresocsim_libresoc_interface2_dat_w),
5991         .sram4k_2_wb__sel(libresocsim_libresoc_interface2_sel),
5992         .sram4k_2_wb__stb(libresocsim_libresoc_interface2_stb),
5993         .sram4k_2_wb__we(libresocsim_libresoc_interface2_we),
5994         .sram4k_3_wb__adr(libresocsim_libresoc_interface3_adr),
5995         .sram4k_3_wb__cyc(libresocsim_libresoc_interface3_cyc),
5996         .sram4k_3_wb__dat_w(libresocsim_libresoc_interface3_dat_w),
5997         .sram4k_3_wb__sel(libresocsim_libresoc_interface3_sel),
5998         .sram4k_3_wb__stb(libresocsim_libresoc_interface3_stb),
5999         .sram4k_3_wb__we(libresocsim_libresoc_interface3_we),
6000         .TAP_bus__tdo(libresocsim_libresoc_jtag_tdo),
6001         .busy_o(libresocsim_libresoc1),
6002         .dbus__adr(libresocsim_libresoc_dbus_adr),
6003         .dbus__cyc(libresocsim_libresoc_dbus_cyc),
6004         .dbus__dat_w(libresocsim_libresoc_dbus_dat_w),
6005         .dbus__sel(libresocsim_libresoc_dbus_sel),
6006         .dbus__stb(libresocsim_libresoc_dbus_stb),
6007         .dbus__we(libresocsim_libresoc_dbus_we),
6008         .eint_0__core__i(libresocsim_libresoc_constraintmanager_eint_0),
6009         .eint_1__core__i(libresocsim_libresoc_constraintmanager_eint_1),
6010         .eint_2__core__i(libresocsim_libresoc_constraintmanager_eint_2),
6011         .gpio_e10__core__i(libresocsim_libresoc_constraintmanager_gpio_i[10]),
6012         .gpio_e10__pad__o(gpio_o[10]),
6013         .gpio_e10__pad__oe(gpio_oe[10]),
6014         .gpio_e11__core__i(libresocsim_libresoc_constraintmanager_gpio_i[11]),
6015         .gpio_e11__pad__o(gpio_o[11]),
6016         .gpio_e11__pad__oe(gpio_oe[11]),
6017         .gpio_e12__core__i(libresocsim_libresoc_constraintmanager_gpio_i[12]),
6018         .gpio_e12__pad__o(gpio_o[12]),
6019         .gpio_e12__pad__oe(gpio_oe[12]),
6020         .gpio_e13__core__i(libresocsim_libresoc_constraintmanager_gpio_i[13]),
6021         .gpio_e13__pad__o(gpio_o[13]),
6022         .gpio_e13__pad__oe(gpio_oe[13]),
6023         .gpio_e14__core__i(libresocsim_libresoc_constraintmanager_gpio_i[14]),
6024         .gpio_e14__pad__o(gpio_o[14]),
6025         .gpio_e14__pad__oe(gpio_oe[14]),
6026         .gpio_e15__core__i(libresocsim_libresoc_constraintmanager_gpio_i[15]),
6027         .gpio_e15__pad__o(gpio_o[15]),
6028         .gpio_e15__pad__oe(gpio_oe[15]),
6029         .gpio_e8__core__i(libresocsim_libresoc_constraintmanager_gpio_i[8]),
6030         .gpio_e8__pad__o(gpio_o[8]),
6031         .gpio_e8__pad__oe(gpio_oe[8]),
6032         .gpio_e9__core__i(libresocsim_libresoc_constraintmanager_gpio_i[9]),
6033         .gpio_e9__pad__o(gpio_o[9]),
6034         .gpio_e9__pad__oe(gpio_oe[9]),
6035         .gpio_s0__core__i(libresocsim_libresoc_constraintmanager_gpio_i[0]),
6036         .gpio_s0__pad__o(gpio_o[0]),
6037         .gpio_s0__pad__oe(gpio_oe[0]),
6038         .gpio_s1__core__i(libresocsim_libresoc_constraintmanager_gpio_i[1]),
6039         .gpio_s1__pad__o(gpio_o[1]),
6040         .gpio_s1__pad__oe(gpio_oe[1]),
6041         .gpio_s2__core__i(libresocsim_libresoc_constraintmanager_gpio_i[2]),
6042         .gpio_s2__pad__o(gpio_o[2]),
6043         .gpio_s2__pad__oe(gpio_oe[2]),
6044         .gpio_s3__core__i(libresocsim_libresoc_constraintmanager_gpio_i[3]),
6045         .gpio_s3__pad__o(gpio_o[3]),
6046         .gpio_s3__pad__oe(gpio_oe[3]),
6047         .gpio_s4__core__i(libresocsim_libresoc_constraintmanager_gpio_i[4]),
6048         .gpio_s4__pad__o(gpio_o[4]),
6049         .gpio_s4__pad__oe(gpio_oe[4]),
6050         .gpio_s5__core__i(libresocsim_libresoc_constraintmanager_gpio_i[5]),
6051         .gpio_s5__pad__o(gpio_o[5]),
6052         .gpio_s5__pad__oe(gpio_oe[5]),
6053         .gpio_s6__core__i(libresocsim_libresoc_constraintmanager_gpio_i[6]),
6054         .gpio_s6__pad__o(gpio_o[6]),
6055         .gpio_s6__pad__oe(gpio_oe[6]),
6056         .gpio_s7__core__i(libresocsim_libresoc_constraintmanager_gpio_i[7]),
6057         .gpio_s7__pad__o(gpio_o[7]),
6058         .gpio_s7__pad__oe(gpio_oe[7]),
6059         .ibus__adr(libresocsim_libresoc_ibus_adr),
6060         .ibus__cyc(libresocsim_libresoc_ibus_cyc),
6061         .ibus__dat_w(libresocsim_libresoc_ibus_dat_w),
6062         .ibus__sel(libresocsim_libresoc_ibus_sel),
6063         .ibus__stb(libresocsim_libresoc_ibus_stb),
6064         .ibus__we(libresocsim_libresoc_ibus_we),
6065         .icp_wb__ack(libresocsim_libresoc_xics_icp_ack),
6066         .icp_wb__dat_r(libresocsim_libresoc_xics_icp_dat_r),
6067         .icp_wb__err(libresocsim_libresoc_xics_icp_err),
6068         .ics_wb__ack(libresocsim_libresoc_xics_ics_ack),
6069         .ics_wb__dat_r(libresocsim_libresoc_xics_ics_dat_r),
6070         .ics_wb__err(libresocsim_libresoc_xics_ics_err),
6071         .jtag_wb__adr(libresocsim_libresoc_jtag_wb_adr),
6072         .jtag_wb__cyc(libresocsim_libresoc_jtag_wb_cyc),
6073         .jtag_wb__dat_w(libresocsim_libresoc_jtag_wb_dat_w),
6074         .jtag_wb__sel(libresocsim_libresoc_jtag_wb_sel),
6075         .jtag_wb__stb(libresocsim_libresoc_jtag_wb_stb),
6076         .jtag_wb__we(libresocsim_libresoc_jtag_wb_we),
6077         .memerr_o(libresocsim_libresoc2),
6078         .mspi0_clk__pad__o(spimaster_clk),
6079         .mspi0_cs_n__pad__o(spimaster_cs_n),
6080         .mspi0_miso__core__i(libresocsim_libresoc_constraintmanager_spimaster_miso),
6081         .mspi0_mosi__pad__o(spimaster_mosi),
6082         .mtwi_scl__pad__o(i2c_scl),
6083         .mtwi_sda__core__i(libresocsim_libresoc_constraintmanager_i2c_sda_i),
6084         .mtwi_sda__pad__o(i2c_sda_o),
6085         .mtwi_sda__pad__oe(i2c_sda_oe),
6086         .pc_o(libresocsim_libresoc3),
6087         .pll_18_o(libresocsim_libresoc_pll_18_o),
6088         .sdr_a_0__pad__o(sdram_a[0]),
6089         .sdr_a_10__pad__o(sdram_a[10]),
6090         .sdr_a_11__pad__o(sdram_a[11]),
6091         .sdr_a_12__pad__o(sdram_a[12]),
6092         .sdr_a_1__pad__o(sdram_a[1]),
6093         .sdr_a_2__pad__o(sdram_a[2]),
6094         .sdr_a_3__pad__o(sdram_a[3]),
6095         .sdr_a_4__pad__o(sdram_a[4]),
6096         .sdr_a_5__pad__o(sdram_a[5]),
6097         .sdr_a_6__pad__o(sdram_a[6]),
6098         .sdr_a_7__pad__o(sdram_a[7]),
6099         .sdr_a_8__pad__o(sdram_a[8]),
6100         .sdr_a_9__pad__o(sdram_a[9]),
6101         .sdr_ba_0__pad__o(sdram_ba[0]),
6102         .sdr_ba_1__pad__o(sdram_ba[1]),
6103         .sdr_cas_n__pad__o(sdram_cas_n),
6104         .sdr_cke__pad__o(sdram_cke),
6105         .sdr_clock__pad__o(sdram_clock),
6106         .sdr_cs_n__pad__o(sdram_cs_n),
6107         .sdr_dm_0__pad__o(sdram_dm[0]),
6108         .sdr_dm_1__pad__o(sdram_dm[1]),
6109         .sdr_dq_0__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[0]),
6110         .sdr_dq_0__pad__o(sdram_dq_o[0]),
6111         .sdr_dq_0__pad__oe(sdram_dq_oe[0]),
6112         .sdr_dq_10__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[10]),
6113         .sdr_dq_10__pad__o(sdram_dq_o[10]),
6114         .sdr_dq_10__pad__oe(sdram_dq_oe[10]),
6115         .sdr_dq_11__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[11]),
6116         .sdr_dq_11__pad__o(sdram_dq_o[11]),
6117         .sdr_dq_11__pad__oe(sdram_dq_oe[11]),
6118         .sdr_dq_12__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[12]),
6119         .sdr_dq_12__pad__o(sdram_dq_o[12]),
6120         .sdr_dq_12__pad__oe(sdram_dq_oe[12]),
6121         .sdr_dq_13__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[13]),
6122         .sdr_dq_13__pad__o(sdram_dq_o[13]),
6123         .sdr_dq_13__pad__oe(sdram_dq_oe[13]),
6124         .sdr_dq_14__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[14]),
6125         .sdr_dq_14__pad__o(sdram_dq_o[14]),
6126         .sdr_dq_14__pad__oe(sdram_dq_oe[14]),
6127         .sdr_dq_15__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[15]),
6128         .sdr_dq_15__pad__o(sdram_dq_o[15]),
6129         .sdr_dq_15__pad__oe(sdram_dq_oe[15]),
6130         .sdr_dq_1__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[1]),
6131         .sdr_dq_1__pad__o(sdram_dq_o[1]),
6132         .sdr_dq_1__pad__oe(sdram_dq_oe[1]),
6133         .sdr_dq_2__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[2]),
6134         .sdr_dq_2__pad__o(sdram_dq_o[2]),
6135         .sdr_dq_2__pad__oe(sdram_dq_oe[2]),
6136         .sdr_dq_3__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[3]),
6137         .sdr_dq_3__pad__o(sdram_dq_o[3]),
6138         .sdr_dq_3__pad__oe(sdram_dq_oe[3]),
6139         .sdr_dq_4__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[4]),
6140         .sdr_dq_4__pad__o(sdram_dq_o[4]),
6141         .sdr_dq_4__pad__oe(sdram_dq_oe[4]),
6142         .sdr_dq_5__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[5]),
6143         .sdr_dq_5__pad__o(sdram_dq_o[5]),
6144         .sdr_dq_5__pad__oe(sdram_dq_oe[5]),
6145         .sdr_dq_6__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[6]),
6146         .sdr_dq_6__pad__o(sdram_dq_o[6]),
6147         .sdr_dq_6__pad__oe(sdram_dq_oe[6]),
6148         .sdr_dq_7__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[7]),
6149         .sdr_dq_7__pad__o(sdram_dq_o[7]),
6150         .sdr_dq_7__pad__oe(sdram_dq_oe[7]),
6151         .sdr_dq_8__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[8]),
6152         .sdr_dq_8__pad__o(sdram_dq_o[8]),
6153         .sdr_dq_8__pad__oe(sdram_dq_oe[8]),
6154         .sdr_dq_9__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[9]),
6155         .sdr_dq_9__pad__o(sdram_dq_o[9]),
6156         .sdr_dq_9__pad__oe(sdram_dq_oe[9]),
6157         .sdr_ras_n__pad__o(sdram_ras_n),
6158         .sdr_we_n__pad__o(sdram_we_n),
6159         .sram4k_0_wb__ack(libresocsim_libresoc_interface0_ack),
6160         .sram4k_0_wb__dat_r(libresocsim_libresoc_interface0_dat_r),
6161         .sram4k_0_wb__err(libresocsim_libresoc_interface0_err),
6162         .sram4k_1_wb__ack(libresocsim_libresoc_interface1_ack),
6163         .sram4k_1_wb__dat_r(libresocsim_libresoc_interface1_dat_r),
6164         .sram4k_1_wb__err(libresocsim_libresoc_interface1_err),
6165         .sram4k_2_wb__ack(libresocsim_libresoc_interface2_ack),
6166         .sram4k_2_wb__dat_r(libresocsim_libresoc_interface2_dat_r),
6167         .sram4k_2_wb__err(libresocsim_libresoc_interface2_err),
6168         .sram4k_3_wb__ack(libresocsim_libresoc_interface3_ack),
6169         .sram4k_3_wb__dat_r(libresocsim_libresoc_interface3_dat_r),
6170         .sram4k_3_wb__err(libresocsim_libresoc_interface3_err),
6171         .vco_test_ana(libresocsim_libresoc_pll_ana_o)
6172 );
6173
6174 endmodule