experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v

   1 //--------------------------------------------------------------------------------
   2 // Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-26 15:05:51
   3 //--------------------------------------------------------------------------------
   4 module ls180(
   5         output wire spimaster_clk,
   6         output wire spimaster_mosi,
   7         output wire spimaster_cs_n,
   8         input wire spimaster_miso,
   9         input wire [15:0] gpio_i,
  10         output wire [15:0] gpio_o,
  11         output wire [15:0] gpio_oe,
  12         input wire uart_tx,
  13         input wire uart_rx,
  14         input wire eint_0,
  15         input wire eint_1,
  16         input wire eint_2,
  17         output wire [12:0] sdram_a,
  18         input wire [15:0] sdram_dq_i,
  19         output wire [15:0] sdram_dq_o,
  20         output wire [15:0] sdram_dq_oe,
  21         output wire sdram_we_n,
  22         output wire sdram_ras_n,
  23         output wire sdram_cas_n,
  24         output wire sdram_cs_n,
  25         output wire sdram_cke,
  26         output wire [1:0] sdram_ba,
  27         output wire [1:0] sdram_dm,
  28         output wire sdram_clock,
  29         output wire i2c_scl,
  30         input wire i2c_sda_i,
  31         output wire i2c_sda_o,
  32         output wire i2c_sda_oe,
  33         input wire sys_clk,
  34         input wire sys_rst,
  35         input wire [1:0] sys_clksel_i,
  36         output wire sys_pll_testout_o,
  37         output wire sys_pll_vco_o,
  38         input wire jtag_tms,
  39         input wire jtag_tck,
  40         input wire jtag_tdi,
  41         output wire jtag_tdo,
  42         input wire [35:0] nc
  43 );
  44
  45 wire sys_clk_0;
  46 (* ram_style = "distributed" *) reg libresocsim_reset_storage = 1'd0;
  47 reg libresocsim_reset_re = 1'd0;
  48 (* ram_style = "distributed" *) reg [31:0] libresocsim_scratch_storage = 32'd305419896;
  49 reg libresocsim_scratch_re = 1'd0;
  50 wire [31:0] libresocsim_bus_errors_status;
  51 wire libresocsim_bus_errors_we;
  52 wire libresocsim_reset;
  53 wire libresocsim_bus_error;
  54 reg [31:0] libresocsim_bus_errors = 32'd0;
  55 wire libresocsim_libresoc_reset;
  56 reg [15:0] libresocsim_libresoc_interrupt = 16'd0;
  57 wire [28:0] libresocsim_libresoc_dbus_adr;
  58 wire [63:0] libresocsim_libresoc_dbus_dat_w;
  59 wire [63:0] libresocsim_libresoc_dbus_dat_r;
  60 wire [7:0] libresocsim_libresoc_dbus_sel;
  61 wire libresocsim_libresoc_dbus_cyc;
  62 wire libresocsim_libresoc_dbus_stb;
  63 reg libresocsim_libresoc_dbus_ack = 1'd0;
  64 wire libresocsim_libresoc_dbus_we;
  65 reg libresocsim_libresoc_dbus_err = 1'd0;
  66 wire [28:0] libresocsim_libresoc_ibus_adr;
  67 wire [63:0] libresocsim_libresoc_ibus_dat_w;
  68 wire [63:0] libresocsim_libresoc_ibus_dat_r;
  69 wire [7:0] libresocsim_libresoc_ibus_sel;
  70 wire libresocsim_libresoc_ibus_cyc;
  71 wire libresocsim_libresoc_ibus_stb;
  72 reg libresocsim_libresoc_ibus_ack = 1'd0;
  73 wire libresocsim_libresoc_ibus_we;
  74 reg libresocsim_libresoc_ibus_err = 1'd0;
  75 wire [29:0] libresocsim_libresoc_xics_icp_adr;
  76 wire [31:0] libresocsim_libresoc_xics_icp_dat_w;
  77 wire [31:0] libresocsim_libresoc_xics_icp_dat_r;
  78 wire [3:0] libresocsim_libresoc_xics_icp_sel;
  79 wire libresocsim_libresoc_xics_icp_cyc;
  80 wire libresocsim_libresoc_xics_icp_stb;
  81 wire libresocsim_libresoc_xics_icp_ack;
  82 wire libresocsim_libresoc_xics_icp_we;
  83 wire [2:0] libresocsim_libresoc_xics_icp_cti;
  84 wire [1:0] libresocsim_libresoc_xics_icp_bte;
  85 wire libresocsim_libresoc_xics_icp_err;
  86 wire [29:0] libresocsim_libresoc_xics_ics_adr;
  87 wire [31:0] libresocsim_libresoc_xics_ics_dat_w;
  88 wire [31:0] libresocsim_libresoc_xics_ics_dat_r;
  89 wire [3:0] libresocsim_libresoc_xics_ics_sel;
  90 wire libresocsim_libresoc_xics_ics_cyc;
  91 wire libresocsim_libresoc_xics_ics_stb;
  92 wire libresocsim_libresoc_xics_ics_ack;
  93 wire libresocsim_libresoc_xics_ics_we;
  94 wire [2:0] libresocsim_libresoc_xics_ics_cti;
  95 wire [1:0] libresocsim_libresoc_xics_ics_bte;
  96 wire libresocsim_libresoc_xics_ics_err;
  97 wire [29:0] libresocsim_libresoc_jtag_wb_adr;
  98 wire [31:0] libresocsim_libresoc_jtag_wb_dat_w;
  99 wire [31:0] libresocsim_libresoc_jtag_wb_dat_r;
 100 wire [3:0] libresocsim_libresoc_jtag_wb_sel;
 101 wire libresocsim_libresoc_jtag_wb_cyc;
 102 wire libresocsim_libresoc_jtag_wb_stb;
 103 wire libresocsim_libresoc_jtag_wb_ack;
 104 wire libresocsim_libresoc_jtag_wb_we;
 105 reg [2:0] libresocsim_libresoc_jtag_wb_cti = 3'd0;
 106 reg [1:0] libresocsim_libresoc_jtag_wb_bte = 2'd0;
 107 wire libresocsim_libresoc_jtag_wb_err;
 108 reg [28:0] libresocsim_libresoc_interface0_adr = 29'd0;
 109 reg [63:0] libresocsim_libresoc_interface0_dat_w = 64'd0;
 110 wire [63:0] libresocsim_libresoc_interface0_dat_r;
 111 reg [7:0] libresocsim_libresoc_interface0_sel = 8'd0;
 112 wire libresocsim_libresoc_interface0_cyc;
 113 wire libresocsim_libresoc_interface0_stb;
 114 wire libresocsim_libresoc_interface0_ack;
 115 wire libresocsim_libresoc_interface0_we;
 116 wire [2:0] libresocsim_libresoc_interface0_cti;
 117 wire [1:0] libresocsim_libresoc_interface0_bte;
 118 reg libresocsim_libresoc_interface0_err = 1'd0;
 119 reg [28:0] libresocsim_libresoc_interface1_adr = 29'd0;
 120 reg [63:0] libresocsim_libresoc_interface1_dat_w = 64'd0;
 121 wire [63:0] libresocsim_libresoc_interface1_dat_r;
 122 reg [7:0] libresocsim_libresoc_interface1_sel = 8'd0;
 123 wire libresocsim_libresoc_interface1_cyc;
 124 wire libresocsim_libresoc_interface1_stb;
 125 wire libresocsim_libresoc_interface1_ack;
 126 wire libresocsim_libresoc_interface1_we;
 127 wire [2:0] libresocsim_libresoc_interface1_cti;
 128 wire [1:0] libresocsim_libresoc_interface1_bte;
 129 reg libresocsim_libresoc_interface1_err = 1'd0;
 130 reg [28:0] libresocsim_libresoc_interface2_adr = 29'd0;
 131 reg [63:0] libresocsim_libresoc_interface2_dat_w = 64'd0;
 132 wire [63:0] libresocsim_libresoc_interface2_dat_r;
 133 reg [7:0] libresocsim_libresoc_interface2_sel = 8'd0;
 134 wire libresocsim_libresoc_interface2_cyc;
 135 wire libresocsim_libresoc_interface2_stb;
 136 wire libresocsim_libresoc_interface2_ack;
 137 wire libresocsim_libresoc_interface2_we;
 138 wire [2:0] libresocsim_libresoc_interface2_cti;
 139 wire [1:0] libresocsim_libresoc_interface2_bte;
 140 reg libresocsim_libresoc_interface2_err = 1'd0;
 141 reg [28:0] libresocsim_libresoc_interface3_adr = 29'd0;
 142 reg [63:0] libresocsim_libresoc_interface3_dat_w = 64'd0;
 143 wire [63:0] libresocsim_libresoc_interface3_dat_r;
 144 reg [7:0] libresocsim_libresoc_interface3_sel = 8'd0;
 145 wire libresocsim_libresoc_interface3_cyc;
 146 wire libresocsim_libresoc_interface3_stb;
 147 wire libresocsim_libresoc_interface3_ack;
 148 wire libresocsim_libresoc_interface3_we;
 149 wire [2:0] libresocsim_libresoc_interface3_cti;
 150 wire [1:0] libresocsim_libresoc_interface3_bte;
 151 reg libresocsim_libresoc_interface3_err = 1'd0;
 152 wire libresocsim_libresoc_jtag_tck;
 153 wire libresocsim_libresoc_jtag_tms;
 154 wire libresocsim_libresoc_jtag_tdi;
 155 wire libresocsim_libresoc_jtag_tdo;
 156 reg [63:0] libresocsim_libresoc0 = 64'd0;
 157 wire libresocsim_libresoc1;
 158 wire libresocsim_libresoc2;
 159 wire [63:0] libresocsim_libresoc3;
 160 wire libresocsim_libresoc_pll_vco_o;
 161 wire [1:0] libresocsim_libresoc_clk_sel;
 162 wire libresocsim_libresoc_pll_test_o;
 163 reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0;
 164 reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0;
 165 reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0;
 166 wire libresocsim_libresoc_constraintmanager_spimaster_miso;
 167 wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i;
 168 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0;
 169 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0;
 170 reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1;
 171 reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0;
 172 wire libresocsim_libresoc_constraintmanager_eint_0;
 173 wire libresocsim_libresoc_constraintmanager_eint_1;
 174 wire libresocsim_libresoc_constraintmanager_eint_2;
 175 reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0;
 176 wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i;
 177 reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0;
 178 reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_oe = 16'd0;
 179 reg libresocsim_libresoc_constraintmanager_sdram_we_n = 1'd0;
 180 reg libresocsim_libresoc_constraintmanager_sdram_ras_n = 1'd0;
 181 reg libresocsim_libresoc_constraintmanager_sdram_cas_n = 1'd0;
 182 reg libresocsim_libresoc_constraintmanager_sdram_cs_n = 1'd0;
 183 reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0;
 184 reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0;
 185 reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0;
 186 reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0;
 187 wire libresocsim_libresoc_constraintmanager_i2c_scl;
 188 wire libresocsim_libresoc_constraintmanager_i2c_sda_i;
 189 wire libresocsim_libresoc_constraintmanager_i2c_sda_o;
 190 wire libresocsim_libresoc_constraintmanager_i2c_sda_oe;
 191 reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0;
 192 reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0;
 193 wire [31:0] libresocsim_interface0_converted_interface_dat_r;
 194 reg [3:0] libresocsim_interface0_converted_interface_sel = 4'd0;
 195 reg libresocsim_interface0_converted_interface_cyc = 1'd0;
 196 reg libresocsim_interface0_converted_interface_stb = 1'd0;
 197 wire libresocsim_interface0_converted_interface_ack;
 198 reg libresocsim_interface0_converted_interface_we = 1'd0;
 199 reg [2:0] libresocsim_interface0_converted_interface_cti = 3'd0;
 200 reg [1:0] libresocsim_interface0_converted_interface_bte = 2'd0;
 201 wire libresocsim_interface0_converted_interface_err;
 202 reg libresocsim_converter0_skip = 1'd0;
 203 reg libresocsim_converter0_counter = 1'd0;
 204 wire libresocsim_converter0_reset;
 205 reg [63:0] libresocsim_converter0_dat_r = 64'd0;
 206 reg [29:0] libresocsim_interface1_converted_interface_adr = 30'd0;
 207 reg [31:0] libresocsim_interface1_converted_interface_dat_w = 32'd0;
 208 wire [31:0] libresocsim_interface1_converted_interface_dat_r;
 209 reg [3:0] libresocsim_interface1_converted_interface_sel = 4'd0;
 210 reg libresocsim_interface1_converted_interface_cyc = 1'd0;
 211 reg libresocsim_interface1_converted_interface_stb = 1'd0;
 212 wire libresocsim_interface1_converted_interface_ack;
 213 reg libresocsim_interface1_converted_interface_we = 1'd0;
 214 reg [2:0] libresocsim_interface1_converted_interface_cti = 3'd0;
 215 reg [1:0] libresocsim_interface1_converted_interface_bte = 2'd0;
 216 wire libresocsim_interface1_converted_interface_err;
 217 reg libresocsim_converter1_skip = 1'd0;
 218 reg libresocsim_converter1_counter = 1'd0;
 219 wire libresocsim_converter1_reset;
 220 reg [63:0] libresocsim_converter1_dat_r = 64'd0;
 221 wire [29:0] libresocsim_ram_bus_adr;
 222 wire [31:0] libresocsim_ram_bus_dat_w;
 223 wire [31:0] libresocsim_ram_bus_dat_r;
 224 wire [3:0] libresocsim_ram_bus_sel;
 225 wire libresocsim_ram_bus_cyc;
 226 wire libresocsim_ram_bus_stb;
 227 reg libresocsim_ram_bus_ack = 1'd0;
 228 wire libresocsim_ram_bus_we;
 229 wire [2:0] libresocsim_ram_bus_cti;
 230 wire [1:0] libresocsim_ram_bus_bte;
 231 reg libresocsim_ram_bus_err = 1'd0;
 232 wire [4:0] libresocsim_adr;
 233 wire [31:0] libresocsim_dat_r;
 234 reg [3:0] libresocsim_we = 4'd0;
 235 wire [31:0] libresocsim_dat_w;
 236 (* ram_style = "distributed" *) reg [31:0] libresocsim_load_storage = 32'd0;
 237 reg libresocsim_load_re = 1'd0;
 238 (* ram_style = "distributed" *) reg [31:0] libresocsim_reload_storage = 32'd0;
 239 reg libresocsim_reload_re = 1'd0;
 240 (* ram_style = "distributed" *) reg libresocsim_en_storage = 1'd0;
 241 reg libresocsim_en_re = 1'd0;
 242 (* ram_style = "distributed" *) reg libresocsim_update_value_storage = 1'd0;
 243 reg libresocsim_update_value_re = 1'd0;
 244 reg [31:0] libresocsim_value_status = 32'd0;
 245 wire libresocsim_value_we;
 246 wire libresocsim_irq;
 247 wire libresocsim_zero_status;
 248 reg libresocsim_zero_pending = 1'd0;
 249 wire libresocsim_zero_trigger;
 250 reg libresocsim_zero_clear = 1'd0;
 251 reg libresocsim_zero_old_trigger = 1'd0;
 252 wire libresocsim_eventmanager_status_re;
 253 wire libresocsim_eventmanager_status_r;
 254 wire libresocsim_eventmanager_status_we;
 255 wire libresocsim_eventmanager_status_w;
 256 wire libresocsim_eventmanager_pending_re;
 257 wire libresocsim_eventmanager_pending_r;
 258 wire libresocsim_eventmanager_pending_we;
 259 wire libresocsim_eventmanager_pending_w;
 260 (* ram_style = "distributed" *) reg libresocsim_eventmanager_storage = 1'd0;
 261 reg libresocsim_eventmanager_re = 1'd0;
 262 reg [31:0] libresocsim_value = 32'd0;
 263 wire [29:0] ram_bus_ram_bus_adr;
 264 wire [31:0] ram_bus_ram_bus_dat_w;
 265 wire [31:0] ram_bus_ram_bus_dat_r;
 266 wire [3:0] ram_bus_ram_bus_sel;
 267 wire ram_bus_ram_bus_cyc;
 268 wire ram_bus_ram_bus_stb;
 269 reg ram_bus_ram_bus_ack = 1'd0;
 270 wire ram_bus_ram_bus_we;
 271 wire [2:0] ram_bus_ram_bus_cti;
 272 wire [1:0] ram_bus_ram_bus_bte;
 273 reg ram_bus_ram_bus_err = 1'd0;
 274 wire [4:0] ram_adr;
 275 wire [31:0] ram_dat_r;
 276 reg [3:0] ram_we = 4'd0;
 277 wire [31:0] ram_dat_w;
 278 wire [29:0] interface0_converted_interface_adr;
 279 wire [31:0] interface0_converted_interface_dat_w;
 280 reg [31:0] interface0_converted_interface_dat_r = 32'd0;
 281 wire [3:0] interface0_converted_interface_sel;
 282 wire interface0_converted_interface_cyc;
 283 wire interface0_converted_interface_stb;
 284 wire interface0_converted_interface_ack;
 285 wire interface0_converted_interface_we;
 286 wire [2:0] interface0_converted_interface_cti;
 287 wire [1:0] interface0_converted_interface_bte;
 288 wire interface0_converted_interface_err;
 289 wire [29:0] interface1_converted_interface_adr;
 290 wire [31:0] interface1_converted_interface_dat_w;
 291 reg [31:0] interface1_converted_interface_dat_r = 32'd0;
 292 wire [3:0] interface1_converted_interface_sel;
 293 wire interface1_converted_interface_cyc;
 294 wire interface1_converted_interface_stb;
 295 wire interface1_converted_interface_ack;
 296 wire interface1_converted_interface_we;
 297 wire [2:0] interface1_converted_interface_cti;
 298 wire [1:0] interface1_converted_interface_bte;
 299 wire interface1_converted_interface_err;
 300 wire [29:0] interface2_converted_interface_adr;
 301 wire [31:0] interface2_converted_interface_dat_w;
 302 reg [31:0] interface2_converted_interface_dat_r = 32'd0;
 303 wire [3:0] interface2_converted_interface_sel;
 304 wire interface2_converted_interface_cyc;
 305 wire interface2_converted_interface_stb;
 306 wire interface2_converted_interface_ack;
 307 wire interface2_converted_interface_we;
 308 wire [2:0] interface2_converted_interface_cti;
 309 wire [1:0] interface2_converted_interface_bte;
 310 wire interface2_converted_interface_err;
 311 wire [29:0] interface3_converted_interface_adr;
 312 wire [31:0] interface3_converted_interface_dat_w;
 313 reg [31:0] interface3_converted_interface_dat_r = 32'd0;
 314 wire [3:0] interface3_converted_interface_sel;
 315 wire interface3_converted_interface_cyc;
 316 wire interface3_converted_interface_stb;
 317 wire interface3_converted_interface_ack;
 318 wire interface3_converted_interface_we;
 319 wire [2:0] interface3_converted_interface_cti;
 320 wire [1:0] interface3_converted_interface_bte;
 321 wire interface3_converted_interface_err;
 322 wire sys_clk_1;
 323 wire sys_rst_1;
 324 wire por_clk;
 325 reg int_rst = 1'd1;
 326 wire [12:0] dfi_p0_address;
 327 wire [1:0] dfi_p0_bank;
 328 wire dfi_p0_cas_n;
 329 wire dfi_p0_cs_n;
 330 wire dfi_p0_ras_n;
 331 wire dfi_p0_we_n;
 332 wire dfi_p0_cke;
 333 wire dfi_p0_odt;
 334 wire dfi_p0_reset_n;
 335 wire dfi_p0_act_n;
 336 wire [15:0] dfi_p0_wrdata;
 337 wire dfi_p0_wrdata_en;
 338 wire [1:0] dfi_p0_wrdata_mask;
 339 wire dfi_p0_rddata_en;
 340 reg [15:0] dfi_p0_rddata = 16'd0;
 341 reg dfi_p0_rddata_valid = 1'd0;
 342 reg [2:0] rddata_en = 3'd0;
 343 wire [12:0] sdram_inti_p0_address;
 344 wire [1:0] sdram_inti_p0_bank;
 345 reg sdram_inti_p0_cas_n = 1'd1;
 346 reg sdram_inti_p0_cs_n = 1'd1;
 347 reg sdram_inti_p0_ras_n = 1'd1;
 348 reg sdram_inti_p0_we_n = 1'd1;
 349 wire sdram_inti_p0_cke;
 350 wire sdram_inti_p0_odt;
 351 wire sdram_inti_p0_reset_n;
 352 reg sdram_inti_p0_act_n = 1'd1;
 353 wire [15:0] sdram_inti_p0_wrdata;
 354 wire sdram_inti_p0_wrdata_en;
 355 wire [1:0] sdram_inti_p0_wrdata_mask;
 356 wire sdram_inti_p0_rddata_en;
 357 reg [15:0] sdram_inti_p0_rddata = 16'd0;
 358 reg sdram_inti_p0_rddata_valid = 1'd0;
 359 wire [12:0] sdram_slave_p0_address;
 360 wire [1:0] sdram_slave_p0_bank;
 361 wire sdram_slave_p0_cas_n;
 362 wire sdram_slave_p0_cs_n;
 363 wire sdram_slave_p0_ras_n;
 364 wire sdram_slave_p0_we_n;
 365 wire sdram_slave_p0_cke;
 366 wire sdram_slave_p0_odt;
 367 wire sdram_slave_p0_reset_n;
 368 wire sdram_slave_p0_act_n;
 369 wire [15:0] sdram_slave_p0_wrdata;
 370 wire sdram_slave_p0_wrdata_en;
 371 wire [1:0] sdram_slave_p0_wrdata_mask;
 372 wire sdram_slave_p0_rddata_en;
 373 reg [15:0] sdram_slave_p0_rddata = 16'd0;
 374 reg sdram_slave_p0_rddata_valid = 1'd0;
 375 reg [12:0] sdram_master_p0_address = 13'd0;
 376 reg [1:0] sdram_master_p0_bank = 2'd0;
 377 reg sdram_master_p0_cas_n = 1'd1;
 378 reg sdram_master_p0_cs_n = 1'd1;
 379 reg sdram_master_p0_ras_n = 1'd1;
 380 reg sdram_master_p0_we_n = 1'd1;
 381 reg sdram_master_p0_cke = 1'd0;
 382 reg sdram_master_p0_odt = 1'd0;
 383 reg sdram_master_p0_reset_n = 1'd0;
 384 reg sdram_master_p0_act_n = 1'd1;
 385 reg [15:0] sdram_master_p0_wrdata = 16'd0;
 386 reg sdram_master_p0_wrdata_en = 1'd0;
 387 reg [1:0] sdram_master_p0_wrdata_mask = 2'd0;
 388 reg sdram_master_p0_rddata_en = 1'd0;
 389 wire [15:0] sdram_master_p0_rddata;
 390 wire sdram_master_p0_rddata_valid;
 391 wire sdram_sel;
 392 wire sdram_cke_1;
 393 wire sdram_odt;
 394 wire sdram_reset_n;
 395 (* ram_style = "distributed" *) reg [3:0] sdram_storage = 4'd1;
 396 reg sdram_re = 1'd0;
 397 (* ram_style = "distributed" *) reg [5:0] sdram_command_storage = 6'd0;
 398 reg sdram_command_re = 1'd0;
 399 wire sdram_command_issue_re;
 400 wire sdram_command_issue_r;
 401 wire sdram_command_issue_we;
 402 reg sdram_command_issue_w = 1'd0;
 403 (* ram_style = "distributed" *) reg [12:0] sdram_address_storage = 13'd0;
 404 reg sdram_address_re = 1'd0;
 405 (* ram_style = "distributed" *) reg [1:0] sdram_baddress_storage = 2'd0;
 406 reg sdram_baddress_re = 1'd0;
 407 (* ram_style = "distributed" *) reg [15:0] sdram_wrdata_storage = 16'd0;
 408 reg sdram_wrdata_re = 1'd0;
 409 reg [15:0] sdram_status = 16'd0;
 410 wire sdram_we;
 411 wire sdram_interface_bank0_valid;
 412 wire sdram_interface_bank0_ready;
 413 wire sdram_interface_bank0_we;
 414 wire [21:0] sdram_interface_bank0_addr;
 415 wire sdram_interface_bank0_lock;
 416 wire sdram_interface_bank0_wdata_ready;
 417 wire sdram_interface_bank0_rdata_valid;
 418 wire sdram_interface_bank1_valid;
 419 wire sdram_interface_bank1_ready;
 420 wire sdram_interface_bank1_we;
 421 wire [21:0] sdram_interface_bank1_addr;
 422 wire sdram_interface_bank1_lock;
 423 wire sdram_interface_bank1_wdata_ready;
 424 wire sdram_interface_bank1_rdata_valid;
 425 wire sdram_interface_bank2_valid;
 426 wire sdram_interface_bank2_ready;
 427 wire sdram_interface_bank2_we;
 428 wire [21:0] sdram_interface_bank2_addr;
 429 wire sdram_interface_bank2_lock;
 430 wire sdram_interface_bank2_wdata_ready;
 431 wire sdram_interface_bank2_rdata_valid;
 432 wire sdram_interface_bank3_valid;
 433 wire sdram_interface_bank3_ready;
 434 wire sdram_interface_bank3_we;
 435 wire [21:0] sdram_interface_bank3_addr;
 436 wire sdram_interface_bank3_lock;
 437 wire sdram_interface_bank3_wdata_ready;
 438 wire sdram_interface_bank3_rdata_valid;
 439 reg [15:0] sdram_interface_wdata = 16'd0;
 440 reg [1:0] sdram_interface_wdata_we = 2'd0;
 441 wire [15:0] sdram_interface_rdata;
 442 reg [12:0] sdram_dfi_p0_address = 13'd0;
 443 reg [1:0] sdram_dfi_p0_bank = 2'd0;
 444 reg sdram_dfi_p0_cas_n = 1'd1;
 445 reg sdram_dfi_p0_cs_n = 1'd1;
 446 reg sdram_dfi_p0_ras_n = 1'd1;
 447 reg sdram_dfi_p0_we_n = 1'd1;
 448 wire sdram_dfi_p0_cke;
 449 wire sdram_dfi_p0_odt;
 450 wire sdram_dfi_p0_reset_n;
 451 reg sdram_dfi_p0_act_n = 1'd1;
 452 wire [15:0] sdram_dfi_p0_wrdata;
 453 reg sdram_dfi_p0_wrdata_en = 1'd0;
 454 wire [1:0] sdram_dfi_p0_wrdata_mask;
 455 reg sdram_dfi_p0_rddata_en = 1'd0;
 456 wire [15:0] sdram_dfi_p0_rddata;
 457 wire sdram_dfi_p0_rddata_valid;
 458 reg sdram_cmd_valid = 1'd0;
 459 reg sdram_cmd_ready = 1'd0;
 460 reg sdram_cmd_last = 1'd0;
 461 reg [12:0] sdram_cmd_payload_a = 13'd0;
 462 reg [1:0] sdram_cmd_payload_ba = 2'd0;
 463 reg sdram_cmd_payload_cas = 1'd0;
 464 reg sdram_cmd_payload_ras = 1'd0;
 465 reg sdram_cmd_payload_we = 1'd0;
 466 reg sdram_cmd_payload_is_read = 1'd0;
 467 reg sdram_cmd_payload_is_write = 1'd0;
 468 wire sdram_wants_refresh;
 469 wire sdram_timer_wait;
 470 wire sdram_timer_done0;
 471 wire [9:0] sdram_timer_count0;
 472 wire sdram_timer_done1;
 473 reg [9:0] sdram_timer_count1 = 10'd781;
 474 wire sdram_postponer_req_i;
 475 reg sdram_postponer_req_o = 1'd0;
 476 reg sdram_postponer_count = 1'd0;
 477 reg sdram_sequencer_start0 = 1'd0;
 478 wire sdram_sequencer_done0;
 479 wire sdram_sequencer_start1;
 480 reg sdram_sequencer_done1 = 1'd0;
 481 reg [3:0] sdram_sequencer_counter = 4'd0;
 482 reg sdram_sequencer_count = 1'd0;
 483 wire sdram_bankmachine0_req_valid;
 484 wire sdram_bankmachine0_req_ready;
 485 wire sdram_bankmachine0_req_we;
 486 wire [21:0] sdram_bankmachine0_req_addr;
 487 wire sdram_bankmachine0_req_lock;
 488 reg sdram_bankmachine0_req_wdata_ready = 1'd0;
 489 reg sdram_bankmachine0_req_rdata_valid = 1'd0;
 490 wire sdram_bankmachine0_refresh_req;
 491 reg sdram_bankmachine0_refresh_gnt = 1'd0;
 492 reg sdram_bankmachine0_cmd_valid = 1'd0;
 493 reg sdram_bankmachine0_cmd_ready = 1'd0;
 494 reg [12:0] sdram_bankmachine0_cmd_payload_a = 13'd0;
 495 wire [1:0] sdram_bankmachine0_cmd_payload_ba;
 496 reg sdram_bankmachine0_cmd_payload_cas = 1'd0;
 497 reg sdram_bankmachine0_cmd_payload_ras = 1'd0;
 498 reg sdram_bankmachine0_cmd_payload_we = 1'd0;
 499 reg sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
 500 reg sdram_bankmachine0_cmd_payload_is_read = 1'd0;
 501 reg sdram_bankmachine0_cmd_payload_is_write = 1'd0;
 502 reg sdram_bankmachine0_auto_precharge = 1'd0;
 503 wire sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
 504 wire sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
 505 reg sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
 506 reg sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
 507 wire sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
 508 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
 509 wire sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
 510 wire sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
 511 wire sdram_bankmachine0_cmd_buffer_lookahead_source_first;
 512 wire sdram_bankmachine0_cmd_buffer_lookahead_source_last;
 513 wire sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
 514 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
 515 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
 516 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
 517 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
 518 wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
 519 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
 520 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
 521 reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0;
 522 reg sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
 523 reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0;
 524 reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0;
 525 reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0;
 526 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
 527 wire sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
 528 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
 529 wire sdram_bankmachine0_cmd_buffer_lookahead_do_read;
 530 wire [2:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
 531 wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
 532 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
 533 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
 534 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
 535 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
 536 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
 537 wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
 538 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
 539 wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
 540 wire sdram_bankmachine0_cmd_buffer_sink_valid;
 541 wire sdram_bankmachine0_cmd_buffer_sink_ready;
 542 wire sdram_bankmachine0_cmd_buffer_sink_first;
 543 wire sdram_bankmachine0_cmd_buffer_sink_last;
 544 wire sdram_bankmachine0_cmd_buffer_sink_payload_we;
 545 wire [21:0] sdram_bankmachine0_cmd_buffer_sink_payload_addr;
 546 reg sdram_bankmachine0_cmd_buffer_source_valid = 1'd0;
 547 wire sdram_bankmachine0_cmd_buffer_source_ready;
 548 reg sdram_bankmachine0_cmd_buffer_source_first = 1'd0;
 549 reg sdram_bankmachine0_cmd_buffer_source_last = 1'd0;
 550 reg sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
 551 reg [21:0] sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
 552 reg [12:0] sdram_bankmachine0_row = 13'd0;
 553 reg sdram_bankmachine0_row_opened = 1'd0;
 554 wire sdram_bankmachine0_row_hit;
 555 reg sdram_bankmachine0_row_open = 1'd0;
 556 reg sdram_bankmachine0_row_close = 1'd0;
 557 reg sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
 558 wire sdram_bankmachine0_twtpcon_valid;
 559 (* no_retiming = "true" *) reg sdram_bankmachine0_twtpcon_ready = 1'd0;
 560 reg [2:0] sdram_bankmachine0_twtpcon_count = 3'd0;
 561 wire sdram_bankmachine0_trccon_valid;
 562 (* no_retiming = "true" *) reg sdram_bankmachine0_trccon_ready = 1'd1;
 563 wire sdram_bankmachine0_trascon_valid;
 564 (* no_retiming = "true" *) reg sdram_bankmachine0_trascon_ready = 1'd1;
 565 wire sdram_bankmachine1_req_valid;
 566 wire sdram_bankmachine1_req_ready;
 567 wire sdram_bankmachine1_req_we;
 568 wire [21:0] sdram_bankmachine1_req_addr;
 569 wire sdram_bankmachine1_req_lock;
 570 reg sdram_bankmachine1_req_wdata_ready = 1'd0;
 571 reg sdram_bankmachine1_req_rdata_valid = 1'd0;
 572 wire sdram_bankmachine1_refresh_req;
 573 reg sdram_bankmachine1_refresh_gnt = 1'd0;
 574 reg sdram_bankmachine1_cmd_valid = 1'd0;
 575 reg sdram_bankmachine1_cmd_ready = 1'd0;
 576 reg [12:0] sdram_bankmachine1_cmd_payload_a = 13'd0;
 577 wire [1:0] sdram_bankmachine1_cmd_payload_ba;
 578 reg sdram_bankmachine1_cmd_payload_cas = 1'd0;
 579 reg sdram_bankmachine1_cmd_payload_ras = 1'd0;
 580 reg sdram_bankmachine1_cmd_payload_we = 1'd0;
 581 reg sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
 582 reg sdram_bankmachine1_cmd_payload_is_read = 1'd0;
 583 reg sdram_bankmachine1_cmd_payload_is_write = 1'd0;
 584 reg sdram_bankmachine1_auto_precharge = 1'd0;
 585 wire sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
 586 wire sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
 587 reg sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
 588 reg sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
 589 wire sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
 590 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
 591 wire sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
 592 wire sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
 593 wire sdram_bankmachine1_cmd_buffer_lookahead_source_first;
 594 wire sdram_bankmachine1_cmd_buffer_lookahead_source_last;
 595 wire sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
 596 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
 597 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
 598 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
 599 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
 600 wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
 601 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
 602 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
 603 reg [3:0] sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0;
 604 reg sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
 605 reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0;
 606 reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0;
 607 reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0;
 608 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
 609 wire sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
 610 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
 611 wire sdram_bankmachine1_cmd_buffer_lookahead_do_read;
 612 wire [2:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
 613 wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
 614 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
 615 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
 616 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
 617 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
 618 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
 619 wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
 620 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
 621 wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
 622 wire sdram_bankmachine1_cmd_buffer_sink_valid;
 623 wire sdram_bankmachine1_cmd_buffer_sink_ready;
 624 wire sdram_bankmachine1_cmd_buffer_sink_first;
 625 wire sdram_bankmachine1_cmd_buffer_sink_last;
 626 wire sdram_bankmachine1_cmd_buffer_sink_payload_we;
 627 wire [21:0] sdram_bankmachine1_cmd_buffer_sink_payload_addr;
 628 reg sdram_bankmachine1_cmd_buffer_source_valid = 1'd0;
 629 wire sdram_bankmachine1_cmd_buffer_source_ready;
 630 reg sdram_bankmachine1_cmd_buffer_source_first = 1'd0;
 631 reg sdram_bankmachine1_cmd_buffer_source_last = 1'd0;
 632 reg sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
 633 reg [21:0] sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
 634 reg [12:0] sdram_bankmachine1_row = 13'd0;
 635 reg sdram_bankmachine1_row_opened = 1'd0;
 636 wire sdram_bankmachine1_row_hit;
 637 reg sdram_bankmachine1_row_open = 1'd0;
 638 reg sdram_bankmachine1_row_close = 1'd0;
 639 reg sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
 640 wire sdram_bankmachine1_twtpcon_valid;
 641 (* no_retiming = "true" *) reg sdram_bankmachine1_twtpcon_ready = 1'd0;
 642 reg [2:0] sdram_bankmachine1_twtpcon_count = 3'd0;
 643 wire sdram_bankmachine1_trccon_valid;
 644 (* no_retiming = "true" *) reg sdram_bankmachine1_trccon_ready = 1'd1;
 645 wire sdram_bankmachine1_trascon_valid;
 646 (* no_retiming = "true" *) reg sdram_bankmachine1_trascon_ready = 1'd1;
 647 wire sdram_bankmachine2_req_valid;
 648 wire sdram_bankmachine2_req_ready;
 649 wire sdram_bankmachine2_req_we;
 650 wire [21:0] sdram_bankmachine2_req_addr;
 651 wire sdram_bankmachine2_req_lock;
 652 reg sdram_bankmachine2_req_wdata_ready = 1'd0;
 653 reg sdram_bankmachine2_req_rdata_valid = 1'd0;
 654 wire sdram_bankmachine2_refresh_req;
 655 reg sdram_bankmachine2_refresh_gnt = 1'd0;
 656 reg sdram_bankmachine2_cmd_valid = 1'd0;
 657 reg sdram_bankmachine2_cmd_ready = 1'd0;
 658 reg [12:0] sdram_bankmachine2_cmd_payload_a = 13'd0;
 659 wire [1:0] sdram_bankmachine2_cmd_payload_ba;
 660 reg sdram_bankmachine2_cmd_payload_cas = 1'd0;
 661 reg sdram_bankmachine2_cmd_payload_ras = 1'd0;
 662 reg sdram_bankmachine2_cmd_payload_we = 1'd0;
 663 reg sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
 664 reg sdram_bankmachine2_cmd_payload_is_read = 1'd0;
 665 reg sdram_bankmachine2_cmd_payload_is_write = 1'd0;
 666 reg sdram_bankmachine2_auto_precharge = 1'd0;
 667 wire sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
 668 wire sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
 669 reg sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
 670 reg sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
 671 wire sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
 672 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
 673 wire sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
 674 wire sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
 675 wire sdram_bankmachine2_cmd_buffer_lookahead_source_first;
 676 wire sdram_bankmachine2_cmd_buffer_lookahead_source_last;
 677 wire sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
 678 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
 679 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
 680 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
 681 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
 682 wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
 683 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
 684 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
 685 reg [3:0] sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0;
 686 reg sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
 687 reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0;
 688 reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0;
 689 reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0;
 690 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
 691 wire sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
 692 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
 693 wire sdram_bankmachine2_cmd_buffer_lookahead_do_read;
 694 wire [2:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
 695 wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
 696 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
 697 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
 698 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
 699 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
 700 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
 701 wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
 702 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
 703 wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
 704 wire sdram_bankmachine2_cmd_buffer_sink_valid;
 705 wire sdram_bankmachine2_cmd_buffer_sink_ready;
 706 wire sdram_bankmachine2_cmd_buffer_sink_first;
 707 wire sdram_bankmachine2_cmd_buffer_sink_last;
 708 wire sdram_bankmachine2_cmd_buffer_sink_payload_we;
 709 wire [21:0] sdram_bankmachine2_cmd_buffer_sink_payload_addr;
 710 reg sdram_bankmachine2_cmd_buffer_source_valid = 1'd0;
 711 wire sdram_bankmachine2_cmd_buffer_source_ready;
 712 reg sdram_bankmachine2_cmd_buffer_source_first = 1'd0;
 713 reg sdram_bankmachine2_cmd_buffer_source_last = 1'd0;
 714 reg sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
 715 reg [21:0] sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
 716 reg [12:0] sdram_bankmachine2_row = 13'd0;
 717 reg sdram_bankmachine2_row_opened = 1'd0;
 718 wire sdram_bankmachine2_row_hit;
 719 reg sdram_bankmachine2_row_open = 1'd0;
 720 reg sdram_bankmachine2_row_close = 1'd0;
 721 reg sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
 722 wire sdram_bankmachine2_twtpcon_valid;
 723 (* no_retiming = "true" *) reg sdram_bankmachine2_twtpcon_ready = 1'd0;
 724 reg [2:0] sdram_bankmachine2_twtpcon_count = 3'd0;
 725 wire sdram_bankmachine2_trccon_valid;
 726 (* no_retiming = "true" *) reg sdram_bankmachine2_trccon_ready = 1'd1;
 727 wire sdram_bankmachine2_trascon_valid;
 728 (* no_retiming = "true" *) reg sdram_bankmachine2_trascon_ready = 1'd1;
 729 wire sdram_bankmachine3_req_valid;
 730 wire sdram_bankmachine3_req_ready;
 731 wire sdram_bankmachine3_req_we;
 732 wire [21:0] sdram_bankmachine3_req_addr;
 733 wire sdram_bankmachine3_req_lock;
 734 reg sdram_bankmachine3_req_wdata_ready = 1'd0;
 735 reg sdram_bankmachine3_req_rdata_valid = 1'd0;
 736 wire sdram_bankmachine3_refresh_req;
 737 reg sdram_bankmachine3_refresh_gnt = 1'd0;
 738 reg sdram_bankmachine3_cmd_valid = 1'd0;
 739 reg sdram_bankmachine3_cmd_ready = 1'd0;
 740 reg [12:0] sdram_bankmachine3_cmd_payload_a = 13'd0;
 741 wire [1:0] sdram_bankmachine3_cmd_payload_ba;
 742 reg sdram_bankmachine3_cmd_payload_cas = 1'd0;
 743 reg sdram_bankmachine3_cmd_payload_ras = 1'd0;
 744 reg sdram_bankmachine3_cmd_payload_we = 1'd0;
 745 reg sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
 746 reg sdram_bankmachine3_cmd_payload_is_read = 1'd0;
 747 reg sdram_bankmachine3_cmd_payload_is_write = 1'd0;
 748 reg sdram_bankmachine3_auto_precharge = 1'd0;
 749 wire sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
 750 wire sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
 751 reg sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
 752 reg sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
 753 wire sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
 754 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
 755 wire sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
 756 wire sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
 757 wire sdram_bankmachine3_cmd_buffer_lookahead_source_first;
 758 wire sdram_bankmachine3_cmd_buffer_lookahead_source_last;
 759 wire sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
 760 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
 761 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
 762 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
 763 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
 764 wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
 765 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
 766 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
 767 reg [3:0] sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0;
 768 reg sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
 769 reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0;
 770 reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0;
 771 reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0;
 772 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
 773 wire sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
 774 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
 775 wire sdram_bankmachine3_cmd_buffer_lookahead_do_read;
 776 wire [2:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
 777 wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
 778 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
 779 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
 780 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
 781 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
 782 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
 783 wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
 784 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
 785 wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
 786 wire sdram_bankmachine3_cmd_buffer_sink_valid;
 787 wire sdram_bankmachine3_cmd_buffer_sink_ready;
 788 wire sdram_bankmachine3_cmd_buffer_sink_first;
 789 wire sdram_bankmachine3_cmd_buffer_sink_last;
 790 wire sdram_bankmachine3_cmd_buffer_sink_payload_we;
 791 wire [21:0] sdram_bankmachine3_cmd_buffer_sink_payload_addr;
 792 reg sdram_bankmachine3_cmd_buffer_source_valid = 1'd0;
 793 wire sdram_bankmachine3_cmd_buffer_source_ready;
 794 reg sdram_bankmachine3_cmd_buffer_source_first = 1'd0;
 795 reg sdram_bankmachine3_cmd_buffer_source_last = 1'd0;
 796 reg sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
 797 reg [21:0] sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
 798 reg [12:0] sdram_bankmachine3_row = 13'd0;
 799 reg sdram_bankmachine3_row_opened = 1'd0;
 800 wire sdram_bankmachine3_row_hit;
 801 reg sdram_bankmachine3_row_open = 1'd0;
 802 reg sdram_bankmachine3_row_close = 1'd0;
 803 reg sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
 804 wire sdram_bankmachine3_twtpcon_valid;
 805 (* no_retiming = "true" *) reg sdram_bankmachine3_twtpcon_ready = 1'd0;
 806 reg [2:0] sdram_bankmachine3_twtpcon_count = 3'd0;
 807 wire sdram_bankmachine3_trccon_valid;
 808 (* no_retiming = "true" *) reg sdram_bankmachine3_trccon_ready = 1'd1;
 809 wire sdram_bankmachine3_trascon_valid;
 810 (* no_retiming = "true" *) reg sdram_bankmachine3_trascon_ready = 1'd1;
 811 wire sdram_ras_allowed;
 812 wire sdram_cas_allowed;
 813 reg sdram_choose_cmd_want_reads = 1'd0;
 814 reg sdram_choose_cmd_want_writes = 1'd0;
 815 reg sdram_choose_cmd_want_cmds = 1'd0;
 816 reg sdram_choose_cmd_want_activates = 1'd0;
 817 wire sdram_choose_cmd_cmd_valid;
 818 reg sdram_choose_cmd_cmd_ready = 1'd0;
 819 wire [12:0] sdram_choose_cmd_cmd_payload_a;
 820 wire [1:0] sdram_choose_cmd_cmd_payload_ba;
 821 reg sdram_choose_cmd_cmd_payload_cas = 1'd0;
 822 reg sdram_choose_cmd_cmd_payload_ras = 1'd0;
 823 reg sdram_choose_cmd_cmd_payload_we = 1'd0;
 824 wire sdram_choose_cmd_cmd_payload_is_cmd;
 825 wire sdram_choose_cmd_cmd_payload_is_read;
 826 wire sdram_choose_cmd_cmd_payload_is_write;
 827 reg [3:0] sdram_choose_cmd_valids = 4'd0;
 828 wire [3:0] sdram_choose_cmd_request;
 829 reg [1:0] sdram_choose_cmd_grant = 2'd0;
 830 wire sdram_choose_cmd_ce;
 831 reg sdram_choose_req_want_reads = 1'd0;
 832 reg sdram_choose_req_want_writes = 1'd0;
 833 wire sdram_choose_req_want_cmds;
 834 reg sdram_choose_req_want_activates = 1'd0;
 835 wire sdram_choose_req_cmd_valid;
 836 reg sdram_choose_req_cmd_ready = 1'd0;
 837 wire [12:0] sdram_choose_req_cmd_payload_a;
 838 wire [1:0] sdram_choose_req_cmd_payload_ba;
 839 reg sdram_choose_req_cmd_payload_cas = 1'd0;
 840 reg sdram_choose_req_cmd_payload_ras = 1'd0;
 841 reg sdram_choose_req_cmd_payload_we = 1'd0;
 842 wire sdram_choose_req_cmd_payload_is_cmd;
 843 wire sdram_choose_req_cmd_payload_is_read;
 844 wire sdram_choose_req_cmd_payload_is_write;
 845 reg [3:0] sdram_choose_req_valids = 4'd0;
 846 wire [3:0] sdram_choose_req_request;
 847 reg [1:0] sdram_choose_req_grant = 2'd0;
 848 wire sdram_choose_req_ce;
 849 reg [12:0] sdram_nop_a = 13'd0;
 850 reg [1:0] sdram_nop_ba = 2'd0;
 851 reg [1:0] sdram_steerer_sel = 2'd0;
 852 reg sdram_steerer0 = 1'd1;
 853 reg sdram_steerer1 = 1'd1;
 854 wire sdram_trrdcon_valid;
 855 (* no_retiming = "true" *) reg sdram_trrdcon_ready = 1'd1;
 856 wire sdram_tfawcon_valid;
 857 (* no_retiming = "true" *) reg sdram_tfawcon_ready = 1'd1;
 858 wire sdram_tccdcon_valid;
 859 (* no_retiming = "true" *) reg sdram_tccdcon_ready = 1'd0;
 860 reg sdram_tccdcon_count = 1'd0;
 861 wire sdram_twtrcon_valid;
 862 (* no_retiming = "true" *) reg sdram_twtrcon_ready = 1'd0;
 863 reg [2:0] sdram_twtrcon_count = 3'd0;
 864 wire sdram_read_available;
 865 wire sdram_write_available;
 866 reg sdram_en0 = 1'd0;
 867 wire sdram_max_time0;
 868 reg [4:0] sdram_time0 = 5'd0;
 869 reg sdram_en1 = 1'd0;
 870 wire sdram_max_time1;
 871 reg [3:0] sdram_time1 = 4'd0;
 872 wire sdram_go_to_refresh;
 873 wire port_flush;
 874 wire port_cmd_valid;
 875 wire port_cmd_ready;
 876 wire port_cmd_last;
 877 wire port_cmd_payload_we;
 878 wire [23:0] port_cmd_payload_addr;
 879 wire port_wdata_valid;
 880 wire port_wdata_ready;
 881 wire [15:0] port_wdata_payload_data;
 882 wire [1:0] port_wdata_payload_we;
 883 wire port_rdata_valid;
 884 wire port_rdata_ready;
 885 wire [15:0] port_rdata_payload_data;
 886 wire [29:0] wb_sdram_adr;
 887 wire [31:0] wb_sdram_dat_w;
 888 wire [31:0] wb_sdram_dat_r;
 889 wire [3:0] wb_sdram_sel;
 890 wire wb_sdram_cyc;
 891 wire wb_sdram_stb;
 892 reg wb_sdram_ack = 1'd0;
 893 wire wb_sdram_we;
 894 wire [2:0] wb_sdram_cti;
 895 wire [1:0] wb_sdram_bte;
 896 reg wb_sdram_err = 1'd0;
 897 reg [29:0] litedram_wb_adr = 30'd0;
 898 reg [15:0] litedram_wb_dat_w = 16'd0;
 899 wire [15:0] litedram_wb_dat_r;
 900 reg [1:0] litedram_wb_sel = 2'd0;
 901 reg litedram_wb_cyc = 1'd0;
 902 reg litedram_wb_stb = 1'd0;
 903 wire litedram_wb_ack;
 904 reg litedram_wb_we = 1'd0;
 905 reg converter_skip = 1'd0;
 906 reg converter_counter = 1'd0;
 907 wire converter_reset;
 908 reg [31:0] converter_dat_r = 32'd0;
 909 reg cmd_consumed = 1'd0;
 910 reg wdata_consumed = 1'd0;
 911 wire ack_cmd;
 912 wire ack_wdata;
 913 wire ack_rdata;
 914 (* ram_style = "distributed" *) reg [31:0] uart_phy_storage = 32'd9895604;
 915 reg uart_phy_re = 1'd0;
 916 wire uart_phy_sink_valid;
 917 reg uart_phy_sink_ready = 1'd0;
 918 wire uart_phy_sink_first;
 919 wire uart_phy_sink_last;
 920 wire [7:0] uart_phy_sink_payload_data;
 921 reg uart_phy_uart_clk_txen = 1'd0;
 922 reg [31:0] uart_phy_phase_accumulator_tx = 32'd0;
 923 reg [7:0] uart_phy_tx_reg = 8'd0;
 924 reg [3:0] uart_phy_tx_bitcount = 4'd0;
 925 reg uart_phy_tx_busy = 1'd0;
 926 reg uart_phy_source_valid = 1'd0;
 927 wire uart_phy_source_ready;
 928 reg uart_phy_source_first = 1'd0;
 929 reg uart_phy_source_last = 1'd0;
 930 reg [7:0] uart_phy_source_payload_data = 8'd0;
 931 reg uart_phy_uart_clk_rxen = 1'd0;
 932 reg [31:0] uart_phy_phase_accumulator_rx = 32'd0;
 933 wire uart_phy_rx;
 934 reg uart_phy_rx_r = 1'd0;
 935 reg [7:0] uart_phy_rx_reg = 8'd0;
 936 reg [3:0] uart_phy_rx_bitcount = 4'd0;
 937 reg uart_phy_rx_busy = 1'd0;
 938 wire rxtx_re;
 939 wire [7:0] rxtx_r;
 940 wire rxtx_we;
 941 wire [7:0] rxtx_w;
 942 wire txfull_status;
 943 wire txfull_we;
 944 wire rxempty_status;
 945 wire rxempty_we;
 946 wire irq;
 947 wire tx_status;
 948 reg tx_pending = 1'd0;
 949 wire tx_trigger;
 950 reg tx_clear = 1'd0;
 951 reg tx_old_trigger = 1'd0;
 952 wire rx_status;
 953 reg rx_pending = 1'd0;
 954 wire rx_trigger;
 955 reg rx_clear = 1'd0;
 956 reg rx_old_trigger = 1'd0;
 957 wire eventmanager_status_re;
 958 wire [1:0] eventmanager_status_r;
 959 wire eventmanager_status_we;
 960 reg [1:0] eventmanager_status_w = 2'd0;
 961 wire eventmanager_pending_re;
 962 wire [1:0] eventmanager_pending_r;
 963 wire eventmanager_pending_we;
 964 reg [1:0] eventmanager_pending_w = 2'd0;
 965 (* ram_style = "distributed" *) reg [1:0] eventmanager_storage = 2'd0;
 966 reg eventmanager_re = 1'd0;
 967 wire txempty_status;
 968 wire txempty_we;
 969 wire rxfull_status;
 970 wire rxfull_we;
 971 wire uart_sink_valid;
 972 wire uart_sink_ready;
 973 wire uart_sink_first;
 974 wire uart_sink_last;
 975 wire [7:0] uart_sink_payload_data;
 976 wire uart_source_valid;
 977 wire uart_source_ready;
 978 wire uart_source_first;
 979 wire uart_source_last;
 980 wire [7:0] uart_source_payload_data;
 981 wire tx_fifo_sink_valid;
 982 wire tx_fifo_sink_ready;
 983 reg tx_fifo_sink_first = 1'd0;
 984 reg tx_fifo_sink_last = 1'd0;
 985 wire [7:0] tx_fifo_sink_payload_data;
 986 wire tx_fifo_source_valid;
 987 wire tx_fifo_source_ready;
 988 wire tx_fifo_source_first;
 989 wire tx_fifo_source_last;
 990 wire [7:0] tx_fifo_source_payload_data;
 991 wire tx_fifo_re;
 992 reg tx_fifo_readable = 1'd0;
 993 wire tx_fifo_syncfifo_we;
 994 wire tx_fifo_syncfifo_writable;
 995 wire tx_fifo_syncfifo_re;
 996 wire tx_fifo_syncfifo_readable;
 997 wire [9:0] tx_fifo_syncfifo_din;
 998 wire [9:0] tx_fifo_syncfifo_dout;
 999 reg [4:0] tx_fifo_level0 = 5'd0;
1000 reg tx_fifo_replace = 1'd0;
1001 reg [3:0] tx_fifo_produce = 4'd0;
1002 reg [3:0] tx_fifo_consume = 4'd0;
1003 reg [3:0] tx_fifo_wrport_adr = 4'd0;
1004 wire [9:0] tx_fifo_wrport_dat_r;
1005 wire tx_fifo_wrport_we;
1006 wire [9:0] tx_fifo_wrport_dat_w;
1007 wire tx_fifo_do_read;
1008 wire [3:0] tx_fifo_rdport_adr;
1009 wire [9:0] tx_fifo_rdport_dat_r;
1010 wire tx_fifo_rdport_re;
1011 wire [4:0] tx_fifo_level1;
1012 wire [7:0] tx_fifo_fifo_in_payload_data;
1013 wire tx_fifo_fifo_in_first;
1014 wire tx_fifo_fifo_in_last;
1015 wire [7:0] tx_fifo_fifo_out_payload_data;
1016 wire tx_fifo_fifo_out_first;
1017 wire tx_fifo_fifo_out_last;
1018 wire rx_fifo_sink_valid;
1019 wire rx_fifo_sink_ready;
1020 wire rx_fifo_sink_first;
1021 wire rx_fifo_sink_last;
1022 wire [7:0] rx_fifo_sink_payload_data;
1023 wire rx_fifo_source_valid;
1024 wire rx_fifo_source_ready;
1025 wire rx_fifo_source_first;
1026 wire rx_fifo_source_last;
1027 wire [7:0] rx_fifo_source_payload_data;
1028 wire rx_fifo_re;
1029 reg rx_fifo_readable = 1'd0;
1030 wire rx_fifo_syncfifo_we;
1031 wire rx_fifo_syncfifo_writable;
1032 wire rx_fifo_syncfifo_re;
1033 wire rx_fifo_syncfifo_readable;
1034 wire [9:0] rx_fifo_syncfifo_din;
1035 wire [9:0] rx_fifo_syncfifo_dout;
1036 reg [4:0] rx_fifo_level0 = 5'd0;
1037 reg rx_fifo_replace = 1'd0;
1038 reg [3:0] rx_fifo_produce = 4'd0;
1039 reg [3:0] rx_fifo_consume = 4'd0;
1040 reg [3:0] rx_fifo_wrport_adr = 4'd0;
1041 wire [9:0] rx_fifo_wrport_dat_r;
1042 wire rx_fifo_wrport_we;
1043 wire [9:0] rx_fifo_wrport_dat_w;
1044 wire rx_fifo_do_read;
1045 wire [3:0] rx_fifo_rdport_adr;
1046 wire [9:0] rx_fifo_rdport_dat_r;
1047 wire rx_fifo_rdport_re;
1048 wire [4:0] rx_fifo_level1;
1049 wire [7:0] rx_fifo_fifo_in_payload_data;
1050 wire rx_fifo_fifo_in_first;
1051 wire rx_fifo_fifo_in_last;
1052 wire [7:0] rx_fifo_fifo_out_payload_data;
1053 wire rx_fifo_fifo_out_first;
1054 wire rx_fifo_fifo_out_last;
1055 reg reset = 1'd0;
1056 (* ram_style = "distributed" *) reg [7:0] gpio0_oe_storage = 8'd0;
1057 reg gpio0_oe_re = 1'd0;
1058 reg [7:0] gpio0_status = 8'd0;
1059 wire gpio0_we;
1060 (* ram_style = "distributed" *) reg [7:0] gpio0_out_storage = 8'd0;
1061 reg gpio0_out_re = 1'd0;
1062 reg [7:0] gpio0_pads_gpio0i = 8'd0;
1063 reg [7:0] gpio0_pads_gpio0o = 8'd0;
1064 reg [7:0] gpio0_pads_gpio0oe = 8'd0;
1065 (* ram_style = "distributed" *) reg [7:0] gpio1_oe_storage = 8'd0;
1066 reg gpio1_oe_re = 1'd0;
1067 reg [7:0] gpio1_status = 8'd0;
1068 wire gpio1_we;
1069 (* ram_style = "distributed" *) reg [7:0] gpio1_out_storage = 8'd0;
1070 reg gpio1_out_re = 1'd0;
1071 reg [7:0] gpio1_pads_gpio1i = 8'd0;
1072 reg [7:0] gpio1_pads_gpio1o = 8'd0;
1073 reg [7:0] gpio1_pads_gpio1oe = 8'd0;
1074 reg [2:0] eint_tmp = 3'd0;
1075 wire [35:0] nc_1;
1076 reg [35:0] dummy = 36'd0;
1077 wire i2c_scl_1;
1078 wire i2c_oe;
1079 wire i2c_sda0;
1080 (* ram_style = "distributed" *) reg [2:0] i2c_storage = 3'd0;
1081 reg i2c_re = 1'd0;
1082 wire i2c_sda1;
1083 wire i2c_status;
1084 wire i2c_we;
1085 reg subfragments_converter0_state = 1'd0;
1086 reg subfragments_converter0_next_state = 1'd0;
1087 reg libresocsim_converter0_counter_subfragments_converter0_next_value = 1'd0;
1088 reg libresocsim_converter0_counter_subfragments_converter0_next_value_ce = 1'd0;
1089 reg subfragments_converter1_state = 1'd0;
1090 reg subfragments_converter1_next_state = 1'd0;
1091 reg libresocsim_converter1_counter_subfragments_converter1_next_value = 1'd0;
1092 reg libresocsim_converter1_counter_subfragments_converter1_next_value_ce = 1'd0;
1093 reg [1:0] subfragments_refresher_state = 2'd0;
1094 reg [1:0] subfragments_refresher_next_state = 2'd0;
1095 reg [2:0] subfragments_bankmachine0_state = 3'd0;
1096 reg [2:0] subfragments_bankmachine0_next_state = 3'd0;
1097 reg [2:0] subfragments_bankmachine1_state = 3'd0;
1098 reg [2:0] subfragments_bankmachine1_next_state = 3'd0;
1099 reg [2:0] subfragments_bankmachine2_state = 3'd0;
1100 reg [2:0] subfragments_bankmachine2_next_state = 3'd0;
1101 reg [2:0] subfragments_bankmachine3_state = 3'd0;
1102 reg [2:0] subfragments_bankmachine3_next_state = 3'd0;
1103 reg [2:0] subfragments_multiplexer_state = 3'd0;
1104 reg [2:0] subfragments_multiplexer_next_state = 3'd0;
1105 wire subfragments_roundrobin0_request;
1106 wire subfragments_roundrobin0_grant;
1107 wire subfragments_roundrobin0_ce;
1108 wire subfragments_roundrobin1_request;
1109 wire subfragments_roundrobin1_grant;
1110 wire subfragments_roundrobin1_ce;
1111 wire subfragments_roundrobin2_request;
1112 wire subfragments_roundrobin2_grant;
1113 wire subfragments_roundrobin2_ce;
1114 wire subfragments_roundrobin3_request;
1115 wire subfragments_roundrobin3_grant;
1116 wire subfragments_roundrobin3_ce;
1117 reg subfragments_locked0 = 1'd0;
1118 reg subfragments_locked1 = 1'd0;
1119 reg subfragments_locked2 = 1'd0;
1120 reg subfragments_locked3 = 1'd0;
1121 reg subfragments_new_master_wdata_ready = 1'd0;
1122 reg subfragments_new_master_rdata_valid0 = 1'd0;
1123 reg subfragments_new_master_rdata_valid1 = 1'd0;
1124 reg subfragments_new_master_rdata_valid2 = 1'd0;
1125 reg subfragments_new_master_rdata_valid3 = 1'd0;
1126 reg subfragments_state = 1'd0;
1127 reg subfragments_next_state = 1'd0;
1128 reg converter_counter_subfragments_next_value = 1'd0;
1129 reg converter_counter_subfragments_next_value_ce = 1'd0;
1130 reg [12:0] libresocsim_libresocsim_adr = 13'd0;
1131 reg libresocsim_libresocsim_we = 1'd0;
1132 reg [7:0] libresocsim_libresocsim_dat_w = 8'd0;
1133 wire [7:0] libresocsim_libresocsim_dat_r;
1134 wire [29:0] libresocsim_libresocsim_wishbone_adr;
1135 wire [31:0] libresocsim_libresocsim_wishbone_dat_w;
1136 reg [31:0] libresocsim_libresocsim_wishbone_dat_r = 32'd0;
1137 wire [3:0] libresocsim_libresocsim_wishbone_sel;
1138 wire libresocsim_libresocsim_wishbone_cyc;
1139 wire libresocsim_libresocsim_wishbone_stb;
1140 reg libresocsim_libresocsim_wishbone_ack = 1'd0;
1141 wire libresocsim_libresocsim_wishbone_we;
1142 wire [2:0] libresocsim_libresocsim_wishbone_cti;
1143 wire [1:0] libresocsim_libresocsim_wishbone_bte;
1144 reg libresocsim_libresocsim_wishbone_err = 1'd0;
1145 wire [29:0] libresocsim_shared_adr;
1146 wire [31:0] libresocsim_shared_dat_w;
1147 reg [31:0] libresocsim_shared_dat_r = 32'd0;
1148 wire [3:0] libresocsim_shared_sel;
1149 wire libresocsim_shared_cyc;
1150 wire libresocsim_shared_stb;
1151 reg libresocsim_shared_ack = 1'd0;
1152 wire libresocsim_shared_we;
1153 wire [2:0] libresocsim_shared_cti;
1154 wire [1:0] libresocsim_shared_bte;
1155 wire libresocsim_shared_err;
1156 wire [2:0] libresocsim_request;
1157 reg [1:0] libresocsim_grant = 2'd0;
1158 reg [9:0] libresocsim_slave_sel = 10'd0;
1159 reg [9:0] libresocsim_slave_sel_r = 10'd0;
1160 reg libresocsim_error = 1'd0;
1161 wire libresocsim_wait;
1162 wire libresocsim_done;
1163 reg [19:0] libresocsim_count = 20'd1000000;
1164 wire [12:0] libresocsim_interface0_bank_bus_adr;
1165 wire libresocsim_interface0_bank_bus_we;
1166 wire [7:0] libresocsim_interface0_bank_bus_dat_w;
1167 reg [7:0] libresocsim_interface0_bank_bus_dat_r = 8'd0;
1168 wire libresocsim_csrbank0_reset0_re;
1169 wire libresocsim_csrbank0_reset0_r;
1170 wire libresocsim_csrbank0_reset0_we;
1171 wire libresocsim_csrbank0_reset0_w;
1172 wire libresocsim_csrbank0_scratch3_re;
1173 wire [7:0] libresocsim_csrbank0_scratch3_r;
1174 wire libresocsim_csrbank0_scratch3_we;
1175 wire [7:0] libresocsim_csrbank0_scratch3_w;
1176 wire libresocsim_csrbank0_scratch2_re;
1177 wire [7:0] libresocsim_csrbank0_scratch2_r;
1178 wire libresocsim_csrbank0_scratch2_we;
1179 wire [7:0] libresocsim_csrbank0_scratch2_w;
1180 wire libresocsim_csrbank0_scratch1_re;
1181 wire [7:0] libresocsim_csrbank0_scratch1_r;
1182 wire libresocsim_csrbank0_scratch1_we;
1183 wire [7:0] libresocsim_csrbank0_scratch1_w;
1184 wire libresocsim_csrbank0_scratch0_re;
1185 wire [7:0] libresocsim_csrbank0_scratch0_r;
1186 wire libresocsim_csrbank0_scratch0_we;
1187 wire [7:0] libresocsim_csrbank0_scratch0_w;
1188 wire libresocsim_csrbank0_bus_errors3_re;
1189 wire [7:0] libresocsim_csrbank0_bus_errors3_r;
1190 wire libresocsim_csrbank0_bus_errors3_we;
1191 wire [7:0] libresocsim_csrbank0_bus_errors3_w;
1192 wire libresocsim_csrbank0_bus_errors2_re;
1193 wire [7:0] libresocsim_csrbank0_bus_errors2_r;
1194 wire libresocsim_csrbank0_bus_errors2_we;
1195 wire [7:0] libresocsim_csrbank0_bus_errors2_w;
1196 wire libresocsim_csrbank0_bus_errors1_re;
1197 wire [7:0] libresocsim_csrbank0_bus_errors1_r;
1198 wire libresocsim_csrbank0_bus_errors1_we;
1199 wire [7:0] libresocsim_csrbank0_bus_errors1_w;
1200 wire libresocsim_csrbank0_bus_errors0_re;
1201 wire [7:0] libresocsim_csrbank0_bus_errors0_r;
1202 wire libresocsim_csrbank0_bus_errors0_we;
1203 wire [7:0] libresocsim_csrbank0_bus_errors0_w;
1204 wire libresocsim_csrbank0_sel;
1205 wire [12:0] libresocsim_interface1_bank_bus_adr;
1206 wire libresocsim_interface1_bank_bus_we;
1207 wire [7:0] libresocsim_interface1_bank_bus_dat_w;
1208 reg [7:0] libresocsim_interface1_bank_bus_dat_r = 8'd0;
1209 wire libresocsim_csrbank1_oe0_re;
1210 wire [7:0] libresocsim_csrbank1_oe0_r;
1211 wire libresocsim_csrbank1_oe0_we;
1212 wire [7:0] libresocsim_csrbank1_oe0_w;
1213 wire libresocsim_csrbank1_in_re;
1214 wire [7:0] libresocsim_csrbank1_in_r;
1215 wire libresocsim_csrbank1_in_we;
1216 wire [7:0] libresocsim_csrbank1_in_w;
1217 wire libresocsim_csrbank1_out0_re;
1218 wire [7:0] libresocsim_csrbank1_out0_r;
1219 wire libresocsim_csrbank1_out0_we;
1220 wire [7:0] libresocsim_csrbank1_out0_w;
1221 wire libresocsim_csrbank1_sel;
1222 wire [12:0] libresocsim_interface2_bank_bus_adr;
1223 wire libresocsim_interface2_bank_bus_we;
1224 wire [7:0] libresocsim_interface2_bank_bus_dat_w;
1225 reg [7:0] libresocsim_interface2_bank_bus_dat_r = 8'd0;
1226 wire libresocsim_csrbank2_oe0_re;
1227 wire [7:0] libresocsim_csrbank2_oe0_r;
1228 wire libresocsim_csrbank2_oe0_we;
1229 wire [7:0] libresocsim_csrbank2_oe0_w;
1230 wire libresocsim_csrbank2_in_re;
1231 wire [7:0] libresocsim_csrbank2_in_r;
1232 wire libresocsim_csrbank2_in_we;
1233 wire [7:0] libresocsim_csrbank2_in_w;
1234 wire libresocsim_csrbank2_out0_re;
1235 wire [7:0] libresocsim_csrbank2_out0_r;
1236 wire libresocsim_csrbank2_out0_we;
1237 wire [7:0] libresocsim_csrbank2_out0_w;
1238 wire libresocsim_csrbank2_sel;
1239 wire [12:0] libresocsim_interface3_bank_bus_adr;
1240 wire libresocsim_interface3_bank_bus_we;
1241 wire [7:0] libresocsim_interface3_bank_bus_dat_w;
1242 reg [7:0] libresocsim_interface3_bank_bus_dat_r = 8'd0;
1243 wire libresocsim_csrbank3_w0_re;
1244 wire [2:0] libresocsim_csrbank3_w0_r;
1245 wire libresocsim_csrbank3_w0_we;
1246 wire [2:0] libresocsim_csrbank3_w0_w;
1247 wire libresocsim_csrbank3_r_re;
1248 wire libresocsim_csrbank3_r_r;
1249 wire libresocsim_csrbank3_r_we;
1250 wire libresocsim_csrbank3_r_w;
1251 wire libresocsim_csrbank3_sel;
1252 wire [12:0] libresocsim_interface4_bank_bus_adr;
1253 wire libresocsim_interface4_bank_bus_we;
1254 wire [7:0] libresocsim_interface4_bank_bus_dat_w;
1255 reg [7:0] libresocsim_interface4_bank_bus_dat_r = 8'd0;
1256 wire libresocsim_csrbank4_dfii_control0_re;
1257 wire [3:0] libresocsim_csrbank4_dfii_control0_r;
1258 wire libresocsim_csrbank4_dfii_control0_we;
1259 wire [3:0] libresocsim_csrbank4_dfii_control0_w;
1260 wire libresocsim_csrbank4_dfii_pi0_command0_re;
1261 wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_r;
1262 wire libresocsim_csrbank4_dfii_pi0_command0_we;
1263 wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_w;
1264 wire libresocsim_csrbank4_dfii_pi0_address1_re;
1265 wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_r;
1266 wire libresocsim_csrbank4_dfii_pi0_address1_we;
1267 wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_w;
1268 wire libresocsim_csrbank4_dfii_pi0_address0_re;
1269 wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_r;
1270 wire libresocsim_csrbank4_dfii_pi0_address0_we;
1271 wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_w;
1272 wire libresocsim_csrbank4_dfii_pi0_baddress0_re;
1273 wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_r;
1274 wire libresocsim_csrbank4_dfii_pi0_baddress0_we;
1275 wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_w;
1276 wire libresocsim_csrbank4_dfii_pi0_wrdata1_re;
1277 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_r;
1278 wire libresocsim_csrbank4_dfii_pi0_wrdata1_we;
1279 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_w;
1280 wire libresocsim_csrbank4_dfii_pi0_wrdata0_re;
1281 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_r;
1282 wire libresocsim_csrbank4_dfii_pi0_wrdata0_we;
1283 wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_w;
1284 wire libresocsim_csrbank4_dfii_pi0_rddata1_re;
1285 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_r;
1286 wire libresocsim_csrbank4_dfii_pi0_rddata1_we;
1287 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_w;
1288 wire libresocsim_csrbank4_dfii_pi0_rddata0_re;
1289 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_r;
1290 wire libresocsim_csrbank4_dfii_pi0_rddata0_we;
1291 wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_w;
1292 wire libresocsim_csrbank4_sel;
1293 wire [12:0] libresocsim_interface5_bank_bus_adr;
1294 wire libresocsim_interface5_bank_bus_we;
1295 wire [7:0] libresocsim_interface5_bank_bus_dat_w;
1296 reg [7:0] libresocsim_interface5_bank_bus_dat_r = 8'd0;
1297 wire libresocsim_csrbank5_load3_re;
1298 wire [7:0] libresocsim_csrbank5_load3_r;
1299 wire libresocsim_csrbank5_load3_we;
1300 wire [7:0] libresocsim_csrbank5_load3_w;
1301 wire libresocsim_csrbank5_load2_re;
1302 wire [7:0] libresocsim_csrbank5_load2_r;
1303 wire libresocsim_csrbank5_load2_we;
1304 wire [7:0] libresocsim_csrbank5_load2_w;
1305 wire libresocsim_csrbank5_load1_re;
1306 wire [7:0] libresocsim_csrbank5_load1_r;
1307 wire libresocsim_csrbank5_load1_we;
1308 wire [7:0] libresocsim_csrbank5_load1_w;
1309 wire libresocsim_csrbank5_load0_re;
1310 wire [7:0] libresocsim_csrbank5_load0_r;
1311 wire libresocsim_csrbank5_load0_we;
1312 wire [7:0] libresocsim_csrbank5_load0_w;
1313 wire libresocsim_csrbank5_reload3_re;
1314 wire [7:0] libresocsim_csrbank5_reload3_r;
1315 wire libresocsim_csrbank5_reload3_we;
1316 wire [7:0] libresocsim_csrbank5_reload3_w;
1317 wire libresocsim_csrbank5_reload2_re;
1318 wire [7:0] libresocsim_csrbank5_reload2_r;
1319 wire libresocsim_csrbank5_reload2_we;
1320 wire [7:0] libresocsim_csrbank5_reload2_w;
1321 wire libresocsim_csrbank5_reload1_re;
1322 wire [7:0] libresocsim_csrbank5_reload1_r;
1323 wire libresocsim_csrbank5_reload1_we;
1324 wire [7:0] libresocsim_csrbank5_reload1_w;
1325 wire libresocsim_csrbank5_reload0_re;
1326 wire [7:0] libresocsim_csrbank5_reload0_r;
1327 wire libresocsim_csrbank5_reload0_we;
1328 wire [7:0] libresocsim_csrbank5_reload0_w;
1329 wire libresocsim_csrbank5_en0_re;
1330 wire libresocsim_csrbank5_en0_r;
1331 wire libresocsim_csrbank5_en0_we;
1332 wire libresocsim_csrbank5_en0_w;
1333 wire libresocsim_csrbank5_update_value0_re;
1334 wire libresocsim_csrbank5_update_value0_r;
1335 wire libresocsim_csrbank5_update_value0_we;
1336 wire libresocsim_csrbank5_update_value0_w;
1337 wire libresocsim_csrbank5_value3_re;
1338 wire [7:0] libresocsim_csrbank5_value3_r;
1339 wire libresocsim_csrbank5_value3_we;
1340 wire [7:0] libresocsim_csrbank5_value3_w;
1341 wire libresocsim_csrbank5_value2_re;
1342 wire [7:0] libresocsim_csrbank5_value2_r;
1343 wire libresocsim_csrbank5_value2_we;
1344 wire [7:0] libresocsim_csrbank5_value2_w;
1345 wire libresocsim_csrbank5_value1_re;
1346 wire [7:0] libresocsim_csrbank5_value1_r;
1347 wire libresocsim_csrbank5_value1_we;
1348 wire [7:0] libresocsim_csrbank5_value1_w;
1349 wire libresocsim_csrbank5_value0_re;
1350 wire [7:0] libresocsim_csrbank5_value0_r;
1351 wire libresocsim_csrbank5_value0_we;
1352 wire [7:0] libresocsim_csrbank5_value0_w;
1353 wire libresocsim_csrbank5_ev_enable0_re;
1354 wire libresocsim_csrbank5_ev_enable0_r;
1355 wire libresocsim_csrbank5_ev_enable0_we;
1356 wire libresocsim_csrbank5_ev_enable0_w;
1357 wire libresocsim_csrbank5_sel;
1358 wire [12:0] libresocsim_interface6_bank_bus_adr;
1359 wire libresocsim_interface6_bank_bus_we;
1360 wire [7:0] libresocsim_interface6_bank_bus_dat_w;
1361 reg [7:0] libresocsim_interface6_bank_bus_dat_r = 8'd0;
1362 wire libresocsim_csrbank6_txfull_re;
1363 wire libresocsim_csrbank6_txfull_r;
1364 wire libresocsim_csrbank6_txfull_we;
1365 wire libresocsim_csrbank6_txfull_w;
1366 wire libresocsim_csrbank6_rxempty_re;
1367 wire libresocsim_csrbank6_rxempty_r;
1368 wire libresocsim_csrbank6_rxempty_we;
1369 wire libresocsim_csrbank6_rxempty_w;
1370 wire libresocsim_csrbank6_ev_enable0_re;
1371 wire [1:0] libresocsim_csrbank6_ev_enable0_r;
1372 wire libresocsim_csrbank6_ev_enable0_we;
1373 wire [1:0] libresocsim_csrbank6_ev_enable0_w;
1374 wire libresocsim_csrbank6_txempty_re;
1375 wire libresocsim_csrbank6_txempty_r;
1376 wire libresocsim_csrbank6_txempty_we;
1377 wire libresocsim_csrbank6_txempty_w;
1378 wire libresocsim_csrbank6_rxfull_re;
1379 wire libresocsim_csrbank6_rxfull_r;
1380 wire libresocsim_csrbank6_rxfull_we;
1381 wire libresocsim_csrbank6_rxfull_w;
1382 wire libresocsim_csrbank6_sel;
1383 wire [12:0] libresocsim_interface7_bank_bus_adr;
1384 wire libresocsim_interface7_bank_bus_we;
1385 wire [7:0] libresocsim_interface7_bank_bus_dat_w;
1386 reg [7:0] libresocsim_interface7_bank_bus_dat_r = 8'd0;
1387 wire libresocsim_csrbank7_tuning_word3_re;
1388 wire [7:0] libresocsim_csrbank7_tuning_word3_r;
1389 wire libresocsim_csrbank7_tuning_word3_we;
1390 wire [7:0] libresocsim_csrbank7_tuning_word3_w;
1391 wire libresocsim_csrbank7_tuning_word2_re;
1392 wire [7:0] libresocsim_csrbank7_tuning_word2_r;
1393 wire libresocsim_csrbank7_tuning_word2_we;
1394 wire [7:0] libresocsim_csrbank7_tuning_word2_w;
1395 wire libresocsim_csrbank7_tuning_word1_re;
1396 wire [7:0] libresocsim_csrbank7_tuning_word1_r;
1397 wire libresocsim_csrbank7_tuning_word1_we;
1398 wire [7:0] libresocsim_csrbank7_tuning_word1_w;
1399 wire libresocsim_csrbank7_tuning_word0_re;
1400 wire [7:0] libresocsim_csrbank7_tuning_word0_r;
1401 wire libresocsim_csrbank7_tuning_word0_we;
1402 wire [7:0] libresocsim_csrbank7_tuning_word0_w;
1403 wire libresocsim_csrbank7_sel;
1404 wire [12:0] libresocsim_csr_interconnect_adr;
1405 wire libresocsim_csr_interconnect_we;
1406 wire [7:0] libresocsim_csr_interconnect_dat_w;
1407 wire [7:0] libresocsim_csr_interconnect_dat_r;
1408 reg [1:0] libresocsim_state = 2'd0;
1409 reg [1:0] libresocsim_next_state = 2'd0;
1410 reg [7:0] libresocsim_libresocsim_dat_w_libresocsim_next_value0 = 8'd0;
1411 reg libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 = 1'd0;
1412 reg [12:0] libresocsim_libresocsim_adr_libresocsim_next_value1 = 13'd0;
1413 reg libresocsim_libresocsim_adr_libresocsim_next_value_ce1 = 1'd0;
1414 reg libresocsim_libresocsim_we_libresocsim_next_value2 = 1'd0;
1415 reg libresocsim_libresocsim_we_libresocsim_next_value_ce2 = 1'd0;
1416 reg rhs_array_muxed0 = 1'd0;
1417 reg [12:0] rhs_array_muxed1 = 13'd0;
1418 reg [1:0] rhs_array_muxed2 = 2'd0;
1419 reg rhs_array_muxed3 = 1'd0;
1420 reg rhs_array_muxed4 = 1'd0;
1421 reg rhs_array_muxed5 = 1'd0;
1422 reg t_array_muxed0 = 1'd0;
1423 reg t_array_muxed1 = 1'd0;
1424 reg t_array_muxed2 = 1'd0;
1425 reg rhs_array_muxed6 = 1'd0;
1426 reg [12:0] rhs_array_muxed7 = 13'd0;
1427 reg [1:0] rhs_array_muxed8 = 2'd0;
1428 reg rhs_array_muxed9 = 1'd0;
1429 reg rhs_array_muxed10 = 1'd0;
1430 reg rhs_array_muxed11 = 1'd0;
1431 reg t_array_muxed3 = 1'd0;
1432 reg t_array_muxed4 = 1'd0;
1433 reg t_array_muxed5 = 1'd0;
1434 reg [21:0] rhs_array_muxed12 = 22'd0;
1435 reg rhs_array_muxed13 = 1'd0;
1436 reg rhs_array_muxed14 = 1'd0;
1437 reg [21:0] rhs_array_muxed15 = 22'd0;
1438 reg rhs_array_muxed16 = 1'd0;
1439 reg rhs_array_muxed17 = 1'd0;
1440 reg [21:0] rhs_array_muxed18 = 22'd0;
1441 reg rhs_array_muxed19 = 1'd0;
1442 reg rhs_array_muxed20 = 1'd0;
1443 reg [21:0] rhs_array_muxed21 = 22'd0;
1444 reg rhs_array_muxed22 = 1'd0;
1445 reg rhs_array_muxed23 = 1'd0;
1446 reg [29:0] rhs_array_muxed24 = 30'd0;
1447 reg [31:0] rhs_array_muxed25 = 32'd0;
1448 reg [3:0] rhs_array_muxed26 = 4'd0;
1449 reg rhs_array_muxed27 = 1'd0;
1450 reg rhs_array_muxed28 = 1'd0;
1451 reg rhs_array_muxed29 = 1'd0;
1452 reg [2:0] rhs_array_muxed30 = 3'd0;
1453 reg [1:0] rhs_array_muxed31 = 2'd0;
1454 reg [1:0] array_muxed0 = 2'd0;
1455 reg [12:0] array_muxed1 = 13'd0;
1456 reg array_muxed2 = 1'd0;
1457 reg array_muxed3 = 1'd0;
1458 reg array_muxed4 = 1'd0;
1459 reg array_muxed5 = 1'd0;
1460 reg array_muxed6 = 1'd0;
1461 wire sdrio_clk;
1462 wire sdrio_clk_1;
1463 wire sdrio_clk_2;
1464 wire sdrio_clk_3;
1465 wire sdrio_clk_4;
1466 wire sdrio_clk_5;
1467 wire sdrio_clk_6;
1468 wire sdrio_clk_7;
1469 wire sdrio_clk_8;
1470 wire sdrio_clk_9;
1471 wire sdrio_clk_10;
1472 wire sdrio_clk_11;
1473 wire sdrio_clk_12;
1474 wire sdrio_clk_13;
1475 wire sdrio_clk_14;
1476 wire sdrio_clk_15;
1477 wire sdrio_clk_16;
1478 wire sdrio_clk_17;
1479 wire sdrio_clk_18;
1480 wire sdrio_clk_19;
1481 wire sdrio_clk_20;
1482 wire sdrio_clk_21;
1483 wire sdrio_clk_22;
1484 wire sdrio_clk_23;
1485 wire sdrio_clk_24;
1486 wire sdrio_clk_25;
1487 wire sdrio_clk_26;
1488 wire sdrio_clk_27;
1489 wire sdrio_clk_28;
1490 wire sdrio_clk_29;
1491 wire sdrio_clk_30;
1492 wire sdrio_clk_31;
1493 wire sdrio_clk_32;
1494 wire sdrio_clk_33;
1495 wire sdrio_clk_34;
1496 wire sdrio_clk_35;
1497 wire sdrio_clk_36;
1498 wire sdrio_clk_37;
1499 wire sdrio_clk_38;
1500 wire sdrio_clk_39;
1501 wire sdrio_clk_40;
1502 wire sdrio_clk_41;
1503 wire sdrio_clk_42;
1504 wire sdrio_clk_43;
1505 wire sdrio_clk_44;
1506 wire sdrio_clk_45;
1507 wire sdrio_clk_46;
1508 wire sdrio_clk_47;
1509 wire sdrio_clk_48;
1510 wire sdrio_clk_49;
1511 wire sdrio_clk_50;
1512 wire sdrio_clk_51;
1513 wire sdrio_clk_52;
1514 wire sdrio_clk_53;
1515 wire sdrio_clk_54;
1516 wire sdrio_clk_55;
1517 wire sdrio_clk_56;
1518 wire sdrio_clk_57;
1519 wire sdrio_clk_58;
1520 wire sdrio_clk_59;
1521 wire sdrio_clk_60;
1522 wire sdrio_clk_61;
1523 wire sdrio_clk_62;
1524 wire sdrio_clk_63;
1525 wire sdrio_clk_64;
1526 wire sdrio_clk_65;
1527 wire sdrio_clk_66;
1528 wire sdrio_clk_67;
1529 wire sdrio_clk_68;
1530 wire sdrio_clk_69;
1531 wire sdrio_clk_70;
1532 (* no_retiming = "true" *) reg regs0 = 1'd0;
1533 (* no_retiming = "true" *) reg regs1 = 1'd0;
1534 wire sdrio_clk_71;
1535 wire sdrio_clk_72;
1536 wire sdrio_clk_73;
1537 wire sdrio_clk_74;
1538 wire sdrio_clk_75;
1539 wire sdrio_clk_76;
1540 wire sdrio_clk_77;
1541 wire sdrio_clk_78;
1542 wire sdrio_clk_79;
1543 wire sdrio_clk_80;
1544 wire sdrio_clk_81;
1545 wire sdrio_clk_82;
1546 wire sdrio_clk_83;
1547 wire sdrio_clk_84;
1548 wire sdrio_clk_85;
1549 wire sdrio_clk_86;
1550 wire sdrio_clk_87;
1551 wire sdrio_clk_88;
1552 wire sdrio_clk_89;
1553 wire sdrio_clk_90;
1554 wire sdrio_clk_91;
1555 wire sdrio_clk_92;
1556 wire sdrio_clk_93;
1557 wire sdrio_clk_94;
1558 wire sdrio_clk_95;
1559 wire sdrio_clk_96;
1560 wire sdrio_clk_97;
1561 wire sdrio_clk_98;
1562 wire sdrio_clk_99;
1563 wire sdrio_clk_100;
1564 wire sdrio_clk_101;
1565 wire sdrio_clk_102;
1566 wire sdrio_clk_103;
1567 wire sdrio_clk_104;
1568 wire sdrio_clk_105;
1569 wire sdrio_clk_106;
1570 wire sdrio_clk_107;
1571 wire sdrio_clk_108;
1572 wire sdrio_clk_109;
1573 wire sdrio_clk_110;
1574 wire sdrio_clk_111;
1575 wire sdrio_clk_112;
1576 wire sdrio_clk_113;
1577 wire sdrio_clk_114;
1578 wire sdrio_clk_115;
1579 wire sdrio_clk_116;
1580 wire sdrio_clk_117;
1581 wire sdrio_clk_118;
1582
1583 assign libresocsim_libresoc_reset = libresocsim_reset;
1584 assign libresocsim_libresoc_clk_sel = sys_clksel_i;
1585 assign sys_pll_testout_o = libresocsim_libresoc_pll_test_o;
1586 assign sys_pll_vco_o = libresocsim_libresoc_pll_vco_o;
1587 always @(*) begin
1588         eint_tmp <= 3'd0;
1589         eint_tmp[0] <= libresocsim_libresoc_constraintmanager_eint_0;
1590         eint_tmp[1] <= libresocsim_libresoc_constraintmanager_eint_1;
1591         eint_tmp[2] <= libresocsim_libresoc_constraintmanager_eint_2;
1592 end
1593 assign libresocsim_libresoc_jtag_tck = jtag_tck;
1594 assign libresocsim_libresoc_jtag_tms = jtag_tms;
1595 assign libresocsim_libresoc_jtag_tdi = jtag_tdi;
1596 assign jtag_tdo = libresocsim_libresoc_jtag_tdo;
1597 assign nc_1 = nc;
1598 assign libresocsim_bus_error = libresocsim_error;
1599 always @(*) begin
1600         libresocsim_libresoc_interrupt <= 16'd0;
1601         libresocsim_libresoc_interrupt[13] <= eint_tmp[0];
1602         libresocsim_libresoc_interrupt[14] <= eint_tmp[1];
1603         libresocsim_libresoc_interrupt[15] <= eint_tmp[2];
1604         libresocsim_libresoc_interrupt[0] <= libresocsim_irq;
1605         libresocsim_libresoc_interrupt[1] <= irq;
1606 end
1607 assign libresocsim_converter0_reset = (~libresocsim_libresoc_ibus_cyc);
1608 always @(*) begin
1609         libresocsim_interface0_converted_interface_dat_w <= 32'd0;
1610         case (libresocsim_converter0_counter)
1611                 1'd0: begin
1612                         libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:0];
1613                 end
1614                 1'd1: begin
1615                         libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:32];
1616                 end
1617         endcase
1618 end
1619 assign libresocsim_libresoc_ibus_dat_r = {libresocsim_interface0_converted_interface_dat_r, libresocsim_converter0_dat_r[63:32]};
1620 always @(*) begin
1621         libresocsim_interface0_converted_interface_cyc <= 1'd0;
1622         libresocsim_interface0_converted_interface_stb <= 1'd0;
1623         libresocsim_libresoc_ibus_ack <= 1'd0;
1624         subfragments_converter0_next_state <= 1'd0;
1625         libresocsim_interface0_converted_interface_we <= 1'd0;
1626         libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0;
1627         libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0;
1628         libresocsim_converter0_skip <= 1'd0;
1629         libresocsim_interface0_converted_interface_adr <= 30'd0;
1630         libresocsim_interface0_converted_interface_sel <= 4'd0;
1631         subfragments_converter0_next_state <= subfragments_converter0_state;
1632         case (subfragments_converter0_state)
1633                 1'd1: begin
1634                         libresocsim_interface0_converted_interface_adr <= {libresocsim_libresoc_ibus_adr, libresocsim_converter0_counter};
1635                         case (libresocsim_converter0_counter)
1636                                 1'd0: begin
1637                                         libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:0];
1638                                 end
1639                                 1'd1: begin
1640                                         libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:4];
1641                                 end
1642                         endcase
1643                         if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin
1644                                 libresocsim_converter0_skip <= (libresocsim_interface0_converted_interface_sel == 1'd0);
1645                                 libresocsim_interface0_converted_interface_we <= libresocsim_libresoc_ibus_we;
1646                                 libresocsim_interface0_converted_interface_cyc <= (~libresocsim_converter0_skip);
1647                                 libresocsim_interface0_converted_interface_stb <= (~libresocsim_converter0_skip);
1648                                 if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin
1649                                         libresocsim_converter0_counter_subfragments_converter0_next_value <= (libresocsim_converter0_counter + 1'd1);
1650                                         libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1;
1651                                         if ((libresocsim_converter0_counter == 1'd1)) begin
1652                                                 libresocsim_libresoc_ibus_ack <= 1'd1;
1653                                                 subfragments_converter0_next_state <= 1'd0;
1654                                         end
1655                                 end
1656                         end
1657                 end
1658                 default: begin
1659                         libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0;
1660                         libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1;
1661                         if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin
1662                                 subfragments_converter0_next_state <= 1'd1;
1663                         end
1664                 end
1665         endcase
1666 end
1667 assign libresocsim_converter1_reset = (~libresocsim_libresoc_dbus_cyc);
1668 always @(*) begin
1669         libresocsim_interface1_converted_interface_dat_w <= 32'd0;
1670         case (libresocsim_converter1_counter)
1671                 1'd0: begin
1672                         libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:0];
1673                 end
1674                 1'd1: begin
1675                         libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:32];
1676                 end
1677         endcase
1678 end
1679 assign libresocsim_libresoc_dbus_dat_r = {libresocsim_interface1_converted_interface_dat_r, libresocsim_converter1_dat_r[63:32]};
1680 always @(*) begin
1681         subfragments_converter1_next_state <= 1'd0;
1682         libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0;
1683         libresocsim_converter1_skip <= 1'd0;
1684         libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0;
1685         libresocsim_libresoc_dbus_ack <= 1'd0;
1686         libresocsim_interface1_converted_interface_adr <= 30'd0;
1687         libresocsim_interface1_converted_interface_sel <= 4'd0;
1688         libresocsim_interface1_converted_interface_cyc <= 1'd0;
1689         libresocsim_interface1_converted_interface_stb <= 1'd0;
1690         libresocsim_interface1_converted_interface_we <= 1'd0;
1691         subfragments_converter1_next_state <= subfragments_converter1_state;
1692         case (subfragments_converter1_state)
1693                 1'd1: begin
1694                         libresocsim_interface1_converted_interface_adr <= {libresocsim_libresoc_dbus_adr, libresocsim_converter1_counter};
1695                         case (libresocsim_converter1_counter)
1696                                 1'd0: begin
1697                                         libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:0];
1698                                 end
1699                                 1'd1: begin
1700                                         libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:4];
1701                                 end
1702                         endcase
1703                         if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin
1704                                 libresocsim_converter1_skip <= (libresocsim_interface1_converted_interface_sel == 1'd0);
1705                                 libresocsim_interface1_converted_interface_we <= libresocsim_libresoc_dbus_we;
1706                                 libresocsim_interface1_converted_interface_cyc <= (~libresocsim_converter1_skip);
1707                                 libresocsim_interface1_converted_interface_stb <= (~libresocsim_converter1_skip);
1708                                 if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin
1709                                         libresocsim_converter1_counter_subfragments_converter1_next_value <= (libresocsim_converter1_counter + 1'd1);
1710                                         libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1;
1711                                         if ((libresocsim_converter1_counter == 1'd1)) begin
1712                                                 libresocsim_libresoc_dbus_ack <= 1'd1;
1713                                                 subfragments_converter1_next_state <= 1'd0;
1714                                         end
1715                                 end
1716                         end
1717                 end
1718                 default: begin
1719                         libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0;
1720                         libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1;
1721                         if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin
1722                                 subfragments_converter1_next_state <= 1'd1;
1723                         end
1724                 end
1725         endcase
1726 end
1727 assign libresocsim_libresoc_interface0_cyc = interface0_converted_interface_cyc;
1728 assign libresocsim_libresoc_interface0_stb = interface0_converted_interface_stb;
1729 assign interface0_converted_interface_ack = libresocsim_libresoc_interface0_ack;
1730 assign libresocsim_libresoc_interface0_we = interface0_converted_interface_we;
1731 assign libresocsim_libresoc_interface0_cti = interface0_converted_interface_cti;
1732 assign libresocsim_libresoc_interface0_bte = interface0_converted_interface_bte;
1733 assign interface0_converted_interface_err = libresocsim_libresoc_interface0_err;
1734 always @(*) begin
1735         libresocsim_libresoc_interface0_adr <= 29'd0;
1736         libresocsim_libresoc_interface0_dat_w <= 64'd0;
1737         libresocsim_libresoc_interface0_sel <= 8'd0;
1738         interface0_converted_interface_dat_r <= 32'd0;
1739         case (interface0_converted_interface_adr[0])
1740                 1'd0: begin
1741                         libresocsim_libresoc_interface0_adr <= interface0_converted_interface_adr[29:1];
1742                         libresocsim_libresoc_interface0_sel[3:0] <= 4'd15;
1743                         libresocsim_libresoc_interface0_dat_w[31:0] <= interface0_converted_interface_dat_w;
1744                         interface0_converted_interface_dat_r <= libresocsim_libresoc_interface0_dat_r[31:0];
1745                 end
1746                 1'd1: begin
1747                         libresocsim_libresoc_interface0_adr <= interface0_converted_interface_adr[29:1];
1748                         libresocsim_libresoc_interface0_sel[7:4] <= 4'd15;
1749                         libresocsim_libresoc_interface0_dat_w[63:32] <= interface0_converted_interface_dat_w;
1750                         interface0_converted_interface_dat_r <= libresocsim_libresoc_interface0_dat_r[63:32];
1751                 end
1752         endcase
1753 end
1754 assign libresocsim_libresoc_interface1_cyc = interface1_converted_interface_cyc;
1755 assign libresocsim_libresoc_interface1_stb = interface1_converted_interface_stb;
1756 assign interface1_converted_interface_ack = libresocsim_libresoc_interface1_ack;
1757 assign libresocsim_libresoc_interface1_we = interface1_converted_interface_we;
1758 assign libresocsim_libresoc_interface1_cti = interface1_converted_interface_cti;
1759 assign libresocsim_libresoc_interface1_bte = interface1_converted_interface_bte;
1760 assign interface1_converted_interface_err = libresocsim_libresoc_interface1_err;
1761 always @(*) begin
1762         libresocsim_libresoc_interface1_dat_w <= 64'd0;
1763         libresocsim_libresoc_interface1_sel <= 8'd0;
1764         interface1_converted_interface_dat_r <= 32'd0;
1765         libresocsim_libresoc_interface1_adr <= 29'd0;
1766         case (interface1_converted_interface_adr[0])
1767                 1'd0: begin
1768                         libresocsim_libresoc_interface1_adr <= interface1_converted_interface_adr[29:1];
1769                         libresocsim_libresoc_interface1_sel[3:0] <= 4'd15;
1770                         libresocsim_libresoc_interface1_dat_w[31:0] <= interface1_converted_interface_dat_w;
1771                         interface1_converted_interface_dat_r <= libresocsim_libresoc_interface1_dat_r[31:0];
1772                 end
1773                 1'd1: begin
1774                         libresocsim_libresoc_interface1_adr <= interface1_converted_interface_adr[29:1];
1775                         libresocsim_libresoc_interface1_sel[7:4] <= 4'd15;
1776                         libresocsim_libresoc_interface1_dat_w[63:32] <= interface1_converted_interface_dat_w;
1777                         interface1_converted_interface_dat_r <= libresocsim_libresoc_interface1_dat_r[63:32];
1778                 end
1779         endcase
1780 end
1781 assign libresocsim_libresoc_interface2_cyc = interface2_converted_interface_cyc;
1782 assign libresocsim_libresoc_interface2_stb = interface2_converted_interface_stb;
1783 assign interface2_converted_interface_ack = libresocsim_libresoc_interface2_ack;
1784 assign libresocsim_libresoc_interface2_we = interface2_converted_interface_we;
1785 assign libresocsim_libresoc_interface2_cti = interface2_converted_interface_cti;
1786 assign libresocsim_libresoc_interface2_bte = interface2_converted_interface_bte;
1787 assign interface2_converted_interface_err = libresocsim_libresoc_interface2_err;
1788 always @(*) begin
1789         interface2_converted_interface_dat_r <= 32'd0;
1790         libresocsim_libresoc_interface2_sel <= 8'd0;
1791         libresocsim_libresoc_interface2_adr <= 29'd0;
1792         libresocsim_libresoc_interface2_dat_w <= 64'd0;
1793         case (interface2_converted_interface_adr[0])
1794                 1'd0: begin
1795                         libresocsim_libresoc_interface2_adr <= interface2_converted_interface_adr[29:1];
1796                         libresocsim_libresoc_interface2_sel[3:0] <= 4'd15;
1797                         libresocsim_libresoc_interface2_dat_w[31:0] <= interface2_converted_interface_dat_w;
1798                         interface2_converted_interface_dat_r <= libresocsim_libresoc_interface2_dat_r[31:0];
1799                 end
1800                 1'd1: begin
1801                         libresocsim_libresoc_interface2_adr <= interface2_converted_interface_adr[29:1];
1802                         libresocsim_libresoc_interface2_sel[7:4] <= 4'd15;
1803                         libresocsim_libresoc_interface2_dat_w[63:32] <= interface2_converted_interface_dat_w;
1804                         interface2_converted_interface_dat_r <= libresocsim_libresoc_interface2_dat_r[63:32];
1805                 end
1806         endcase
1807 end
1808 assign libresocsim_libresoc_interface3_cyc = interface3_converted_interface_cyc;
1809 assign libresocsim_libresoc_interface3_stb = interface3_converted_interface_stb;
1810 assign interface3_converted_interface_ack = libresocsim_libresoc_interface3_ack;
1811 assign libresocsim_libresoc_interface3_we = interface3_converted_interface_we;
1812 assign libresocsim_libresoc_interface3_cti = interface3_converted_interface_cti;
1813 assign libresocsim_libresoc_interface3_bte = interface3_converted_interface_bte;
1814 assign interface3_converted_interface_err = libresocsim_libresoc_interface3_err;
1815 always @(*) begin
1816         libresocsim_libresoc_interface3_sel <= 8'd0;
1817         libresocsim_libresoc_interface3_adr <= 29'd0;
1818         interface3_converted_interface_dat_r <= 32'd0;
1819         libresocsim_libresoc_interface3_dat_w <= 64'd0;
1820         case (interface3_converted_interface_adr[0])
1821                 1'd0: begin
1822                         libresocsim_libresoc_interface3_adr <= interface3_converted_interface_adr[29:1];
1823                         libresocsim_libresoc_interface3_sel[3:0] <= 4'd15;
1824                         libresocsim_libresoc_interface3_dat_w[31:0] <= interface3_converted_interface_dat_w;
1825                         interface3_converted_interface_dat_r <= libresocsim_libresoc_interface3_dat_r[31:0];
1826                 end
1827                 1'd1: begin
1828                         libresocsim_libresoc_interface3_adr <= interface3_converted_interface_adr[29:1];
1829                         libresocsim_libresoc_interface3_sel[7:4] <= 4'd15;
1830                         libresocsim_libresoc_interface3_dat_w[63:32] <= interface3_converted_interface_dat_w;
1831                         interface3_converted_interface_dat_r <= libresocsim_libresoc_interface3_dat_r[63:32];
1832                 end
1833         endcase
1834 end
1835 assign libresocsim_reset = libresocsim_reset_re;
1836 assign libresocsim_bus_errors_status = libresocsim_bus_errors;
1837 always @(*) begin
1838         libresocsim_we <= 4'd0;
1839         libresocsim_we[0] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[0]);
1840         libresocsim_we[1] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[1]);
1841         libresocsim_we[2] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[2]);
1842         libresocsim_we[3] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[3]);
1843 end
1844 assign libresocsim_adr = libresocsim_ram_bus_adr[4:0];
1845 assign libresocsim_ram_bus_dat_r = libresocsim_dat_r;
1846 assign libresocsim_dat_w = libresocsim_ram_bus_dat_w;
1847 assign libresocsim_zero_trigger = (libresocsim_value != 1'd0);
1848 assign libresocsim_eventmanager_status_w = libresocsim_zero_status;
1849 always @(*) begin
1850         libresocsim_zero_clear <= 1'd0;
1851         if ((libresocsim_eventmanager_pending_re & libresocsim_eventmanager_pending_r)) begin
1852                 libresocsim_zero_clear <= 1'd1;
1853         end
1854 end
1855 assign libresocsim_eventmanager_pending_w = libresocsim_zero_pending;
1856 assign libresocsim_irq = (libresocsim_eventmanager_pending_w & libresocsim_eventmanager_storage);
1857 assign libresocsim_zero_status = libresocsim_zero_trigger;
1858 always @(*) begin
1859         ram_we <= 4'd0;
1860         ram_we[0] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[0]);
1861         ram_we[1] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[1]);
1862         ram_we[2] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[2]);
1863         ram_we[3] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[3]);
1864 end
1865 assign ram_adr = ram_bus_ram_bus_adr[4:0];
1866 assign ram_bus_ram_bus_dat_r = ram_dat_r;
1867 assign ram_dat_w = ram_bus_ram_bus_dat_w;
1868 assign sys_clk_1 = sys_clk_0;
1869 assign por_clk = sys_clk_0;
1870 assign sys_rst_1 = int_rst;
1871 assign dfi_p0_address = sdram_master_p0_address;
1872 assign dfi_p0_bank = sdram_master_p0_bank;
1873 assign dfi_p0_cas_n = sdram_master_p0_cas_n;
1874 assign dfi_p0_cs_n = sdram_master_p0_cs_n;
1875 assign dfi_p0_ras_n = sdram_master_p0_ras_n;
1876 assign dfi_p0_we_n = sdram_master_p0_we_n;
1877 assign dfi_p0_cke = sdram_master_p0_cke;
1878 assign dfi_p0_odt = sdram_master_p0_odt;
1879 assign dfi_p0_reset_n = sdram_master_p0_reset_n;
1880 assign dfi_p0_act_n = sdram_master_p0_act_n;
1881 assign dfi_p0_wrdata = sdram_master_p0_wrdata;
1882 assign dfi_p0_wrdata_en = sdram_master_p0_wrdata_en;
1883 assign dfi_p0_wrdata_mask = sdram_master_p0_wrdata_mask;
1884 assign dfi_p0_rddata_en = sdram_master_p0_rddata_en;
1885 assign sdram_master_p0_rddata = dfi_p0_rddata;
1886 assign sdram_master_p0_rddata_valid = dfi_p0_rddata_valid;
1887 assign sdram_slave_p0_address = sdram_dfi_p0_address;
1888 assign sdram_slave_p0_bank = sdram_dfi_p0_bank;
1889 assign sdram_slave_p0_cas_n = sdram_dfi_p0_cas_n;
1890 assign sdram_slave_p0_cs_n = sdram_dfi_p0_cs_n;
1891 assign sdram_slave_p0_ras_n = sdram_dfi_p0_ras_n;
1892 assign sdram_slave_p0_we_n = sdram_dfi_p0_we_n;
1893 assign sdram_slave_p0_cke = sdram_dfi_p0_cke;
1894 assign sdram_slave_p0_odt = sdram_dfi_p0_odt;
1895 assign sdram_slave_p0_reset_n = sdram_dfi_p0_reset_n;
1896 assign sdram_slave_p0_act_n = sdram_dfi_p0_act_n;
1897 assign sdram_slave_p0_wrdata = sdram_dfi_p0_wrdata;
1898 assign sdram_slave_p0_wrdata_en = sdram_dfi_p0_wrdata_en;
1899 assign sdram_slave_p0_wrdata_mask = sdram_dfi_p0_wrdata_mask;
1900 assign sdram_slave_p0_rddata_en = sdram_dfi_p0_rddata_en;
1901 assign sdram_dfi_p0_rddata = sdram_slave_p0_rddata;
1902 assign sdram_dfi_p0_rddata_valid = sdram_slave_p0_rddata_valid;
1903 always @(*) begin
1904         sdram_master_p0_wrdata_mask <= 2'd0;
1905         sdram_master_p0_rddata_en <= 1'd0;
1906         sdram_master_p0_act_n <= 1'd1;
1907         sdram_master_p0_wrdata <= 16'd0;
1908         sdram_slave_p0_rddata <= 16'd0;
1909         sdram_slave_p0_rddata_valid <= 1'd0;
1910         sdram_master_p0_address <= 13'd0;
1911         sdram_master_p0_bank <= 2'd0;
1912         sdram_master_p0_cas_n <= 1'd1;
1913         sdram_master_p0_cs_n <= 1'd1;
1914         sdram_master_p0_ras_n <= 1'd1;
1915         sdram_master_p0_we_n <= 1'd1;
1916         sdram_master_p0_cke <= 1'd0;
1917         sdram_master_p0_odt <= 1'd0;
1918         sdram_master_p0_reset_n <= 1'd0;
1919         sdram_inti_p0_rddata <= 16'd0;
1920         sdram_inti_p0_rddata_valid <= 1'd0;
1921         sdram_master_p0_wrdata_en <= 1'd0;
1922         if (sdram_sel) begin
1923                 sdram_master_p0_address <= sdram_slave_p0_address;
1924                 sdram_master_p0_bank <= sdram_slave_p0_bank;
1925                 sdram_master_p0_cas_n <= sdram_slave_p0_cas_n;
1926                 sdram_master_p0_cs_n <= sdram_slave_p0_cs_n;
1927                 sdram_master_p0_ras_n <= sdram_slave_p0_ras_n;
1928                 sdram_master_p0_we_n <= sdram_slave_p0_we_n;
1929                 sdram_master_p0_cke <= sdram_slave_p0_cke;
1930                 sdram_master_p0_odt <= sdram_slave_p0_odt;
1931                 sdram_master_p0_reset_n <= sdram_slave_p0_reset_n;
1932                 sdram_master_p0_act_n <= sdram_slave_p0_act_n;
1933                 sdram_master_p0_wrdata <= sdram_slave_p0_wrdata;
1934                 sdram_master_p0_wrdata_en <= sdram_slave_p0_wrdata_en;
1935                 sdram_master_p0_wrdata_mask <= sdram_slave_p0_wrdata_mask;
1936                 sdram_master_p0_rddata_en <= sdram_slave_p0_rddata_en;
1937                 sdram_slave_p0_rddata <= sdram_master_p0_rddata;
1938                 sdram_slave_p0_rddata_valid <= sdram_master_p0_rddata_valid;
1939         end else begin
1940                 sdram_master_p0_address <= sdram_inti_p0_address;
1941                 sdram_master_p0_bank <= sdram_inti_p0_bank;
1942                 sdram_master_p0_cas_n <= sdram_inti_p0_cas_n;
1943                 sdram_master_p0_cs_n <= sdram_inti_p0_cs_n;
1944                 sdram_master_p0_ras_n <= sdram_inti_p0_ras_n;
1945                 sdram_master_p0_we_n <= sdram_inti_p0_we_n;
1946                 sdram_master_p0_cke <= sdram_inti_p0_cke;
1947                 sdram_master_p0_odt <= sdram_inti_p0_odt;
1948                 sdram_master_p0_reset_n <= sdram_inti_p0_reset_n;
1949                 sdram_master_p0_act_n <= sdram_inti_p0_act_n;
1950                 sdram_master_p0_wrdata <= sdram_inti_p0_wrdata;
1951                 sdram_master_p0_wrdata_en <= sdram_inti_p0_wrdata_en;
1952                 sdram_master_p0_wrdata_mask <= sdram_inti_p0_wrdata_mask;
1953                 sdram_master_p0_rddata_en <= sdram_inti_p0_rddata_en;
1954                 sdram_inti_p0_rddata <= sdram_master_p0_rddata;
1955                 sdram_inti_p0_rddata_valid <= sdram_master_p0_rddata_valid;
1956         end
1957 end
1958 assign sdram_inti_p0_cke = sdram_cke_1;
1959 assign sdram_inti_p0_odt = sdram_odt;
1960 assign sdram_inti_p0_reset_n = sdram_reset_n;
1961 always @(*) begin
1962         sdram_inti_p0_we_n <= 1'd1;
1963         sdram_inti_p0_cas_n <= 1'd1;
1964         sdram_inti_p0_cs_n <= 1'd1;
1965         sdram_inti_p0_ras_n <= 1'd1;
1966         if (sdram_command_issue_re) begin
1967                 sdram_inti_p0_cs_n <= {1{(~sdram_command_storage[0])}};
1968                 sdram_inti_p0_we_n <= (~sdram_command_storage[1]);
1969                 sdram_inti_p0_cas_n <= (~sdram_command_storage[2]);
1970                 sdram_inti_p0_ras_n <= (~sdram_command_storage[3]);
1971         end else begin
1972                 sdram_inti_p0_cs_n <= {1{1'd1}};
1973                 sdram_inti_p0_we_n <= 1'd1;
1974                 sdram_inti_p0_cas_n <= 1'd1;
1975                 sdram_inti_p0_ras_n <= 1'd1;
1976         end
1977 end
1978 assign sdram_inti_p0_address = sdram_address_storage;
1979 assign sdram_inti_p0_bank = sdram_baddress_storage;
1980 assign sdram_inti_p0_wrdata_en = (sdram_command_issue_re & sdram_command_storage[4]);
1981 assign sdram_inti_p0_rddata_en = (sdram_command_issue_re & sdram_command_storage[5]);
1982 assign sdram_inti_p0_wrdata = sdram_wrdata_storage;
1983 assign sdram_inti_p0_wrdata_mask = 1'd0;
1984 assign sdram_bankmachine0_req_valid = sdram_interface_bank0_valid;
1985 assign sdram_interface_bank0_ready = sdram_bankmachine0_req_ready;
1986 assign sdram_bankmachine0_req_we = sdram_interface_bank0_we;
1987 assign sdram_bankmachine0_req_addr = sdram_interface_bank0_addr;
1988 assign sdram_interface_bank0_lock = sdram_bankmachine0_req_lock;
1989 assign sdram_interface_bank0_wdata_ready = sdram_bankmachine0_req_wdata_ready;
1990 assign sdram_interface_bank0_rdata_valid = sdram_bankmachine0_req_rdata_valid;
1991 assign sdram_bankmachine1_req_valid = sdram_interface_bank1_valid;
1992 assign sdram_interface_bank1_ready = sdram_bankmachine1_req_ready;
1993 assign sdram_bankmachine1_req_we = sdram_interface_bank1_we;
1994 assign sdram_bankmachine1_req_addr = sdram_interface_bank1_addr;
1995 assign sdram_interface_bank1_lock = sdram_bankmachine1_req_lock;
1996 assign sdram_interface_bank1_wdata_ready = sdram_bankmachine1_req_wdata_ready;
1997 assign sdram_interface_bank1_rdata_valid = sdram_bankmachine1_req_rdata_valid;
1998 assign sdram_bankmachine2_req_valid = sdram_interface_bank2_valid;
1999 assign sdram_interface_bank2_ready = sdram_bankmachine2_req_ready;
2000 assign sdram_bankmachine2_req_we = sdram_interface_bank2_we;
2001 assign sdram_bankmachine2_req_addr = sdram_interface_bank2_addr;
2002 assign sdram_interface_bank2_lock = sdram_bankmachine2_req_lock;
2003 assign sdram_interface_bank2_wdata_ready = sdram_bankmachine2_req_wdata_ready;
2004 assign sdram_interface_bank2_rdata_valid = sdram_bankmachine2_req_rdata_valid;
2005 assign sdram_bankmachine3_req_valid = sdram_interface_bank3_valid;
2006 assign sdram_interface_bank3_ready = sdram_bankmachine3_req_ready;
2007 assign sdram_bankmachine3_req_we = sdram_interface_bank3_we;
2008 assign sdram_bankmachine3_req_addr = sdram_interface_bank3_addr;
2009 assign sdram_interface_bank3_lock = sdram_bankmachine3_req_lock;
2010 assign sdram_interface_bank3_wdata_ready = sdram_bankmachine3_req_wdata_ready;
2011 assign sdram_interface_bank3_rdata_valid = sdram_bankmachine3_req_rdata_valid;
2012 assign sdram_timer_wait = (~sdram_timer_done0);
2013 assign sdram_postponer_req_i = sdram_timer_done0;
2014 assign sdram_wants_refresh = sdram_postponer_req_o;
2015 assign sdram_timer_done1 = (sdram_timer_count1 == 1'd0);
2016 assign sdram_timer_done0 = sdram_timer_done1;
2017 assign sdram_timer_count0 = sdram_timer_count1;
2018 assign sdram_sequencer_start1 = (sdram_sequencer_start0 | (sdram_sequencer_count != 1'd0));
2019 assign sdram_sequencer_done0 = (sdram_sequencer_done1 & (sdram_sequencer_count == 1'd0));
2020 always @(*) begin
2021         sdram_sequencer_start0 <= 1'd0;
2022         subfragments_refresher_next_state <= 2'd0;
2023         sdram_cmd_valid <= 1'd0;
2024         sdram_cmd_last <= 1'd0;
2025         subfragments_refresher_next_state <= subfragments_refresher_state;
2026         case (subfragments_refresher_state)
2027                 1'd1: begin
2028                         sdram_cmd_valid <= 1'd1;
2029                         if (sdram_cmd_ready) begin
2030                                 sdram_sequencer_start0 <= 1'd1;
2031                                 subfragments_refresher_next_state <= 2'd2;
2032                         end
2033                 end
2034                 2'd2: begin
2035                         sdram_cmd_valid <= 1'd1;
2036                         if (sdram_sequencer_done0) begin
2037                                 sdram_cmd_valid <= 1'd0;
2038                                 sdram_cmd_last <= 1'd1;
2039                                 subfragments_refresher_next_state <= 1'd0;
2040                         end
2041                 end
2042                 default: begin
2043                         if (1'd1) begin
2044                                 if (sdram_wants_refresh) begin
2045                                         subfragments_refresher_next_state <= 1'd1;
2046                                 end
2047                         end
2048                 end
2049         endcase
2050 end
2051 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = sdram_bankmachine0_req_valid;
2052 assign sdram_bankmachine0_req_ready = sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
2053 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine0_req_we;
2054 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine0_req_addr;
2055 assign sdram_bankmachine0_cmd_buffer_sink_valid = sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
2056 assign sdram_bankmachine0_cmd_buffer_lookahead_source_ready = sdram_bankmachine0_cmd_buffer_sink_ready;
2057 assign sdram_bankmachine0_cmd_buffer_sink_first = sdram_bankmachine0_cmd_buffer_lookahead_source_first;
2058 assign sdram_bankmachine0_cmd_buffer_sink_last = sdram_bankmachine0_cmd_buffer_lookahead_source_last;
2059 assign sdram_bankmachine0_cmd_buffer_sink_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
2060 assign sdram_bankmachine0_cmd_buffer_sink_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
2061 assign sdram_bankmachine0_cmd_buffer_source_ready = (sdram_bankmachine0_req_wdata_ready | sdram_bankmachine0_req_rdata_valid);
2062 assign sdram_bankmachine0_req_lock = (sdram_bankmachine0_cmd_buffer_lookahead_source_valid | sdram_bankmachine0_cmd_buffer_source_valid);
2063 assign sdram_bankmachine0_row_hit = (sdram_bankmachine0_row == sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]);
2064 assign sdram_bankmachine0_cmd_payload_ba = 1'd0;
2065 always @(*) begin
2066         sdram_bankmachine0_cmd_payload_a <= 13'd0;
2067         if (sdram_bankmachine0_row_col_n_addr_sel) begin
2068                 sdram_bankmachine0_cmd_payload_a <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
2069         end else begin
2070                 sdram_bankmachine0_cmd_payload_a <= ((sdram_bankmachine0_auto_precharge <<< 4'd10) | {sdram_bankmachine0_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2071         end
2072 end
2073 assign sdram_bankmachine0_twtpcon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_cmd_payload_is_write);
2074 assign sdram_bankmachine0_trccon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open);
2075 assign sdram_bankmachine0_trascon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open);
2076 always @(*) begin
2077         sdram_bankmachine0_auto_precharge <= 1'd0;
2078         if ((sdram_bankmachine0_cmd_buffer_lookahead_source_valid & sdram_bankmachine0_cmd_buffer_source_valid)) begin
2079                 if ((sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9])) begin
2080                         sdram_bankmachine0_auto_precharge <= (sdram_bankmachine0_row_close == 1'd0);
2081                 end
2082         end
2083 end
2084 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
2085 assign {sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
2086 assign sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
2087 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
2088 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
2089 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
2090 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
2091 assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
2092 assign sdram_bankmachine0_cmd_buffer_lookahead_source_valid = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
2093 assign sdram_bankmachine0_cmd_buffer_lookahead_source_first = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
2094 assign sdram_bankmachine0_cmd_buffer_lookahead_source_last = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
2095 assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
2096 assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
2097 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
2098 always @(*) begin
2099         sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2100         if (sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
2101                 sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
2102         end else begin
2103                 sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine0_cmd_buffer_lookahead_produce;
2104         end
2105 end
2106 assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
2107 assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | sdram_bankmachine0_cmd_buffer_lookahead_replace));
2108 assign sdram_bankmachine0_cmd_buffer_lookahead_do_read = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
2109 assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine0_cmd_buffer_lookahead_consume;
2110 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
2111 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8);
2112 assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
2113 assign sdram_bankmachine0_cmd_buffer_sink_ready = ((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready);
2114 always @(*) begin
2115         sdram_bankmachine0_refresh_gnt <= 1'd0;
2116         sdram_bankmachine0_cmd_valid <= 1'd0;
2117         sdram_bankmachine0_row_open <= 1'd0;
2118         sdram_bankmachine0_row_close <= 1'd0;
2119         sdram_bankmachine0_cmd_payload_cas <= 1'd0;
2120         sdram_bankmachine0_cmd_payload_ras <= 1'd0;
2121         subfragments_bankmachine0_next_state <= 3'd0;
2122         sdram_bankmachine0_cmd_payload_we <= 1'd0;
2123         sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
2124         sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
2125         sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
2126         sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
2127         sdram_bankmachine0_req_wdata_ready <= 1'd0;
2128         sdram_bankmachine0_req_rdata_valid <= 1'd0;
2129         subfragments_bankmachine0_next_state <= subfragments_bankmachine0_state;
2130         case (subfragments_bankmachine0_state)
2131                 1'd1: begin
2132                         if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin
2133                                 sdram_bankmachine0_cmd_valid <= 1'd1;
2134                                 if (sdram_bankmachine0_cmd_ready) begin
2135                                         subfragments_bankmachine0_next_state <= 3'd5;
2136                                 end
2137                                 sdram_bankmachine0_cmd_payload_ras <= 1'd1;
2138                                 sdram_bankmachine0_cmd_payload_we <= 1'd1;
2139                                 sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
2140                         end
2141                         sdram_bankmachine0_row_close <= 1'd1;
2142                 end
2143                 2'd2: begin
2144                         if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin
2145                                 subfragments_bankmachine0_next_state <= 3'd5;
2146                         end
2147                         sdram_bankmachine0_row_close <= 1'd1;
2148                 end
2149                 2'd3: begin
2150                         if (sdram_bankmachine0_trccon_ready) begin
2151                                 sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
2152                                 sdram_bankmachine0_row_open <= 1'd1;
2153                                 sdram_bankmachine0_cmd_valid <= 1'd1;
2154                                 sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
2155                                 if (sdram_bankmachine0_cmd_ready) begin
2156                                         subfragments_bankmachine0_next_state <= 3'd6;
2157                                 end
2158                                 sdram_bankmachine0_cmd_payload_ras <= 1'd1;
2159                         end
2160                 end
2161                 3'd4: begin
2162                         if (sdram_bankmachine0_twtpcon_ready) begin
2163                                 sdram_bankmachine0_refresh_gnt <= 1'd1;
2164                         end
2165                         sdram_bankmachine0_row_close <= 1'd1;
2166                         sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
2167                         if ((~sdram_bankmachine0_refresh_req)) begin
2168                                 subfragments_bankmachine0_next_state <= 1'd0;
2169                         end
2170                 end
2171                 3'd5: begin
2172                         subfragments_bankmachine0_next_state <= 2'd3;
2173                 end
2174                 3'd6: begin
2175                         subfragments_bankmachine0_next_state <= 1'd0;
2176                 end
2177                 default: begin
2178                         if (sdram_bankmachine0_refresh_req) begin
2179                                 subfragments_bankmachine0_next_state <= 3'd4;
2180                         end else begin
2181                                 if (sdram_bankmachine0_cmd_buffer_source_valid) begin
2182                                         if (sdram_bankmachine0_row_opened) begin
2183                                                 if (sdram_bankmachine0_row_hit) begin
2184                                                         sdram_bankmachine0_cmd_valid <= 1'd1;
2185                                                         if (sdram_bankmachine0_cmd_buffer_source_payload_we) begin
2186                                                                 sdram_bankmachine0_req_wdata_ready <= sdram_bankmachine0_cmd_ready;
2187                                                                 sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
2188                                                                 sdram_bankmachine0_cmd_payload_we <= 1'd1;
2189                                                         end else begin
2190                                                                 sdram_bankmachine0_req_rdata_valid <= sdram_bankmachine0_cmd_ready;
2191                                                                 sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
2192                                                         end
2193                                                         sdram_bankmachine0_cmd_payload_cas <= 1'd1;
2194                                                         if ((sdram_bankmachine0_cmd_ready & sdram_bankmachine0_auto_precharge)) begin
2195                                                                 subfragments_bankmachine0_next_state <= 2'd2;
2196                                                         end
2197                                                 end else begin
2198                                                         subfragments_bankmachine0_next_state <= 1'd1;
2199                                                 end
2200                                         end else begin
2201                                                 subfragments_bankmachine0_next_state <= 2'd3;
2202                                         end
2203                                 end
2204                         end
2205                 end
2206         endcase
2207 end
2208 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = sdram_bankmachine1_req_valid;
2209 assign sdram_bankmachine1_req_ready = sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
2210 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine1_req_we;
2211 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine1_req_addr;
2212 assign sdram_bankmachine1_cmd_buffer_sink_valid = sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
2213 assign sdram_bankmachine1_cmd_buffer_lookahead_source_ready = sdram_bankmachine1_cmd_buffer_sink_ready;
2214 assign sdram_bankmachine1_cmd_buffer_sink_first = sdram_bankmachine1_cmd_buffer_lookahead_source_first;
2215 assign sdram_bankmachine1_cmd_buffer_sink_last = sdram_bankmachine1_cmd_buffer_lookahead_source_last;
2216 assign sdram_bankmachine1_cmd_buffer_sink_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
2217 assign sdram_bankmachine1_cmd_buffer_sink_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
2218 assign sdram_bankmachine1_cmd_buffer_source_ready = (sdram_bankmachine1_req_wdata_ready | sdram_bankmachine1_req_rdata_valid);
2219 assign sdram_bankmachine1_req_lock = (sdram_bankmachine1_cmd_buffer_lookahead_source_valid | sdram_bankmachine1_cmd_buffer_source_valid);
2220 assign sdram_bankmachine1_row_hit = (sdram_bankmachine1_row == sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]);
2221 assign sdram_bankmachine1_cmd_payload_ba = 1'd1;
2222 always @(*) begin
2223         sdram_bankmachine1_cmd_payload_a <= 13'd0;
2224         if (sdram_bankmachine1_row_col_n_addr_sel) begin
2225                 sdram_bankmachine1_cmd_payload_a <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
2226         end else begin
2227                 sdram_bankmachine1_cmd_payload_a <= ((sdram_bankmachine1_auto_precharge <<< 4'd10) | {sdram_bankmachine1_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2228         end
2229 end
2230 assign sdram_bankmachine1_twtpcon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_cmd_payload_is_write);
2231 assign sdram_bankmachine1_trccon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open);
2232 assign sdram_bankmachine1_trascon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open);
2233 always @(*) begin
2234         sdram_bankmachine1_auto_precharge <= 1'd0;
2235         if ((sdram_bankmachine1_cmd_buffer_lookahead_source_valid & sdram_bankmachine1_cmd_buffer_source_valid)) begin
2236                 if ((sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9])) begin
2237                         sdram_bankmachine1_auto_precharge <= (sdram_bankmachine1_row_close == 1'd0);
2238                 end
2239         end
2240 end
2241 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
2242 assign {sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
2243 assign sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
2244 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
2245 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
2246 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
2247 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
2248 assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
2249 assign sdram_bankmachine1_cmd_buffer_lookahead_source_valid = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
2250 assign sdram_bankmachine1_cmd_buffer_lookahead_source_first = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
2251 assign sdram_bankmachine1_cmd_buffer_lookahead_source_last = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
2252 assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
2253 assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
2254 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
2255 always @(*) begin
2256         sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2257         if (sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
2258                 sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
2259         end else begin
2260                 sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine1_cmd_buffer_lookahead_produce;
2261         end
2262 end
2263 assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
2264 assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | sdram_bankmachine1_cmd_buffer_lookahead_replace));
2265 assign sdram_bankmachine1_cmd_buffer_lookahead_do_read = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
2266 assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine1_cmd_buffer_lookahead_consume;
2267 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
2268 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8);
2269 assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
2270 assign sdram_bankmachine1_cmd_buffer_sink_ready = ((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready);
2271 always @(*) begin
2272         sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
2273         sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
2274         sdram_bankmachine1_req_wdata_ready <= 1'd0;
2275         sdram_bankmachine1_req_rdata_valid <= 1'd0;
2276         sdram_bankmachine1_refresh_gnt <= 1'd0;
2277         sdram_bankmachine1_cmd_valid <= 1'd0;
2278         subfragments_bankmachine1_next_state <= 3'd0;
2279         sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
2280         sdram_bankmachine1_row_open <= 1'd0;
2281         sdram_bankmachine1_row_close <= 1'd0;
2282         sdram_bankmachine1_cmd_payload_cas <= 1'd0;
2283         sdram_bankmachine1_cmd_payload_ras <= 1'd0;
2284         sdram_bankmachine1_cmd_payload_we <= 1'd0;
2285         sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
2286         subfragments_bankmachine1_next_state <= subfragments_bankmachine1_state;
2287         case (subfragments_bankmachine1_state)
2288                 1'd1: begin
2289                         if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin
2290                                 sdram_bankmachine1_cmd_valid <= 1'd1;
2291                                 if (sdram_bankmachine1_cmd_ready) begin
2292                                         subfragments_bankmachine1_next_state <= 3'd5;
2293                                 end
2294                                 sdram_bankmachine1_cmd_payload_ras <= 1'd1;
2295                                 sdram_bankmachine1_cmd_payload_we <= 1'd1;
2296                                 sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2297                         end
2298                         sdram_bankmachine1_row_close <= 1'd1;
2299                 end
2300                 2'd2: begin
2301                         if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin
2302                                 subfragments_bankmachine1_next_state <= 3'd5;
2303                         end
2304                         sdram_bankmachine1_row_close <= 1'd1;
2305                 end
2306                 2'd3: begin
2307                         if (sdram_bankmachine1_trccon_ready) begin
2308                                 sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
2309                                 sdram_bankmachine1_row_open <= 1'd1;
2310                                 sdram_bankmachine1_cmd_valid <= 1'd1;
2311                                 sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2312                                 if (sdram_bankmachine1_cmd_ready) begin
2313                                         subfragments_bankmachine1_next_state <= 3'd6;
2314                                 end
2315                                 sdram_bankmachine1_cmd_payload_ras <= 1'd1;
2316                         end
2317                 end
2318                 3'd4: begin
2319                         if (sdram_bankmachine1_twtpcon_ready) begin
2320                                 sdram_bankmachine1_refresh_gnt <= 1'd1;
2321                         end
2322                         sdram_bankmachine1_row_close <= 1'd1;
2323                         sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
2324                         if ((~sdram_bankmachine1_refresh_req)) begin
2325                                 subfragments_bankmachine1_next_state <= 1'd0;
2326                         end
2327                 end
2328                 3'd5: begin
2329                         subfragments_bankmachine1_next_state <= 2'd3;
2330                 end
2331                 3'd6: begin
2332                         subfragments_bankmachine1_next_state <= 1'd0;
2333                 end
2334                 default: begin
2335                         if (sdram_bankmachine1_refresh_req) begin
2336                                 subfragments_bankmachine1_next_state <= 3'd4;
2337                         end else begin
2338                                 if (sdram_bankmachine1_cmd_buffer_source_valid) begin
2339                                         if (sdram_bankmachine1_row_opened) begin
2340                                                 if (sdram_bankmachine1_row_hit) begin
2341                                                         sdram_bankmachine1_cmd_valid <= 1'd1;
2342                                                         if (sdram_bankmachine1_cmd_buffer_source_payload_we) begin
2343                                                                 sdram_bankmachine1_req_wdata_ready <= sdram_bankmachine1_cmd_ready;
2344                                                                 sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
2345                                                                 sdram_bankmachine1_cmd_payload_we <= 1'd1;
2346                                                         end else begin
2347                                                                 sdram_bankmachine1_req_rdata_valid <= sdram_bankmachine1_cmd_ready;
2348                                                                 sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
2349                                                         end
2350                                                         sdram_bankmachine1_cmd_payload_cas <= 1'd1;
2351                                                         if ((sdram_bankmachine1_cmd_ready & sdram_bankmachine1_auto_precharge)) begin
2352                                                                 subfragments_bankmachine1_next_state <= 2'd2;
2353                                                         end
2354                                                 end else begin
2355                                                         subfragments_bankmachine1_next_state <= 1'd1;
2356                                                 end
2357                                         end else begin
2358                                                 subfragments_bankmachine1_next_state <= 2'd3;
2359                                         end
2360                                 end
2361                         end
2362                 end
2363         endcase
2364 end
2365 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = sdram_bankmachine2_req_valid;
2366 assign sdram_bankmachine2_req_ready = sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
2367 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine2_req_we;
2368 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine2_req_addr;
2369 assign sdram_bankmachine2_cmd_buffer_sink_valid = sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
2370 assign sdram_bankmachine2_cmd_buffer_lookahead_source_ready = sdram_bankmachine2_cmd_buffer_sink_ready;
2371 assign sdram_bankmachine2_cmd_buffer_sink_first = sdram_bankmachine2_cmd_buffer_lookahead_source_first;
2372 assign sdram_bankmachine2_cmd_buffer_sink_last = sdram_bankmachine2_cmd_buffer_lookahead_source_last;
2373 assign sdram_bankmachine2_cmd_buffer_sink_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
2374 assign sdram_bankmachine2_cmd_buffer_sink_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
2375 assign sdram_bankmachine2_cmd_buffer_source_ready = (sdram_bankmachine2_req_wdata_ready | sdram_bankmachine2_req_rdata_valid);
2376 assign sdram_bankmachine2_req_lock = (sdram_bankmachine2_cmd_buffer_lookahead_source_valid | sdram_bankmachine2_cmd_buffer_source_valid);
2377 assign sdram_bankmachine2_row_hit = (sdram_bankmachine2_row == sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]);
2378 assign sdram_bankmachine2_cmd_payload_ba = 2'd2;
2379 always @(*) begin
2380         sdram_bankmachine2_cmd_payload_a <= 13'd0;
2381         if (sdram_bankmachine2_row_col_n_addr_sel) begin
2382                 sdram_bankmachine2_cmd_payload_a <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
2383         end else begin
2384                 sdram_bankmachine2_cmd_payload_a <= ((sdram_bankmachine2_auto_precharge <<< 4'd10) | {sdram_bankmachine2_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2385         end
2386 end
2387 assign sdram_bankmachine2_twtpcon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_cmd_payload_is_write);
2388 assign sdram_bankmachine2_trccon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open);
2389 assign sdram_bankmachine2_trascon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open);
2390 always @(*) begin
2391         sdram_bankmachine2_auto_precharge <= 1'd0;
2392         if ((sdram_bankmachine2_cmd_buffer_lookahead_source_valid & sdram_bankmachine2_cmd_buffer_source_valid)) begin
2393                 if ((sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9])) begin
2394                         sdram_bankmachine2_auto_precharge <= (sdram_bankmachine2_row_close == 1'd0);
2395                 end
2396         end
2397 end
2398 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
2399 assign {sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
2400 assign sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
2401 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
2402 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
2403 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
2404 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
2405 assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
2406 assign sdram_bankmachine2_cmd_buffer_lookahead_source_valid = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
2407 assign sdram_bankmachine2_cmd_buffer_lookahead_source_first = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
2408 assign sdram_bankmachine2_cmd_buffer_lookahead_source_last = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
2409 assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
2410 assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
2411 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
2412 always @(*) begin
2413         sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2414         if (sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
2415                 sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
2416         end else begin
2417                 sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine2_cmd_buffer_lookahead_produce;
2418         end
2419 end
2420 assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
2421 assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | sdram_bankmachine2_cmd_buffer_lookahead_replace));
2422 assign sdram_bankmachine2_cmd_buffer_lookahead_do_read = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
2423 assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine2_cmd_buffer_lookahead_consume;
2424 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
2425 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8);
2426 assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
2427 assign sdram_bankmachine2_cmd_buffer_sink_ready = ((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready);
2428 always @(*) begin
2429         sdram_bankmachine2_cmd_payload_cas <= 1'd0;
2430         sdram_bankmachine2_cmd_payload_ras <= 1'd0;
2431         sdram_bankmachine2_cmd_payload_we <= 1'd0;
2432         sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
2433         sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
2434         sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
2435         sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
2436         subfragments_bankmachine2_next_state <= 3'd0;
2437         sdram_bankmachine2_req_wdata_ready <= 1'd0;
2438         sdram_bankmachine2_req_rdata_valid <= 1'd0;
2439         sdram_bankmachine2_refresh_gnt <= 1'd0;
2440         sdram_bankmachine2_cmd_valid <= 1'd0;
2441         sdram_bankmachine2_row_open <= 1'd0;
2442         sdram_bankmachine2_row_close <= 1'd0;
2443         subfragments_bankmachine2_next_state <= subfragments_bankmachine2_state;
2444         case (subfragments_bankmachine2_state)
2445                 1'd1: begin
2446                         if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin
2447                                 sdram_bankmachine2_cmd_valid <= 1'd1;
2448                                 if (sdram_bankmachine2_cmd_ready) begin
2449                                         subfragments_bankmachine2_next_state <= 3'd5;
2450                                 end
2451                                 sdram_bankmachine2_cmd_payload_ras <= 1'd1;
2452                                 sdram_bankmachine2_cmd_payload_we <= 1'd1;
2453                                 sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2454                         end
2455                         sdram_bankmachine2_row_close <= 1'd1;
2456                 end
2457                 2'd2: begin
2458                         if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin
2459                                 subfragments_bankmachine2_next_state <= 3'd5;
2460                         end
2461                         sdram_bankmachine2_row_close <= 1'd1;
2462                 end
2463                 2'd3: begin
2464                         if (sdram_bankmachine2_trccon_ready) begin
2465                                 sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
2466                                 sdram_bankmachine2_row_open <= 1'd1;
2467                                 sdram_bankmachine2_cmd_valid <= 1'd1;
2468                                 sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2469                                 if (sdram_bankmachine2_cmd_ready) begin
2470                                         subfragments_bankmachine2_next_state <= 3'd6;
2471                                 end
2472                                 sdram_bankmachine2_cmd_payload_ras <= 1'd1;
2473                         end
2474                 end
2475                 3'd4: begin
2476                         if (sdram_bankmachine2_twtpcon_ready) begin
2477                                 sdram_bankmachine2_refresh_gnt <= 1'd1;
2478                         end
2479                         sdram_bankmachine2_row_close <= 1'd1;
2480                         sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
2481                         if ((~sdram_bankmachine2_refresh_req)) begin
2482                                 subfragments_bankmachine2_next_state <= 1'd0;
2483                         end
2484                 end
2485                 3'd5: begin
2486                         subfragments_bankmachine2_next_state <= 2'd3;
2487                 end
2488                 3'd6: begin
2489                         subfragments_bankmachine2_next_state <= 1'd0;
2490                 end
2491                 default: begin
2492                         if (sdram_bankmachine2_refresh_req) begin
2493                                 subfragments_bankmachine2_next_state <= 3'd4;
2494                         end else begin
2495                                 if (sdram_bankmachine2_cmd_buffer_source_valid) begin
2496                                         if (sdram_bankmachine2_row_opened) begin
2497                                                 if (sdram_bankmachine2_row_hit) begin
2498                                                         sdram_bankmachine2_cmd_valid <= 1'd1;
2499                                                         if (sdram_bankmachine2_cmd_buffer_source_payload_we) begin
2500                                                                 sdram_bankmachine2_req_wdata_ready <= sdram_bankmachine2_cmd_ready;
2501                                                                 sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
2502                                                                 sdram_bankmachine2_cmd_payload_we <= 1'd1;
2503                                                         end else begin
2504                                                                 sdram_bankmachine2_req_rdata_valid <= sdram_bankmachine2_cmd_ready;
2505                                                                 sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
2506                                                         end
2507                                                         sdram_bankmachine2_cmd_payload_cas <= 1'd1;
2508                                                         if ((sdram_bankmachine2_cmd_ready & sdram_bankmachine2_auto_precharge)) begin
2509                                                                 subfragments_bankmachine2_next_state <= 2'd2;
2510                                                         end
2511                                                 end else begin
2512                                                         subfragments_bankmachine2_next_state <= 1'd1;
2513                                                 end
2514                                         end else begin
2515                                                 subfragments_bankmachine2_next_state <= 2'd3;
2516                                         end
2517                                 end
2518                         end
2519                 end
2520         endcase
2521 end
2522 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = sdram_bankmachine3_req_valid;
2523 assign sdram_bankmachine3_req_ready = sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
2524 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine3_req_we;
2525 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine3_req_addr;
2526 assign sdram_bankmachine3_cmd_buffer_sink_valid = sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
2527 assign sdram_bankmachine3_cmd_buffer_lookahead_source_ready = sdram_bankmachine3_cmd_buffer_sink_ready;
2528 assign sdram_bankmachine3_cmd_buffer_sink_first = sdram_bankmachine3_cmd_buffer_lookahead_source_first;
2529 assign sdram_bankmachine3_cmd_buffer_sink_last = sdram_bankmachine3_cmd_buffer_lookahead_source_last;
2530 assign sdram_bankmachine3_cmd_buffer_sink_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
2531 assign sdram_bankmachine3_cmd_buffer_sink_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
2532 assign sdram_bankmachine3_cmd_buffer_source_ready = (sdram_bankmachine3_req_wdata_ready | sdram_bankmachine3_req_rdata_valid);
2533 assign sdram_bankmachine3_req_lock = (sdram_bankmachine3_cmd_buffer_lookahead_source_valid | sdram_bankmachine3_cmd_buffer_source_valid);
2534 assign sdram_bankmachine3_row_hit = (sdram_bankmachine3_row == sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]);
2535 assign sdram_bankmachine3_cmd_payload_ba = 2'd3;
2536 always @(*) begin
2537         sdram_bankmachine3_cmd_payload_a <= 13'd0;
2538         if (sdram_bankmachine3_row_col_n_addr_sel) begin
2539                 sdram_bankmachine3_cmd_payload_a <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
2540         end else begin
2541                 sdram_bankmachine3_cmd_payload_a <= ((sdram_bankmachine3_auto_precharge <<< 4'd10) | {sdram_bankmachine3_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}});
2542         end
2543 end
2544 assign sdram_bankmachine3_twtpcon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_cmd_payload_is_write);
2545 assign sdram_bankmachine3_trccon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open);
2546 assign sdram_bankmachine3_trascon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open);
2547 always @(*) begin
2548         sdram_bankmachine3_auto_precharge <= 1'd0;
2549         if ((sdram_bankmachine3_cmd_buffer_lookahead_source_valid & sdram_bankmachine3_cmd_buffer_source_valid)) begin
2550                 if ((sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9])) begin
2551                         sdram_bankmachine3_auto_precharge <= (sdram_bankmachine3_row_close == 1'd0);
2552                 end
2553         end
2554 end
2555 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
2556 assign {sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
2557 assign sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
2558 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
2559 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
2560 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
2561 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
2562 assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
2563 assign sdram_bankmachine3_cmd_buffer_lookahead_source_valid = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
2564 assign sdram_bankmachine3_cmd_buffer_lookahead_source_first = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
2565 assign sdram_bankmachine3_cmd_buffer_lookahead_source_last = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
2566 assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
2567 assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
2568 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
2569 always @(*) begin
2570         sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0;
2571         if (sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
2572                 sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
2573         end else begin
2574                 sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine3_cmd_buffer_lookahead_produce;
2575         end
2576 end
2577 assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
2578 assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | sdram_bankmachine3_cmd_buffer_lookahead_replace));
2579 assign sdram_bankmachine3_cmd_buffer_lookahead_do_read = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
2580 assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine3_cmd_buffer_lookahead_consume;
2581 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
2582 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8);
2583 assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
2584 assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready);
2585 always @(*) begin
2586         sdram_bankmachine3_row_open <= 1'd0;
2587         sdram_bankmachine3_row_close <= 1'd0;
2588         subfragments_bankmachine3_next_state <= 3'd0;
2589         sdram_bankmachine3_cmd_payload_cas <= 1'd0;
2590         sdram_bankmachine3_cmd_payload_ras <= 1'd0;
2591         sdram_bankmachine3_cmd_payload_we <= 1'd0;
2592         sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
2593         sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
2594         sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
2595         sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
2596         sdram_bankmachine3_req_wdata_ready <= 1'd0;
2597         sdram_bankmachine3_req_rdata_valid <= 1'd0;
2598         sdram_bankmachine3_refresh_gnt <= 1'd0;
2599         sdram_bankmachine3_cmd_valid <= 1'd0;
2600         subfragments_bankmachine3_next_state <= subfragments_bankmachine3_state;
2601         case (subfragments_bankmachine3_state)
2602                 1'd1: begin
2603                         if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin
2604                                 sdram_bankmachine3_cmd_valid <= 1'd1;
2605                                 if (sdram_bankmachine3_cmd_ready) begin
2606                                         subfragments_bankmachine3_next_state <= 3'd5;
2607                                 end
2608                                 sdram_bankmachine3_cmd_payload_ras <= 1'd1;
2609                                 sdram_bankmachine3_cmd_payload_we <= 1'd1;
2610                                 sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2611                         end
2612                         sdram_bankmachine3_row_close <= 1'd1;
2613                 end
2614                 2'd2: begin
2615                         if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin
2616                                 subfragments_bankmachine3_next_state <= 3'd5;
2617                         end
2618                         sdram_bankmachine3_row_close <= 1'd1;
2619                 end
2620                 2'd3: begin
2621                         if (sdram_bankmachine3_trccon_ready) begin
2622                                 sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
2623                                 sdram_bankmachine3_row_open <= 1'd1;
2624                                 sdram_bankmachine3_cmd_valid <= 1'd1;
2625                                 sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2626                                 if (sdram_bankmachine3_cmd_ready) begin
2627                                         subfragments_bankmachine3_next_state <= 3'd6;
2628                                 end
2629                                 sdram_bankmachine3_cmd_payload_ras <= 1'd1;
2630                         end
2631                 end
2632                 3'd4: begin
2633                         if (sdram_bankmachine3_twtpcon_ready) begin
2634                                 sdram_bankmachine3_refresh_gnt <= 1'd1;
2635                         end
2636                         sdram_bankmachine3_row_close <= 1'd1;
2637                         sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
2638                         if ((~sdram_bankmachine3_refresh_req)) begin
2639                                 subfragments_bankmachine3_next_state <= 1'd0;
2640                         end
2641                 end
2642                 3'd5: begin
2643                         subfragments_bankmachine3_next_state <= 2'd3;
2644                 end
2645                 3'd6: begin
2646                         subfragments_bankmachine3_next_state <= 1'd0;
2647                 end
2648                 default: begin
2649                         if (sdram_bankmachine3_refresh_req) begin
2650                                 subfragments_bankmachine3_next_state <= 3'd4;
2651                         end else begin
2652                                 if (sdram_bankmachine3_cmd_buffer_source_valid) begin
2653                                         if (sdram_bankmachine3_row_opened) begin
2654                                                 if (sdram_bankmachine3_row_hit) begin
2655                                                         sdram_bankmachine3_cmd_valid <= 1'd1;
2656                                                         if (sdram_bankmachine3_cmd_buffer_source_payload_we) begin
2657                                                                 sdram_bankmachine3_req_wdata_ready <= sdram_bankmachine3_cmd_ready;
2658                                                                 sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
2659                                                                 sdram_bankmachine3_cmd_payload_we <= 1'd1;
2660                                                         end else begin
2661                                                                 sdram_bankmachine3_req_rdata_valid <= sdram_bankmachine3_cmd_ready;
2662                                                                 sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
2663                                                         end
2664                                                         sdram_bankmachine3_cmd_payload_cas <= 1'd1;
2665                                                         if ((sdram_bankmachine3_cmd_ready & sdram_bankmachine3_auto_precharge)) begin
2666                                                                 subfragments_bankmachine3_next_state <= 2'd2;
2667                                                         end
2668                                                 end else begin
2669                                                         subfragments_bankmachine3_next_state <= 1'd1;
2670                                                 end
2671                                         end else begin
2672                                                 subfragments_bankmachine3_next_state <= 2'd3;
2673                                         end
2674                                 end
2675                         end
2676                 end
2677         endcase
2678 end
2679 assign sdram_choose_req_want_cmds = 1'd1;
2680 assign sdram_trrdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we)));
2681 assign sdram_tfawcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we)));
2682 assign sdram_ras_allowed = (sdram_trrdcon_ready & sdram_tfawcon_ready);
2683 assign sdram_tccdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_cmd_payload_is_write | sdram_choose_req_cmd_payload_is_read));
2684 assign sdram_cas_allowed = sdram_tccdcon_ready;
2685 assign sdram_twtrcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write);
2686 assign sdram_read_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_read) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_read)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_read)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_read));
2687 assign sdram_write_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_write) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_write)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_write)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_write));
2688 assign sdram_max_time0 = (sdram_time0 == 1'd0);
2689 assign sdram_max_time1 = (sdram_time1 == 1'd0);
2690 assign sdram_bankmachine0_refresh_req = sdram_cmd_valid;
2691 assign sdram_bankmachine1_refresh_req = sdram_cmd_valid;
2692 assign sdram_bankmachine2_refresh_req = sdram_cmd_valid;
2693 assign sdram_bankmachine3_refresh_req = sdram_cmd_valid;
2694 assign sdram_go_to_refresh = (((sdram_bankmachine0_refresh_gnt & sdram_bankmachine1_refresh_gnt) & sdram_bankmachine2_refresh_gnt) & sdram_bankmachine3_refresh_gnt);
2695 assign sdram_interface_rdata = {sdram_dfi_p0_rddata};
2696 assign {sdram_dfi_p0_wrdata} = sdram_interface_wdata;
2697 assign {sdram_dfi_p0_wrdata_mask} = (~sdram_interface_wdata_we);
2698 always @(*) begin
2699         sdram_choose_cmd_valids <= 4'd0;
2700         sdram_choose_cmd_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2701         sdram_choose_cmd_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2702         sdram_choose_cmd_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2703         sdram_choose_cmd_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_cmd_want_writes))));
2704 end
2705 assign sdram_choose_cmd_request = sdram_choose_cmd_valids;
2706 assign sdram_choose_cmd_cmd_valid = rhs_array_muxed0;
2707 assign sdram_choose_cmd_cmd_payload_a = rhs_array_muxed1;
2708 assign sdram_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
2709 assign sdram_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
2710 assign sdram_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
2711 assign sdram_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
2712 always @(*) begin
2713         sdram_choose_cmd_cmd_payload_cas <= 1'd0;
2714         if (sdram_choose_cmd_cmd_valid) begin
2715                 sdram_choose_cmd_cmd_payload_cas <= t_array_muxed0;
2716         end
2717 end
2718 always @(*) begin
2719         sdram_choose_cmd_cmd_payload_ras <= 1'd0;
2720         if (sdram_choose_cmd_cmd_valid) begin
2721                 sdram_choose_cmd_cmd_payload_ras <= t_array_muxed1;
2722         end
2723 end
2724 always @(*) begin
2725         sdram_choose_cmd_cmd_payload_we <= 1'd0;
2726         if (sdram_choose_cmd_cmd_valid) begin
2727                 sdram_choose_cmd_cmd_payload_we <= t_array_muxed2;
2728         end
2729 end
2730 assign sdram_choose_cmd_ce = (sdram_choose_cmd_cmd_ready | (~sdram_choose_cmd_cmd_valid));
2731 always @(*) begin
2732         sdram_choose_req_valids <= 4'd0;
2733         sdram_choose_req_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_req_want_writes))));
2734         sdram_choose_req_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_req_want_writes))));
2735         sdram_choose_req_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_req_want_writes))));
2736         sdram_choose_req_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_req_want_writes))));
2737 end
2738 assign sdram_choose_req_request = sdram_choose_req_valids;
2739 assign sdram_choose_req_cmd_valid = rhs_array_muxed6;
2740 assign sdram_choose_req_cmd_payload_a = rhs_array_muxed7;
2741 assign sdram_choose_req_cmd_payload_ba = rhs_array_muxed8;
2742 assign sdram_choose_req_cmd_payload_is_read = rhs_array_muxed9;
2743 assign sdram_choose_req_cmd_payload_is_write = rhs_array_muxed10;
2744 assign sdram_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
2745 always @(*) begin
2746         sdram_choose_req_cmd_payload_cas <= 1'd0;
2747         if (sdram_choose_req_cmd_valid) begin
2748                 sdram_choose_req_cmd_payload_cas <= t_array_muxed3;
2749         end
2750 end
2751 always @(*) begin
2752         sdram_choose_req_cmd_payload_ras <= 1'd0;
2753         if (sdram_choose_req_cmd_valid) begin
2754                 sdram_choose_req_cmd_payload_ras <= t_array_muxed4;
2755         end
2756 end
2757 always @(*) begin
2758         sdram_choose_req_cmd_payload_we <= 1'd0;
2759         if (sdram_choose_req_cmd_valid) begin
2760                 sdram_choose_req_cmd_payload_we <= t_array_muxed5;
2761         end
2762 end
2763 always @(*) begin
2764         sdram_bankmachine0_cmd_ready <= 1'd0;
2765         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd0))) begin
2766                 sdram_bankmachine0_cmd_ready <= 1'd1;
2767         end
2768         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd0))) begin
2769                 sdram_bankmachine0_cmd_ready <= 1'd1;
2770         end
2771 end
2772 always @(*) begin
2773         sdram_bankmachine1_cmd_ready <= 1'd0;
2774         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd1))) begin
2775                 sdram_bankmachine1_cmd_ready <= 1'd1;
2776         end
2777         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd1))) begin
2778                 sdram_bankmachine1_cmd_ready <= 1'd1;
2779         end
2780 end
2781 always @(*) begin
2782         sdram_bankmachine2_cmd_ready <= 1'd0;
2783         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd2))) begin
2784                 sdram_bankmachine2_cmd_ready <= 1'd1;
2785         end
2786         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd2))) begin
2787                 sdram_bankmachine2_cmd_ready <= 1'd1;
2788         end
2789 end
2790 always @(*) begin
2791         sdram_bankmachine3_cmd_ready <= 1'd0;
2792         if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd3))) begin
2793                 sdram_bankmachine3_cmd_ready <= 1'd1;
2794         end
2795         if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd3))) begin
2796                 sdram_bankmachine3_cmd_ready <= 1'd1;
2797         end
2798 end
2799 assign sdram_choose_req_ce = (sdram_choose_req_cmd_ready | (~sdram_choose_req_cmd_valid));
2800 assign sdram_dfi_p0_reset_n = 1'd1;
2801 assign sdram_dfi_p0_cke = {1{sdram_steerer0}};
2802 assign sdram_dfi_p0_odt = {1{sdram_steerer1}};
2803 always @(*) begin
2804         subfragments_multiplexer_next_state <= 3'd0;
2805         sdram_en0 <= 1'd0;
2806         sdram_choose_req_want_writes <= 1'd0;
2807         sdram_en1 <= 1'd0;
2808         sdram_choose_req_want_reads <= 1'd0;
2809         sdram_choose_req_cmd_ready <= 1'd0;
2810         sdram_cmd_ready <= 1'd0;
2811         sdram_choose_req_want_activates <= 1'd0;
2812         sdram_steerer_sel <= 2'd0;
2813         sdram_choose_req_want_activates <= sdram_ras_allowed;
2814         subfragments_multiplexer_next_state <= subfragments_multiplexer_state;
2815         case (subfragments_multiplexer_state)
2816                 1'd1: begin
2817                         sdram_en1 <= 1'd1;
2818                         sdram_choose_req_want_writes <= 1'd1;
2819                         if (1'd1) begin
2820                                 sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed));
2821                         end else begin
2822                                 sdram_choose_req_want_activates <= sdram_ras_allowed;
2823                                 sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed);
2824                                 sdram_choose_req_cmd_ready <= sdram_cas_allowed;
2825                         end
2826                         sdram_steerer_sel <= 2'd2;
2827                         if (sdram_read_available) begin
2828                                 if (((~sdram_write_available) | sdram_max_time1)) begin
2829                                         subfragments_multiplexer_next_state <= 2'd3;
2830                                 end
2831                         end
2832                         if (sdram_go_to_refresh) begin
2833                                 subfragments_multiplexer_next_state <= 2'd2;
2834                         end
2835                 end
2836                 2'd2: begin
2837                         sdram_steerer_sel <= 2'd3;
2838                         sdram_cmd_ready <= 1'd1;
2839                         if (sdram_cmd_last) begin
2840                                 subfragments_multiplexer_next_state <= 1'd0;
2841                         end
2842                 end
2843                 2'd3: begin
2844                         if (sdram_twtrcon_ready) begin
2845                                 subfragments_multiplexer_next_state <= 1'd0;
2846                         end
2847                 end
2848                 3'd4: begin
2849                         subfragments_multiplexer_next_state <= 3'd5;
2850                 end
2851                 3'd5: begin
2852                         subfragments_multiplexer_next_state <= 1'd1;
2853                 end
2854                 default: begin
2855                         sdram_en0 <= 1'd1;
2856                         sdram_choose_req_want_reads <= 1'd1;
2857                         if (1'd1) begin
2858                                 sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed));
2859                         end else begin
2860                                 sdram_choose_req_want_activates <= sdram_ras_allowed;
2861                                 sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed);
2862                                 sdram_choose_req_cmd_ready <= sdram_cas_allowed;
2863                         end
2864                         sdram_steerer_sel <= 2'd2;
2865                         if (sdram_write_available) begin
2866                                 if (((~sdram_read_available) | sdram_max_time0)) begin
2867                                         subfragments_multiplexer_next_state <= 3'd4;
2868                                 end
2869                         end
2870                         if (sdram_go_to_refresh) begin
2871                                 subfragments_multiplexer_next_state <= 2'd2;
2872                         end
2873                 end
2874         endcase
2875 end
2876 assign subfragments_roundrobin0_request = {(((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)};
2877 assign subfragments_roundrobin0_ce = ((~sdram_interface_bank0_valid) & (~sdram_interface_bank0_lock));
2878 assign sdram_interface_bank0_addr = rhs_array_muxed12;
2879 assign sdram_interface_bank0_we = rhs_array_muxed13;
2880 assign sdram_interface_bank0_valid = rhs_array_muxed14;
2881 assign subfragments_roundrobin1_request = {(((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)};
2882 assign subfragments_roundrobin1_ce = ((~sdram_interface_bank1_valid) & (~sdram_interface_bank1_lock));
2883 assign sdram_interface_bank1_addr = rhs_array_muxed15;
2884 assign sdram_interface_bank1_we = rhs_array_muxed16;
2885 assign sdram_interface_bank1_valid = rhs_array_muxed17;
2886 assign subfragments_roundrobin2_request = {(((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)};
2887 assign subfragments_roundrobin2_ce = ((~sdram_interface_bank2_valid) & (~sdram_interface_bank2_lock));
2888 assign sdram_interface_bank2_addr = rhs_array_muxed18;
2889 assign sdram_interface_bank2_we = rhs_array_muxed19;
2890 assign sdram_interface_bank2_valid = rhs_array_muxed20;
2891 assign subfragments_roundrobin3_request = {(((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid)};
2892 assign subfragments_roundrobin3_ce = ((~sdram_interface_bank3_valid) & (~sdram_interface_bank3_lock));
2893 assign sdram_interface_bank3_addr = rhs_array_muxed21;
2894 assign sdram_interface_bank3_we = rhs_array_muxed22;
2895 assign sdram_interface_bank3_valid = rhs_array_muxed23;
2896 assign port_cmd_ready = ((((1'd0 | (((subfragments_roundrobin0_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank0_ready)) | (((subfragments_roundrobin1_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank1_ready)) | (((subfragments_roundrobin2_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank2_ready)) | (((subfragments_roundrobin3_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0)))))) & sdram_interface_bank3_ready));
2897 assign port_wdata_ready = subfragments_new_master_wdata_ready;
2898 assign port_rdata_valid = subfragments_new_master_rdata_valid3;
2899 always @(*) begin
2900         sdram_interface_wdata <= 16'd0;
2901         sdram_interface_wdata_we <= 2'd0;
2902         case ({subfragments_new_master_wdata_ready})
2903                 1'd1: begin
2904                         sdram_interface_wdata <= port_wdata_payload_data;
2905                         sdram_interface_wdata_we <= port_wdata_payload_we;
2906                 end
2907                 default: begin
2908                         sdram_interface_wdata <= 1'd0;
2909                         sdram_interface_wdata_we <= 1'd0;
2910                 end
2911         endcase
2912 end
2913 assign port_rdata_payload_data = sdram_interface_rdata;
2914 assign subfragments_roundrobin0_grant = 1'd0;
2915 assign subfragments_roundrobin1_grant = 1'd0;
2916 assign subfragments_roundrobin2_grant = 1'd0;
2917 assign subfragments_roundrobin3_grant = 1'd0;
2918 assign converter_reset = (~wb_sdram_cyc);
2919 always @(*) begin
2920         litedram_wb_dat_w <= 16'd0;
2921         case (converter_counter)
2922                 1'd0: begin
2923                         litedram_wb_dat_w <= wb_sdram_dat_w[31:0];
2924                 end
2925                 1'd1: begin
2926                         litedram_wb_dat_w <= wb_sdram_dat_w[31:16];
2927                 end
2928         endcase
2929 end
2930 assign wb_sdram_dat_r = {litedram_wb_dat_r, converter_dat_r[31:16]};
2931 always @(*) begin
2932         converter_skip <= 1'd0;
2933         wb_sdram_ack <= 1'd0;
2934         subfragments_next_state <= 1'd0;
2935         converter_counter_subfragments_next_value <= 1'd0;
2936         litedram_wb_adr <= 30'd0;
2937         converter_counter_subfragments_next_value_ce <= 1'd0;
2938         litedram_wb_sel <= 2'd0;
2939         litedram_wb_cyc <= 1'd0;
2940         litedram_wb_stb <= 1'd0;
2941         litedram_wb_we <= 1'd0;
2942         subfragments_next_state <= subfragments_state;
2943         case (subfragments_state)
2944                 1'd1: begin
2945                         litedram_wb_adr <= {wb_sdram_adr, converter_counter};
2946                         case (converter_counter)
2947                                 1'd0: begin
2948                                         litedram_wb_sel <= wb_sdram_sel[3:0];
2949                                 end
2950                                 1'd1: begin
2951                                         litedram_wb_sel <= wb_sdram_sel[3:2];
2952                                 end
2953                         endcase
2954                         if ((wb_sdram_stb & wb_sdram_cyc)) begin
2955                                 converter_skip <= (litedram_wb_sel == 1'd0);
2956                                 litedram_wb_we <= wb_sdram_we;
2957                                 litedram_wb_cyc <= (~converter_skip);
2958                                 litedram_wb_stb <= (~converter_skip);
2959                                 if ((litedram_wb_ack | converter_skip)) begin
2960                                         converter_counter_subfragments_next_value <= (converter_counter + 1'd1);
2961                                         converter_counter_subfragments_next_value_ce <= 1'd1;
2962                                         if ((converter_counter == 1'd1)) begin
2963                                                 wb_sdram_ack <= 1'd1;
2964                                                 subfragments_next_state <= 1'd0;
2965                                         end
2966                                 end
2967                         end
2968                 end
2969                 default: begin
2970                         converter_counter_subfragments_next_value <= 1'd0;
2971                         converter_counter_subfragments_next_value_ce <= 1'd1;
2972                         if ((wb_sdram_stb & wb_sdram_cyc)) begin
2973                                 subfragments_next_state <= 1'd1;
2974                         end
2975                 end
2976         endcase
2977 end
2978 assign port_cmd_payload_addr = (litedram_wb_adr - 31'd1207959552);
2979 assign port_cmd_payload_we = litedram_wb_we;
2980 assign port_wdata_payload_data = litedram_wb_dat_w;
2981 assign port_wdata_payload_we = litedram_wb_sel;
2982 assign litedram_wb_dat_r = port_rdata_payload_data;
2983 assign port_flush = (~litedram_wb_cyc);
2984 assign port_cmd_last = (~litedram_wb_we);
2985 assign port_cmd_valid = ((litedram_wb_cyc & litedram_wb_stb) & (~cmd_consumed));
2986 assign port_wdata_valid = (((port_cmd_valid | cmd_consumed) & port_cmd_payload_we) & (~wdata_consumed));
2987 assign port_rdata_ready = ((port_cmd_valid | cmd_consumed) & (~port_cmd_payload_we));
2988 assign litedram_wb_ack = (ack_cmd & ((litedram_wb_we & ack_wdata) | ((~litedram_wb_we) & ack_rdata)));
2989 assign ack_cmd = ((port_cmd_valid & port_cmd_ready) | cmd_consumed);
2990 assign ack_wdata = ((port_wdata_valid & port_wdata_ready) | wdata_consumed);
2991 assign ack_rdata = (port_rdata_valid & port_rdata_ready);
2992 assign uart_sink_valid = uart_phy_source_valid;
2993 assign uart_phy_source_ready = uart_sink_ready;
2994 assign uart_sink_first = uart_phy_source_first;
2995 assign uart_sink_last = uart_phy_source_last;
2996 assign uart_sink_payload_data = uart_phy_source_payload_data;
2997 assign uart_phy_sink_valid = uart_source_valid;
2998 assign uart_source_ready = uart_phy_sink_ready;
2999 assign uart_phy_sink_first = uart_source_first;
3000 assign uart_phy_sink_last = uart_source_last;
3001 assign uart_phy_sink_payload_data = uart_source_payload_data;
3002 assign tx_fifo_sink_valid = rxtx_re;
3003 assign tx_fifo_sink_payload_data = rxtx_r;
3004 assign txfull_status = (~tx_fifo_sink_ready);
3005 assign txempty_status = (~tx_fifo_source_valid);
3006 assign uart_source_valid = tx_fifo_source_valid;
3007 assign tx_fifo_source_ready = uart_source_ready;
3008 assign uart_source_first = tx_fifo_source_first;
3009 assign uart_source_last = tx_fifo_source_last;
3010 assign uart_source_payload_data = tx_fifo_source_payload_data;
3011 assign tx_trigger = (~tx_fifo_sink_ready);
3012 assign rx_fifo_sink_valid = uart_sink_valid;
3013 assign uart_sink_ready = rx_fifo_sink_ready;
3014 assign rx_fifo_sink_first = uart_sink_first;
3015 assign rx_fifo_sink_last = uart_sink_last;
3016 assign rx_fifo_sink_payload_data = uart_sink_payload_data;
3017 assign rxempty_status = (~rx_fifo_source_valid);
3018 assign rxfull_status = (~rx_fifo_sink_ready);
3019 assign rxtx_w = rx_fifo_source_payload_data;
3020 assign rx_fifo_source_ready = (rx_clear | (1'd0 & rxtx_we));
3021 assign rx_trigger = (~rx_fifo_source_valid);
3022 always @(*) begin
3023         tx_clear <= 1'd0;
3024         if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin
3025                 tx_clear <= 1'd1;
3026         end
3027 end
3028 always @(*) begin
3029         eventmanager_status_w <= 2'd0;
3030         eventmanager_status_w[0] <= tx_status;
3031         eventmanager_status_w[1] <= rx_status;
3032 end
3033 always @(*) begin
3034         rx_clear <= 1'd0;
3035         if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin
3036                 rx_clear <= 1'd1;
3037         end
3038 end
3039 always @(*) begin
3040         eventmanager_pending_w <= 2'd0;
3041         eventmanager_pending_w[0] <= tx_pending;
3042         eventmanager_pending_w[1] <= rx_pending;
3043 end
3044 assign irq = ((eventmanager_pending_w[0] & eventmanager_storage[0]) | (eventmanager_pending_w[1] & eventmanager_storage[1]));
3045 assign tx_status = tx_trigger;
3046 assign rx_status = rx_trigger;
3047 assign tx_fifo_syncfifo_din = {tx_fifo_fifo_in_last, tx_fifo_fifo_in_first, tx_fifo_fifo_in_payload_data};
3048 assign {tx_fifo_fifo_out_last, tx_fifo_fifo_out_first, tx_fifo_fifo_out_payload_data} = tx_fifo_syncfifo_dout;
3049 assign tx_fifo_sink_ready = tx_fifo_syncfifo_writable;
3050 assign tx_fifo_syncfifo_we = tx_fifo_sink_valid;
3051 assign tx_fifo_fifo_in_first = tx_fifo_sink_first;
3052 assign tx_fifo_fifo_in_last = tx_fifo_sink_last;
3053 assign tx_fifo_fifo_in_payload_data = tx_fifo_sink_payload_data;
3054 assign tx_fifo_source_valid = tx_fifo_readable;
3055 assign tx_fifo_source_first = tx_fifo_fifo_out_first;
3056 assign tx_fifo_source_last = tx_fifo_fifo_out_last;
3057 assign tx_fifo_source_payload_data = tx_fifo_fifo_out_payload_data;
3058 assign tx_fifo_re = tx_fifo_source_ready;
3059 assign tx_fifo_syncfifo_re = (tx_fifo_syncfifo_readable & ((~tx_fifo_readable) | tx_fifo_re));
3060 assign tx_fifo_level1 = (tx_fifo_level0 + tx_fifo_readable);
3061 always @(*) begin
3062         tx_fifo_wrport_adr <= 4'd0;
3063         if (tx_fifo_replace) begin
3064                 tx_fifo_wrport_adr <= (tx_fifo_produce - 1'd1);
3065         end else begin
3066                 tx_fifo_wrport_adr <= tx_fifo_produce;
3067         end
3068 end
3069 assign tx_fifo_wrport_dat_w = tx_fifo_syncfifo_din;
3070 assign tx_fifo_wrport_we = (tx_fifo_syncfifo_we & (tx_fifo_syncfifo_writable | tx_fifo_replace));
3071 assign tx_fifo_do_read = (tx_fifo_syncfifo_readable & tx_fifo_syncfifo_re);
3072 assign tx_fifo_rdport_adr = tx_fifo_consume;
3073 assign tx_fifo_syncfifo_dout = tx_fifo_rdport_dat_r;
3074 assign tx_fifo_rdport_re = tx_fifo_do_read;
3075 assign tx_fifo_syncfifo_writable = (tx_fifo_level0 != 5'd16);
3076 assign tx_fifo_syncfifo_readable = (tx_fifo_level0 != 1'd0);
3077 assign rx_fifo_syncfifo_din = {rx_fifo_fifo_in_last, rx_fifo_fifo_in_first, rx_fifo_fifo_in_payload_data};
3078 assign {rx_fifo_fifo_out_last, rx_fifo_fifo_out_first, rx_fifo_fifo_out_payload_data} = rx_fifo_syncfifo_dout;
3079 assign rx_fifo_sink_ready = rx_fifo_syncfifo_writable;
3080 assign rx_fifo_syncfifo_we = rx_fifo_sink_valid;
3081 assign rx_fifo_fifo_in_first = rx_fifo_sink_first;
3082 assign rx_fifo_fifo_in_last = rx_fifo_sink_last;
3083 assign rx_fifo_fifo_in_payload_data = rx_fifo_sink_payload_data;
3084 assign rx_fifo_source_valid = rx_fifo_readable;
3085 assign rx_fifo_source_first = rx_fifo_fifo_out_first;
3086 assign rx_fifo_source_last = rx_fifo_fifo_out_last;
3087 assign rx_fifo_source_payload_data = rx_fifo_fifo_out_payload_data;
3088 assign rx_fifo_re = rx_fifo_source_ready;
3089 assign rx_fifo_syncfifo_re = (rx_fifo_syncfifo_readable & ((~rx_fifo_readable) | rx_fifo_re));
3090 assign rx_fifo_level1 = (rx_fifo_level0 + rx_fifo_readable);
3091 always @(*) begin
3092         rx_fifo_wrport_adr <= 4'd0;
3093         if (rx_fifo_replace) begin
3094                 rx_fifo_wrport_adr <= (rx_fifo_produce - 1'd1);
3095         end else begin
3096                 rx_fifo_wrport_adr <= rx_fifo_produce;
3097         end
3098 end
3099 assign rx_fifo_wrport_dat_w = rx_fifo_syncfifo_din;
3100 assign rx_fifo_wrport_we = (rx_fifo_syncfifo_we & (rx_fifo_syncfifo_writable | rx_fifo_replace));
3101 assign rx_fifo_do_read = (rx_fifo_syncfifo_readable & rx_fifo_syncfifo_re);
3102 assign rx_fifo_rdport_adr = rx_fifo_consume;
3103 assign rx_fifo_syncfifo_dout = rx_fifo_rdport_dat_r;
3104 assign rx_fifo_rdport_re = rx_fifo_do_read;
3105 assign rx_fifo_syncfifo_writable = (rx_fifo_level0 != 5'd16);
3106 assign rx_fifo_syncfifo_readable = (rx_fifo_level0 != 1'd0);
3107 always @(*) begin
3108         gpio0_pads_gpio0i <= 8'd0;
3109         gpio0_pads_gpio0i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[0];
3110         gpio0_pads_gpio0i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[1];
3111         gpio0_pads_gpio0i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[2];
3112         gpio0_pads_gpio0i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[3];
3113         gpio0_pads_gpio0i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[4];
3114         gpio0_pads_gpio0i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[5];
3115         gpio0_pads_gpio0i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[6];
3116         gpio0_pads_gpio0i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[7];
3117 end
3118 always @(*) begin
3119         gpio1_pads_gpio1i <= 8'd0;
3120         gpio1_pads_gpio1i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[8];
3121         gpio1_pads_gpio1i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[9];
3122         gpio1_pads_gpio1i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[10];
3123         gpio1_pads_gpio1i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[11];
3124         gpio1_pads_gpio1i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[12];
3125         gpio1_pads_gpio1i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[13];
3126         gpio1_pads_gpio1i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[14];
3127         gpio1_pads_gpio1i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[15];
3128 end
3129 always @(*) begin
3130         libresocsim_libresoc_constraintmanager_gpio_o <= 16'd0;
3131         libresocsim_libresoc_constraintmanager_gpio_o[0] <= gpio0_pads_gpio0o[0];
3132         libresocsim_libresoc_constraintmanager_gpio_o[1] <= gpio0_pads_gpio0o[1];
3133         libresocsim_libresoc_constraintmanager_gpio_o[2] <= gpio0_pads_gpio0o[2];
3134         libresocsim_libresoc_constraintmanager_gpio_o[3] <= gpio0_pads_gpio0o[3];
3135         libresocsim_libresoc_constraintmanager_gpio_o[4] <= gpio0_pads_gpio0o[4];
3136         libresocsim_libresoc_constraintmanager_gpio_o[5] <= gpio0_pads_gpio0o[5];
3137         libresocsim_libresoc_constraintmanager_gpio_o[6] <= gpio0_pads_gpio0o[6];
3138         libresocsim_libresoc_constraintmanager_gpio_o[7] <= gpio0_pads_gpio0o[7];
3139         libresocsim_libresoc_constraintmanager_gpio_o[8] <= gpio1_pads_gpio1o[0];
3140         libresocsim_libresoc_constraintmanager_gpio_o[9] <= gpio1_pads_gpio1o[1];
3141         libresocsim_libresoc_constraintmanager_gpio_o[10] <= gpio1_pads_gpio1o[2];
3142         libresocsim_libresoc_constraintmanager_gpio_o[11] <= gpio1_pads_gpio1o[3];
3143         libresocsim_libresoc_constraintmanager_gpio_o[12] <= gpio1_pads_gpio1o[4];
3144         libresocsim_libresoc_constraintmanager_gpio_o[13] <= gpio1_pads_gpio1o[5];
3145         libresocsim_libresoc_constraintmanager_gpio_o[14] <= gpio1_pads_gpio1o[6];
3146         libresocsim_libresoc_constraintmanager_gpio_o[15] <= gpio1_pads_gpio1o[7];
3147 end
3148 always @(*) begin
3149         libresocsim_libresoc_constraintmanager_gpio_oe <= 16'd0;
3150         libresocsim_libresoc_constraintmanager_gpio_oe[0] <= gpio0_pads_gpio0oe[0];
3151         libresocsim_libresoc_constraintmanager_gpio_oe[1] <= gpio0_pads_gpio0oe[1];
3152         libresocsim_libresoc_constraintmanager_gpio_oe[2] <= gpio0_pads_gpio0oe[2];
3153         libresocsim_libresoc_constraintmanager_gpio_oe[3] <= gpio0_pads_gpio0oe[3];
3154         libresocsim_libresoc_constraintmanager_gpio_oe[4] <= gpio0_pads_gpio0oe[4];
3155         libresocsim_libresoc_constraintmanager_gpio_oe[5] <= gpio0_pads_gpio0oe[5];
3156         libresocsim_libresoc_constraintmanager_gpio_oe[6] <= gpio0_pads_gpio0oe[6];
3157         libresocsim_libresoc_constraintmanager_gpio_oe[7] <= gpio0_pads_gpio0oe[7];
3158         libresocsim_libresoc_constraintmanager_gpio_oe[8] <= gpio1_pads_gpio1oe[0];
3159         libresocsim_libresoc_constraintmanager_gpio_oe[9] <= gpio1_pads_gpio1oe[1];
3160         libresocsim_libresoc_constraintmanager_gpio_oe[10] <= gpio1_pads_gpio1oe[2];
3161         libresocsim_libresoc_constraintmanager_gpio_oe[11] <= gpio1_pads_gpio1oe[3];
3162         libresocsim_libresoc_constraintmanager_gpio_oe[12] <= gpio1_pads_gpio1oe[4];
3163         libresocsim_libresoc_constraintmanager_gpio_oe[13] <= gpio1_pads_gpio1oe[5];
3164         libresocsim_libresoc_constraintmanager_gpio_oe[14] <= gpio1_pads_gpio1oe[6];
3165         libresocsim_libresoc_constraintmanager_gpio_oe[15] <= gpio1_pads_gpio1oe[7];
3166 end
3167 assign libresocsim_libresoc_constraintmanager_i2c_scl = i2c_scl_1;
3168 assign libresocsim_libresoc_constraintmanager_i2c_sda_oe = i2c_oe;
3169 assign libresocsim_libresoc_constraintmanager_i2c_sda_o = i2c_sda0;
3170 assign i2c_sda1 = libresocsim_libresoc_constraintmanager_i2c_sda_i;
3171 always @(*) begin
3172         libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0;
3173         libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0;
3174         libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0;
3175         libresocsim_libresocsim_wishbone_dat_r <= 32'd0;
3176         libresocsim_next_state <= 2'd0;
3177         libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= 8'd0;
3178         libresocsim_libresocsim_wishbone_ack <= 1'd0;
3179         libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd0;
3180         libresocsim_libresocsim_adr_libresocsim_next_value1 <= 13'd0;
3181         libresocsim_next_state <= libresocsim_state;
3182         case (libresocsim_state)
3183                 1'd1: begin
3184                         libresocsim_libresocsim_adr_libresocsim_next_value1 <= 1'd0;
3185                         libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1;
3186                         libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0;
3187                         libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1;
3188                         libresocsim_next_state <= 2'd2;
3189                 end
3190                 2'd2: begin
3191                         libresocsim_libresocsim_wishbone_ack <= 1'd1;
3192                         libresocsim_libresocsim_wishbone_dat_r <= libresocsim_libresocsim_dat_r;
3193                         libresocsim_next_state <= 1'd0;
3194                 end
3195                 default: begin
3196                         libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= libresocsim_libresocsim_wishbone_dat_w;
3197                         libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd1;
3198                         if ((libresocsim_libresocsim_wishbone_cyc & libresocsim_libresocsim_wishbone_stb)) begin
3199                                 libresocsim_libresocsim_adr_libresocsim_next_value1 <= libresocsim_libresocsim_wishbone_adr;
3200                                 libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1;
3201                                 libresocsim_libresocsim_we_libresocsim_next_value2 <= (libresocsim_libresocsim_wishbone_we & (libresocsim_libresocsim_wishbone_sel != 1'd0));
3202                                 libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1;
3203                                 libresocsim_next_state <= 1'd1;
3204                         end
3205                 end
3206         endcase
3207 end
3208 assign libresocsim_shared_adr = rhs_array_muxed24;
3209 assign libresocsim_shared_dat_w = rhs_array_muxed25;
3210 assign libresocsim_shared_sel = rhs_array_muxed26;
3211 assign libresocsim_shared_cyc = rhs_array_muxed27;
3212 assign libresocsim_shared_stb = rhs_array_muxed28;
3213 assign libresocsim_shared_we = rhs_array_muxed29;
3214 assign libresocsim_shared_cti = rhs_array_muxed30;
3215 assign libresocsim_shared_bte = rhs_array_muxed31;
3216 assign libresocsim_interface0_converted_interface_dat_r = libresocsim_shared_dat_r;
3217 assign libresocsim_interface1_converted_interface_dat_r = libresocsim_shared_dat_r;
3218 assign libresocsim_libresoc_jtag_wb_dat_r = libresocsim_shared_dat_r;
3219 assign libresocsim_interface0_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd0));
3220 assign libresocsim_interface1_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd1));
3221 assign libresocsim_libresoc_jtag_wb_ack = (libresocsim_shared_ack & (libresocsim_grant == 2'd2));
3222 assign libresocsim_interface0_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd0));
3223 assign libresocsim_interface1_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd1));
3224 assign libresocsim_libresoc_jtag_wb_err = (libresocsim_shared_err & (libresocsim_grant == 2'd2));
3225 assign libresocsim_request = {libresocsim_libresoc_jtag_wb_cyc, libresocsim_interface1_converted_interface_cyc, libresocsim_interface0_converted_interface_cyc};
3226 always @(*) begin
3227         libresocsim_slave_sel <= 10'd0;
3228         libresocsim_slave_sel[0] <= (libresocsim_shared_adr[29:5] == 1'd0);
3229         libresocsim_slave_sel[1] <= (libresocsim_shared_adr[29:5] == 4'd14);
3230         libresocsim_slave_sel[2] <= (libresocsim_shared_adr[29:3] == 27'd100665344);
3231         libresocsim_slave_sel[3] <= (libresocsim_shared_adr[29:10] == 20'd786449);
3232         libresocsim_slave_sel[4] <= (libresocsim_shared_adr[29:10] == 1'd1);
3233         libresocsim_slave_sel[5] <= (libresocsim_shared_adr[29:10] == 2'd2);
3234         libresocsim_slave_sel[6] <= (libresocsim_shared_adr[29:10] == 2'd3);
3235         libresocsim_slave_sel[7] <= (libresocsim_shared_adr[29:10] == 3'd4);
3236         libresocsim_slave_sel[8] <= (libresocsim_shared_adr[29:23] == 7'd72);
3237         libresocsim_slave_sel[9] <= (libresocsim_shared_adr[29:13] == 17'd98304);
3238 end
3239 assign libresocsim_ram_bus_adr = libresocsim_shared_adr;
3240 assign libresocsim_ram_bus_dat_w = libresocsim_shared_dat_w;
3241 assign libresocsim_ram_bus_sel = libresocsim_shared_sel;
3242 assign libresocsim_ram_bus_stb = libresocsim_shared_stb;
3243 assign libresocsim_ram_bus_we = libresocsim_shared_we;
3244 assign libresocsim_ram_bus_cti = libresocsim_shared_cti;
3245 assign libresocsim_ram_bus_bte = libresocsim_shared_bte;
3246 assign ram_bus_ram_bus_adr = libresocsim_shared_adr;
3247 assign ram_bus_ram_bus_dat_w = libresocsim_shared_dat_w;
3248 assign ram_bus_ram_bus_sel = libresocsim_shared_sel;
3249 assign ram_bus_ram_bus_stb = libresocsim_shared_stb;
3250 assign ram_bus_ram_bus_we = libresocsim_shared_we;
3251 assign ram_bus_ram_bus_cti = libresocsim_shared_cti;
3252 assign ram_bus_ram_bus_bte = libresocsim_shared_bte;
3253 assign libresocsim_libresoc_xics_icp_adr = libresocsim_shared_adr;
3254 assign libresocsim_libresoc_xics_icp_dat_w = libresocsim_shared_dat_w;
3255 assign libresocsim_libresoc_xics_icp_sel = libresocsim_shared_sel;
3256 assign libresocsim_libresoc_xics_icp_stb = libresocsim_shared_stb;
3257 assign libresocsim_libresoc_xics_icp_we = libresocsim_shared_we;
3258 assign libresocsim_libresoc_xics_icp_cti = libresocsim_shared_cti;
3259 assign libresocsim_libresoc_xics_icp_bte = libresocsim_shared_bte;
3260 assign libresocsim_libresoc_xics_ics_adr = libresocsim_shared_adr;
3261 assign libresocsim_libresoc_xics_ics_dat_w = libresocsim_shared_dat_w;
3262 assign libresocsim_libresoc_xics_ics_sel = libresocsim_shared_sel;
3263 assign libresocsim_libresoc_xics_ics_stb = libresocsim_shared_stb;
3264 assign libresocsim_libresoc_xics_ics_we = libresocsim_shared_we;
3265 assign libresocsim_libresoc_xics_ics_cti = libresocsim_shared_cti;
3266 assign libresocsim_libresoc_xics_ics_bte = libresocsim_shared_bte;
3267 assign interface0_converted_interface_adr = libresocsim_shared_adr;
3268 assign interface0_converted_interface_dat_w = libresocsim_shared_dat_w;
3269 assign interface0_converted_interface_sel = libresocsim_shared_sel;
3270 assign interface0_converted_interface_stb = libresocsim_shared_stb;
3271 assign interface0_converted_interface_we = libresocsim_shared_we;
3272 assign interface0_converted_interface_cti = libresocsim_shared_cti;
3273 assign interface0_converted_interface_bte = libresocsim_shared_bte;
3274 assign interface1_converted_interface_adr = libresocsim_shared_adr;
3275 assign interface1_converted_interface_dat_w = libresocsim_shared_dat_w;
3276 assign interface1_converted_interface_sel = libresocsim_shared_sel;
3277 assign interface1_converted_interface_stb = libresocsim_shared_stb;
3278 assign interface1_converted_interface_we = libresocsim_shared_we;
3279 assign interface1_converted_interface_cti = libresocsim_shared_cti;
3280 assign interface1_converted_interface_bte = libresocsim_shared_bte;
3281 assign interface2_converted_interface_adr = libresocsim_shared_adr;
3282 assign interface2_converted_interface_dat_w = libresocsim_shared_dat_w;
3283 assign interface2_converted_interface_sel = libresocsim_shared_sel;
3284 assign interface2_converted_interface_stb = libresocsim_shared_stb;
3285 assign interface2_converted_interface_we = libresocsim_shared_we;
3286 assign interface2_converted_interface_cti = libresocsim_shared_cti;
3287 assign interface2_converted_interface_bte = libresocsim_shared_bte;
3288 assign interface3_converted_interface_adr = libresocsim_shared_adr;
3289 assign interface3_converted_interface_dat_w = libresocsim_shared_dat_w;
3290 assign interface3_converted_interface_sel = libresocsim_shared_sel;
3291 assign interface3_converted_interface_stb = libresocsim_shared_stb;
3292 assign interface3_converted_interface_we = libresocsim_shared_we;
3293 assign interface3_converted_interface_cti = libresocsim_shared_cti;
3294 assign interface3_converted_interface_bte = libresocsim_shared_bte;
3295 assign wb_sdram_adr = libresocsim_shared_adr;
3296 assign wb_sdram_dat_w = libresocsim_shared_dat_w;
3297 assign wb_sdram_sel = libresocsim_shared_sel;
3298 assign wb_sdram_stb = libresocsim_shared_stb;
3299 assign wb_sdram_we = libresocsim_shared_we;
3300 assign wb_sdram_cti = libresocsim_shared_cti;
3301 assign wb_sdram_bte = libresocsim_shared_bte;
3302 assign libresocsim_libresocsim_wishbone_adr = libresocsim_shared_adr;
3303 assign libresocsim_libresocsim_wishbone_dat_w = libresocsim_shared_dat_w;
3304 assign libresocsim_libresocsim_wishbone_sel = libresocsim_shared_sel;
3305 assign libresocsim_libresocsim_wishbone_stb = libresocsim_shared_stb;
3306 assign libresocsim_libresocsim_wishbone_we = libresocsim_shared_we;
3307 assign libresocsim_libresocsim_wishbone_cti = libresocsim_shared_cti;
3308 assign libresocsim_libresocsim_wishbone_bte = libresocsim_shared_bte;
3309 assign libresocsim_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[0]);
3310 assign ram_bus_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[1]);
3311 assign libresocsim_libresoc_xics_icp_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[2]);
3312 assign libresocsim_libresoc_xics_ics_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[3]);
3313 assign interface0_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[4]);
3314 assign interface1_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[5]);
3315 assign interface2_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[6]);
3316 assign interface3_converted_interface_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[7]);
3317 assign wb_sdram_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[8]);
3318 assign libresocsim_libresocsim_wishbone_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[9]);
3319 assign libresocsim_shared_err = (((((((((libresocsim_ram_bus_err | ram_bus_ram_bus_err) | libresocsim_libresoc_xics_icp_err) | libresocsim_libresoc_xics_ics_err) | interface0_converted_interface_err) | interface1_converted_interface_err) | interface2_converted_interface_err) | interface3_converted_interface_err) | wb_sdram_err) | libresocsim_libresocsim_wishbone_err);
3320 assign libresocsim_wait = ((libresocsim_shared_stb & libresocsim_shared_cyc) & (~libresocsim_shared_ack));
3321 always @(*) begin
3322         libresocsim_error <= 1'd0;
3323         libresocsim_shared_dat_r <= 32'd0;
3324         libresocsim_shared_ack <= 1'd0;
3325         libresocsim_shared_ack <= (((((((((libresocsim_ram_bus_ack | ram_bus_ram_bus_ack) | libresocsim_libresoc_xics_icp_ack) | libresocsim_libresoc_xics_ics_ack) | interface0_converted_interface_ack) | interface1_converted_interface_ack) | interface2_converted_interface_ack) | interface3_converted_interface_ack) | wb_sdram_ack) | libresocsim_libresocsim_wishbone_ack);
3326         libresocsim_shared_dat_r <= (((((((((({32{libresocsim_slave_sel_r[0]}} & libresocsim_ram_bus_dat_r) | ({32{libresocsim_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{libresocsim_slave_sel_r[2]}} & libresocsim_libresoc_xics_icp_dat_r)) | ({32{libresocsim_slave_sel_r[3]}} & libresocsim_libresoc_xics_ics_dat_r)) | ({32{libresocsim_slave_sel_r[4]}} & interface0_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[5]}} & interface1_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[6]}} & interface2_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[7]}} & interface3_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[8]}} & wb_sdram_dat_r)) | ({32{libresocsim_slave_sel_r[9]}} & libresocsim_libresocsim_wishbone_dat_r));
3327         if (libresocsim_done) begin
3328                 libresocsim_shared_dat_r <= 32'd4294967295;
3329                 libresocsim_shared_ack <= 1'd1;
3330                 libresocsim_error <= 1'd1;
3331         end
3332 end
3333 assign libresocsim_done = (libresocsim_count == 1'd0);
3334 assign libresocsim_csrbank0_sel = (libresocsim_interface0_bank_bus_adr[12:9] == 1'd0);
3335 assign libresocsim_csrbank0_reset0_r = libresocsim_interface0_bank_bus_dat_w[0];
3336 assign libresocsim_csrbank0_reset0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0));
3337 assign libresocsim_csrbank0_reset0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0));
3338 assign libresocsim_csrbank0_scratch3_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3339 assign libresocsim_csrbank0_scratch3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1));
3340 assign libresocsim_csrbank0_scratch3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1));
3341 assign libresocsim_csrbank0_scratch2_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3342 assign libresocsim_csrbank0_scratch2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2));
3343 assign libresocsim_csrbank0_scratch2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2));
3344 assign libresocsim_csrbank0_scratch1_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3345 assign libresocsim_csrbank0_scratch1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3));
3346 assign libresocsim_csrbank0_scratch1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3));
3347 assign libresocsim_csrbank0_scratch0_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3348 assign libresocsim_csrbank0_scratch0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4));
3349 assign libresocsim_csrbank0_scratch0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4));
3350 assign libresocsim_csrbank0_bus_errors3_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3351 assign libresocsim_csrbank0_bus_errors3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5));
3352 assign libresocsim_csrbank0_bus_errors3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5));
3353 assign libresocsim_csrbank0_bus_errors2_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3354 assign libresocsim_csrbank0_bus_errors2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6));
3355 assign libresocsim_csrbank0_bus_errors2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6));
3356 assign libresocsim_csrbank0_bus_errors1_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3357 assign libresocsim_csrbank0_bus_errors1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7));
3358 assign libresocsim_csrbank0_bus_errors1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7));
3359 assign libresocsim_csrbank0_bus_errors0_r = libresocsim_interface0_bank_bus_dat_w[7:0];
3360 assign libresocsim_csrbank0_bus_errors0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8));
3361 assign libresocsim_csrbank0_bus_errors0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8));
3362 assign libresocsim_csrbank0_reset0_w = libresocsim_reset_storage;
3363 assign libresocsim_csrbank0_scratch3_w = libresocsim_scratch_storage[31:24];
3364 assign libresocsim_csrbank0_scratch2_w = libresocsim_scratch_storage[23:16];
3365 assign libresocsim_csrbank0_scratch1_w = libresocsim_scratch_storage[15:8];
3366 assign libresocsim_csrbank0_scratch0_w = libresocsim_scratch_storage[7:0];
3367 assign libresocsim_csrbank0_bus_errors3_w = libresocsim_bus_errors_status[31:24];
3368 assign libresocsim_csrbank0_bus_errors2_w = libresocsim_bus_errors_status[23:16];
3369 assign libresocsim_csrbank0_bus_errors1_w = libresocsim_bus_errors_status[15:8];
3370 assign libresocsim_csrbank0_bus_errors0_w = libresocsim_bus_errors_status[7:0];
3371 assign libresocsim_bus_errors_we = libresocsim_csrbank0_bus_errors0_we;
3372 assign libresocsim_csrbank1_sel = (libresocsim_interface1_bank_bus_adr[12:9] == 3'd6);
3373 assign libresocsim_csrbank1_oe0_r = libresocsim_interface1_bank_bus_dat_w[7:0];
3374 assign libresocsim_csrbank1_oe0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0));
3375 assign libresocsim_csrbank1_oe0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0));
3376 assign libresocsim_csrbank1_in_r = libresocsim_interface1_bank_bus_dat_w[7:0];
3377 assign libresocsim_csrbank1_in_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1));
3378 assign libresocsim_csrbank1_in_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1));
3379 assign libresocsim_csrbank1_out0_r = libresocsim_interface1_bank_bus_dat_w[7:0];
3380 assign libresocsim_csrbank1_out0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2));
3381 assign libresocsim_csrbank1_out0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2));
3382 assign libresocsim_csrbank1_oe0_w = gpio0_oe_storage[7:0];
3383 assign libresocsim_csrbank1_in_w = gpio0_status[7:0];
3384 assign gpio0_we = libresocsim_csrbank1_in_we;
3385 assign libresocsim_csrbank1_out0_w = gpio0_out_storage[7:0];
3386 assign libresocsim_csrbank2_sel = (libresocsim_interface2_bank_bus_adr[12:9] == 3'd7);
3387 assign libresocsim_csrbank2_oe0_r = libresocsim_interface2_bank_bus_dat_w[7:0];
3388 assign libresocsim_csrbank2_oe0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0));
3389 assign libresocsim_csrbank2_oe0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0));
3390 assign libresocsim_csrbank2_in_r = libresocsim_interface2_bank_bus_dat_w[7:0];
3391 assign libresocsim_csrbank2_in_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1));
3392 assign libresocsim_csrbank2_in_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1));
3393 assign libresocsim_csrbank2_out0_r = libresocsim_interface2_bank_bus_dat_w[7:0];
3394 assign libresocsim_csrbank2_out0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2));
3395 assign libresocsim_csrbank2_out0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2));
3396 assign libresocsim_csrbank2_oe0_w = gpio1_oe_storage[7:0];
3397 assign libresocsim_csrbank2_in_w = gpio1_status[7:0];
3398 assign gpio1_we = libresocsim_csrbank2_in_we;
3399 assign libresocsim_csrbank2_out0_w = gpio1_out_storage[7:0];
3400 assign libresocsim_csrbank3_sel = (libresocsim_interface3_bank_bus_adr[12:9] == 4'd8);
3401 assign libresocsim_csrbank3_w0_r = libresocsim_interface3_bank_bus_dat_w[2:0];
3402 assign libresocsim_csrbank3_w0_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0));
3403 assign libresocsim_csrbank3_w0_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0));
3404 assign libresocsim_csrbank3_r_r = libresocsim_interface3_bank_bus_dat_w[0];
3405 assign libresocsim_csrbank3_r_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1));
3406 assign libresocsim_csrbank3_r_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1));
3407 assign i2c_scl_1 = i2c_storage[0];
3408 assign i2c_oe = i2c_storage[1];
3409 assign i2c_sda0 = i2c_storage[2];
3410 assign libresocsim_csrbank3_w0_w = i2c_storage[2:0];
3411 assign i2c_status = i2c_sda1;
3412 assign libresocsim_csrbank3_r_w = i2c_status;
3413 assign i2c_we = libresocsim_csrbank3_r_we;
3414 assign libresocsim_csrbank4_sel = (libresocsim_interface4_bank_bus_adr[12:9] == 2'd3);
3415 assign libresocsim_csrbank4_dfii_control0_r = libresocsim_interface4_bank_bus_dat_w[3:0];
3416 assign libresocsim_csrbank4_dfii_control0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0));
3417 assign libresocsim_csrbank4_dfii_control0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0));
3418 assign libresocsim_csrbank4_dfii_pi0_command0_r = libresocsim_interface4_bank_bus_dat_w[5:0];
3419 assign libresocsim_csrbank4_dfii_pi0_command0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1));
3420 assign libresocsim_csrbank4_dfii_pi0_command0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1));
3421 assign sdram_command_issue_r = libresocsim_interface4_bank_bus_dat_w[0];
3422 assign sdram_command_issue_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2));
3423 assign sdram_command_issue_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2));
3424 assign libresocsim_csrbank4_dfii_pi0_address1_r = libresocsim_interface4_bank_bus_dat_w[4:0];
3425 assign libresocsim_csrbank4_dfii_pi0_address1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3));
3426 assign libresocsim_csrbank4_dfii_pi0_address1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3));
3427 assign libresocsim_csrbank4_dfii_pi0_address0_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3428 assign libresocsim_csrbank4_dfii_pi0_address0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4));
3429 assign libresocsim_csrbank4_dfii_pi0_address0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4));
3430 assign libresocsim_csrbank4_dfii_pi0_baddress0_r = libresocsim_interface4_bank_bus_dat_w[1:0];
3431 assign libresocsim_csrbank4_dfii_pi0_baddress0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5));
3432 assign libresocsim_csrbank4_dfii_pi0_baddress0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5));
3433 assign libresocsim_csrbank4_dfii_pi0_wrdata1_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3434 assign libresocsim_csrbank4_dfii_pi0_wrdata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6));
3435 assign libresocsim_csrbank4_dfii_pi0_wrdata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6));
3436 assign libresocsim_csrbank4_dfii_pi0_wrdata0_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3437 assign libresocsim_csrbank4_dfii_pi0_wrdata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7));
3438 assign libresocsim_csrbank4_dfii_pi0_wrdata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7));
3439 assign libresocsim_csrbank4_dfii_pi0_rddata1_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3440 assign libresocsim_csrbank4_dfii_pi0_rddata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8));
3441 assign libresocsim_csrbank4_dfii_pi0_rddata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8));
3442 assign libresocsim_csrbank4_dfii_pi0_rddata0_r = libresocsim_interface4_bank_bus_dat_w[7:0];
3443 assign libresocsim_csrbank4_dfii_pi0_rddata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9));
3444 assign libresocsim_csrbank4_dfii_pi0_rddata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9));
3445 assign sdram_sel = sdram_storage[0];
3446 assign sdram_cke_1 = sdram_storage[1];
3447 assign sdram_odt = sdram_storage[2];
3448 assign sdram_reset_n = sdram_storage[3];
3449 assign libresocsim_csrbank4_dfii_control0_w = sdram_storage[3:0];
3450 assign libresocsim_csrbank4_dfii_pi0_command0_w = sdram_command_storage[5:0];
3451 assign libresocsim_csrbank4_dfii_pi0_address1_w = sdram_address_storage[12:8];
3452 assign libresocsim_csrbank4_dfii_pi0_address0_w = sdram_address_storage[7:0];
3453 assign libresocsim_csrbank4_dfii_pi0_baddress0_w = sdram_baddress_storage[1:0];
3454 assign libresocsim_csrbank4_dfii_pi0_wrdata1_w = sdram_wrdata_storage[15:8];
3455 assign libresocsim_csrbank4_dfii_pi0_wrdata0_w = sdram_wrdata_storage[7:0];
3456 assign libresocsim_csrbank4_dfii_pi0_rddata1_w = sdram_status[15:8];
3457 assign libresocsim_csrbank4_dfii_pi0_rddata0_w = sdram_status[7:0];
3458 assign sdram_we = libresocsim_csrbank4_dfii_pi0_rddata0_we;
3459 assign libresocsim_csrbank5_sel = (libresocsim_interface5_bank_bus_adr[12:9] == 2'd2);
3460 assign libresocsim_csrbank5_load3_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3461 assign libresocsim_csrbank5_load3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0));
3462 assign libresocsim_csrbank5_load3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0));
3463 assign libresocsim_csrbank5_load2_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3464 assign libresocsim_csrbank5_load2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1));
3465 assign libresocsim_csrbank5_load2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1));
3466 assign libresocsim_csrbank5_load1_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3467 assign libresocsim_csrbank5_load1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2));
3468 assign libresocsim_csrbank5_load1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2));
3469 assign libresocsim_csrbank5_load0_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3470 assign libresocsim_csrbank5_load0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3));
3471 assign libresocsim_csrbank5_load0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3));
3472 assign libresocsim_csrbank5_reload3_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3473 assign libresocsim_csrbank5_reload3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4));
3474 assign libresocsim_csrbank5_reload3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4));
3475 assign libresocsim_csrbank5_reload2_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3476 assign libresocsim_csrbank5_reload2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5));
3477 assign libresocsim_csrbank5_reload2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5));
3478 assign libresocsim_csrbank5_reload1_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3479 assign libresocsim_csrbank5_reload1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6));
3480 assign libresocsim_csrbank5_reload1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6));
3481 assign libresocsim_csrbank5_reload0_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3482 assign libresocsim_csrbank5_reload0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7));
3483 assign libresocsim_csrbank5_reload0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7));
3484 assign libresocsim_csrbank5_en0_r = libresocsim_interface5_bank_bus_dat_w[0];
3485 assign libresocsim_csrbank5_en0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8));
3486 assign libresocsim_csrbank5_en0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8));
3487 assign libresocsim_csrbank5_update_value0_r = libresocsim_interface5_bank_bus_dat_w[0];
3488 assign libresocsim_csrbank5_update_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9));
3489 assign libresocsim_csrbank5_update_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9));
3490 assign libresocsim_csrbank5_value3_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3491 assign libresocsim_csrbank5_value3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10));
3492 assign libresocsim_csrbank5_value3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10));
3493 assign libresocsim_csrbank5_value2_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3494 assign libresocsim_csrbank5_value2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11));
3495 assign libresocsim_csrbank5_value2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11));
3496 assign libresocsim_csrbank5_value1_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3497 assign libresocsim_csrbank5_value1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12));
3498 assign libresocsim_csrbank5_value1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12));
3499 assign libresocsim_csrbank5_value0_r = libresocsim_interface5_bank_bus_dat_w[7:0];
3500 assign libresocsim_csrbank5_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13));
3501 assign libresocsim_csrbank5_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13));
3502 assign libresocsim_eventmanager_status_r = libresocsim_interface5_bank_bus_dat_w[0];
3503 assign libresocsim_eventmanager_status_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14));
3504 assign libresocsim_eventmanager_status_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14));
3505 assign libresocsim_eventmanager_pending_r = libresocsim_interface5_bank_bus_dat_w[0];
3506 assign libresocsim_eventmanager_pending_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15));
3507 assign libresocsim_eventmanager_pending_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15));
3508 assign libresocsim_csrbank5_ev_enable0_r = libresocsim_interface5_bank_bus_dat_w[0];
3509 assign libresocsim_csrbank5_ev_enable0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16));
3510 assign libresocsim_csrbank5_ev_enable0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16));
3511 assign libresocsim_csrbank5_load3_w = libresocsim_load_storage[31:24];
3512 assign libresocsim_csrbank5_load2_w = libresocsim_load_storage[23:16];
3513 assign libresocsim_csrbank5_load1_w = libresocsim_load_storage[15:8];
3514 assign libresocsim_csrbank5_load0_w = libresocsim_load_storage[7:0];
3515 assign libresocsim_csrbank5_reload3_w = libresocsim_reload_storage[31:24];
3516 assign libresocsim_csrbank5_reload2_w = libresocsim_reload_storage[23:16];
3517 assign libresocsim_csrbank5_reload1_w = libresocsim_reload_storage[15:8];
3518 assign libresocsim_csrbank5_reload0_w = libresocsim_reload_storage[7:0];
3519 assign libresocsim_csrbank5_en0_w = libresocsim_en_storage;
3520 assign libresocsim_csrbank5_update_value0_w = libresocsim_update_value_storage;
3521 assign libresocsim_csrbank5_value3_w = libresocsim_value_status[31:24];
3522 assign libresocsim_csrbank5_value2_w = libresocsim_value_status[23:16];
3523 assign libresocsim_csrbank5_value1_w = libresocsim_value_status[15:8];
3524 assign libresocsim_csrbank5_value0_w = libresocsim_value_status[7:0];
3525 assign libresocsim_value_we = libresocsim_csrbank5_value0_we;
3526 assign libresocsim_csrbank5_ev_enable0_w = libresocsim_eventmanager_storage;
3527 assign libresocsim_csrbank6_sel = (libresocsim_interface6_bank_bus_adr[12:9] == 3'd5);
3528 assign rxtx_r = libresocsim_interface6_bank_bus_dat_w[7:0];
3529 assign rxtx_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0));
3530 assign rxtx_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0));
3531 assign libresocsim_csrbank6_txfull_r = libresocsim_interface6_bank_bus_dat_w[0];
3532 assign libresocsim_csrbank6_txfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1));
3533 assign libresocsim_csrbank6_txfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1));
3534 assign libresocsim_csrbank6_rxempty_r = libresocsim_interface6_bank_bus_dat_w[0];
3535 assign libresocsim_csrbank6_rxempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2));
3536 assign libresocsim_csrbank6_rxempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2));
3537 assign eventmanager_status_r = libresocsim_interface6_bank_bus_dat_w[1:0];
3538 assign eventmanager_status_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3));
3539 assign eventmanager_status_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3));
3540 assign eventmanager_pending_r = libresocsim_interface6_bank_bus_dat_w[1:0];
3541 assign eventmanager_pending_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4));
3542 assign eventmanager_pending_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4));
3543 assign libresocsim_csrbank6_ev_enable0_r = libresocsim_interface6_bank_bus_dat_w[1:0];
3544 assign libresocsim_csrbank6_ev_enable0_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5));
3545 assign libresocsim_csrbank6_ev_enable0_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5));
3546 assign libresocsim_csrbank6_txempty_r = libresocsim_interface6_bank_bus_dat_w[0];
3547 assign libresocsim_csrbank6_txempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6));
3548 assign libresocsim_csrbank6_txempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6));
3549 assign libresocsim_csrbank6_rxfull_r = libresocsim_interface6_bank_bus_dat_w[0];
3550 assign libresocsim_csrbank6_rxfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7));
3551 assign libresocsim_csrbank6_rxfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7));
3552 assign libresocsim_csrbank6_txfull_w = txfull_status;
3553 assign txfull_we = libresocsim_csrbank6_txfull_we;
3554 assign libresocsim_csrbank6_rxempty_w = rxempty_status;
3555 assign rxempty_we = libresocsim_csrbank6_rxempty_we;
3556 assign libresocsim_csrbank6_ev_enable0_w = eventmanager_storage[1:0];
3557 assign libresocsim_csrbank6_txempty_w = txempty_status;
3558 assign txempty_we = libresocsim_csrbank6_txempty_we;
3559 assign libresocsim_csrbank6_rxfull_w = rxfull_status;
3560 assign rxfull_we = libresocsim_csrbank6_rxfull_we;
3561 assign libresocsim_csrbank7_sel = (libresocsim_interface7_bank_bus_adr[12:9] == 3'd4);
3562 assign libresocsim_csrbank7_tuning_word3_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3563 assign libresocsim_csrbank7_tuning_word3_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0));
3564 assign libresocsim_csrbank7_tuning_word3_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0));
3565 assign libresocsim_csrbank7_tuning_word2_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3566 assign libresocsim_csrbank7_tuning_word2_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1));
3567 assign libresocsim_csrbank7_tuning_word2_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1));
3568 assign libresocsim_csrbank7_tuning_word1_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3569 assign libresocsim_csrbank7_tuning_word1_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2));
3570 assign libresocsim_csrbank7_tuning_word1_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2));
3571 assign libresocsim_csrbank7_tuning_word0_r = libresocsim_interface7_bank_bus_dat_w[7:0];
3572 assign libresocsim_csrbank7_tuning_word0_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3));
3573 assign libresocsim_csrbank7_tuning_word0_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3));
3574 assign libresocsim_csrbank7_tuning_word3_w = uart_phy_storage[31:24];
3575 assign libresocsim_csrbank7_tuning_word2_w = uart_phy_storage[23:16];
3576 assign libresocsim_csrbank7_tuning_word1_w = uart_phy_storage[15:8];
3577 assign libresocsim_csrbank7_tuning_word0_w = uart_phy_storage[7:0];
3578 assign libresocsim_csr_interconnect_adr = libresocsim_libresocsim_adr;
3579 assign libresocsim_csr_interconnect_we = libresocsim_libresocsim_we;
3580 assign libresocsim_csr_interconnect_dat_w = libresocsim_libresocsim_dat_w;
3581 assign libresocsim_libresocsim_dat_r = libresocsim_csr_interconnect_dat_r;
3582 assign libresocsim_interface0_bank_bus_adr = libresocsim_csr_interconnect_adr;
3583 assign libresocsim_interface1_bank_bus_adr = libresocsim_csr_interconnect_adr;
3584 assign libresocsim_interface2_bank_bus_adr = libresocsim_csr_interconnect_adr;
3585 assign libresocsim_interface3_bank_bus_adr = libresocsim_csr_interconnect_adr;
3586 assign libresocsim_interface4_bank_bus_adr = libresocsim_csr_interconnect_adr;
3587 assign libresocsim_interface5_bank_bus_adr = libresocsim_csr_interconnect_adr;
3588 assign libresocsim_interface6_bank_bus_adr = libresocsim_csr_interconnect_adr;
3589 assign libresocsim_interface7_bank_bus_adr = libresocsim_csr_interconnect_adr;
3590 assign libresocsim_interface0_bank_bus_we = libresocsim_csr_interconnect_we;
3591 assign libresocsim_interface1_bank_bus_we = libresocsim_csr_interconnect_we;
3592 assign libresocsim_interface2_bank_bus_we = libresocsim_csr_interconnect_we;
3593 assign libresocsim_interface3_bank_bus_we = libresocsim_csr_interconnect_we;
3594 assign libresocsim_interface4_bank_bus_we = libresocsim_csr_interconnect_we;
3595 assign libresocsim_interface5_bank_bus_we = libresocsim_csr_interconnect_we;
3596 assign libresocsim_interface6_bank_bus_we = libresocsim_csr_interconnect_we;
3597 assign libresocsim_interface7_bank_bus_we = libresocsim_csr_interconnect_we;
3598 assign libresocsim_interface0_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3599 assign libresocsim_interface1_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3600 assign libresocsim_interface2_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3601 assign libresocsim_interface3_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3602 assign libresocsim_interface4_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3603 assign libresocsim_interface5_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3604 assign libresocsim_interface6_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3605 assign libresocsim_interface7_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
3606 assign libresocsim_csr_interconnect_dat_r = (((((((libresocsim_interface0_bank_bus_dat_r | libresocsim_interface1_bank_bus_dat_r) | libresocsim_interface2_bank_bus_dat_r) | libresocsim_interface3_bank_bus_dat_r) | libresocsim_interface4_bank_bus_dat_r) | libresocsim_interface5_bank_bus_dat_r) | libresocsim_interface6_bank_bus_dat_r) | libresocsim_interface7_bank_bus_dat_r);
3607 always @(*) begin
3608         rhs_array_muxed0 <= 1'd0;
3609         case (sdram_choose_cmd_grant)
3610                 1'd0: begin
3611                         rhs_array_muxed0 <= sdram_choose_cmd_valids[0];
3612                 end
3613                 1'd1: begin
3614                         rhs_array_muxed0 <= sdram_choose_cmd_valids[1];
3615                 end
3616                 2'd2: begin
3617                         rhs_array_muxed0 <= sdram_choose_cmd_valids[2];
3618                 end
3619                 default: begin
3620                         rhs_array_muxed0 <= sdram_choose_cmd_valids[3];
3621                 end
3622         endcase
3623 end
3624 always @(*) begin
3625         rhs_array_muxed1 <= 13'd0;
3626         case (sdram_choose_cmd_grant)
3627                 1'd0: begin
3628                         rhs_array_muxed1 <= sdram_bankmachine0_cmd_payload_a;
3629                 end
3630                 1'd1: begin
3631                         rhs_array_muxed1 <= sdram_bankmachine1_cmd_payload_a;
3632                 end
3633                 2'd2: begin
3634                         rhs_array_muxed1 <= sdram_bankmachine2_cmd_payload_a;
3635                 end
3636                 default: begin
3637                         rhs_array_muxed1 <= sdram_bankmachine3_cmd_payload_a;
3638                 end
3639         endcase
3640 end
3641 always @(*) begin
3642         rhs_array_muxed2 <= 2'd0;
3643         case (sdram_choose_cmd_grant)
3644                 1'd0: begin
3645                         rhs_array_muxed2 <= sdram_bankmachine0_cmd_payload_ba;
3646                 end
3647                 1'd1: begin
3648                         rhs_array_muxed2 <= sdram_bankmachine1_cmd_payload_ba;
3649                 end
3650                 2'd2: begin
3651                         rhs_array_muxed2 <= sdram_bankmachine2_cmd_payload_ba;
3652                 end
3653                 default: begin
3654                         rhs_array_muxed2 <= sdram_bankmachine3_cmd_payload_ba;
3655                 end
3656         endcase
3657 end
3658 always @(*) begin
3659         rhs_array_muxed3 <= 1'd0;
3660         case (sdram_choose_cmd_grant)
3661                 1'd0: begin
3662                         rhs_array_muxed3 <= sdram_bankmachine0_cmd_payload_is_read;
3663                 end
3664                 1'd1: begin
3665                         rhs_array_muxed3 <= sdram_bankmachine1_cmd_payload_is_read;
3666                 end
3667                 2'd2: begin
3668                         rhs_array_muxed3 <= sdram_bankmachine2_cmd_payload_is_read;
3669                 end
3670                 default: begin
3671                         rhs_array_muxed3 <= sdram_bankmachine3_cmd_payload_is_read;
3672                 end
3673         endcase
3674 end
3675 always @(*) begin
3676         rhs_array_muxed4 <= 1'd0;
3677         case (sdram_choose_cmd_grant)
3678                 1'd0: begin
3679                         rhs_array_muxed4 <= sdram_bankmachine0_cmd_payload_is_write;
3680                 end
3681                 1'd1: begin
3682                         rhs_array_muxed4 <= sdram_bankmachine1_cmd_payload_is_write;
3683                 end
3684                 2'd2: begin
3685                         rhs_array_muxed4 <= sdram_bankmachine2_cmd_payload_is_write;
3686                 end
3687                 default: begin
3688                         rhs_array_muxed4 <= sdram_bankmachine3_cmd_payload_is_write;
3689                 end
3690         endcase
3691 end
3692 always @(*) begin
3693         rhs_array_muxed5 <= 1'd0;
3694         case (sdram_choose_cmd_grant)
3695                 1'd0: begin
3696                         rhs_array_muxed5 <= sdram_bankmachine0_cmd_payload_is_cmd;
3697                 end
3698                 1'd1: begin
3699                         rhs_array_muxed5 <= sdram_bankmachine1_cmd_payload_is_cmd;
3700                 end
3701                 2'd2: begin
3702                         rhs_array_muxed5 <= sdram_bankmachine2_cmd_payload_is_cmd;
3703                 end
3704                 default: begin
3705                         rhs_array_muxed5 <= sdram_bankmachine3_cmd_payload_is_cmd;
3706                 end
3707         endcase
3708 end
3709 always @(*) begin
3710         t_array_muxed0 <= 1'd0;
3711         case (sdram_choose_cmd_grant)
3712                 1'd0: begin
3713                         t_array_muxed0 <= sdram_bankmachine0_cmd_payload_cas;
3714                 end
3715                 1'd1: begin
3716                         t_array_muxed0 <= sdram_bankmachine1_cmd_payload_cas;
3717                 end
3718                 2'd2: begin
3719                         t_array_muxed0 <= sdram_bankmachine2_cmd_payload_cas;
3720                 end
3721                 default: begin
3722                         t_array_muxed0 <= sdram_bankmachine3_cmd_payload_cas;
3723                 end
3724         endcase
3725 end
3726 always @(*) begin
3727         t_array_muxed1 <= 1'd0;
3728         case (sdram_choose_cmd_grant)
3729                 1'd0: begin
3730                         t_array_muxed1 <= sdram_bankmachine0_cmd_payload_ras;
3731                 end
3732                 1'd1: begin
3733                         t_array_muxed1 <= sdram_bankmachine1_cmd_payload_ras;
3734                 end
3735                 2'd2: begin
3736                         t_array_muxed1 <= sdram_bankmachine2_cmd_payload_ras;
3737                 end
3738                 default: begin
3739                         t_array_muxed1 <= sdram_bankmachine3_cmd_payload_ras;
3740                 end
3741         endcase
3742 end
3743 always @(*) begin
3744         t_array_muxed2 <= 1'd0;
3745         case (sdram_choose_cmd_grant)
3746                 1'd0: begin
3747                         t_array_muxed2 <= sdram_bankmachine0_cmd_payload_we;
3748                 end
3749                 1'd1: begin
3750                         t_array_muxed2 <= sdram_bankmachine1_cmd_payload_we;
3751                 end
3752                 2'd2: begin
3753                         t_array_muxed2 <= sdram_bankmachine2_cmd_payload_we;
3754                 end
3755                 default: begin
3756                         t_array_muxed2 <= sdram_bankmachine3_cmd_payload_we;
3757                 end
3758         endcase
3759 end
3760 always @(*) begin
3761         rhs_array_muxed6 <= 1'd0;
3762         case (sdram_choose_req_grant)
3763                 1'd0: begin
3764                         rhs_array_muxed6 <= sdram_choose_req_valids[0];
3765                 end
3766                 1'd1: begin
3767                         rhs_array_muxed6 <= sdram_choose_req_valids[1];
3768                 end
3769                 2'd2: begin
3770                         rhs_array_muxed6 <= sdram_choose_req_valids[2];
3771                 end
3772                 default: begin
3773                         rhs_array_muxed6 <= sdram_choose_req_valids[3];
3774                 end
3775         endcase
3776 end
3777 always @(*) begin
3778         rhs_array_muxed7 <= 13'd0;
3779         case (sdram_choose_req_grant)
3780                 1'd0: begin
3781                         rhs_array_muxed7 <= sdram_bankmachine0_cmd_payload_a;
3782                 end
3783                 1'd1: begin
3784                         rhs_array_muxed7 <= sdram_bankmachine1_cmd_payload_a;
3785                 end
3786                 2'd2: begin
3787                         rhs_array_muxed7 <= sdram_bankmachine2_cmd_payload_a;
3788                 end
3789                 default: begin
3790                         rhs_array_muxed7 <= sdram_bankmachine3_cmd_payload_a;
3791                 end
3792         endcase
3793 end
3794 always @(*) begin
3795         rhs_array_muxed8 <= 2'd0;
3796         case (sdram_choose_req_grant)
3797                 1'd0: begin
3798                         rhs_array_muxed8 <= sdram_bankmachine0_cmd_payload_ba;
3799                 end
3800                 1'd1: begin
3801                         rhs_array_muxed8 <= sdram_bankmachine1_cmd_payload_ba;
3802                 end
3803                 2'd2: begin
3804                         rhs_array_muxed8 <= sdram_bankmachine2_cmd_payload_ba;
3805                 end
3806                 default: begin
3807                         rhs_array_muxed8 <= sdram_bankmachine3_cmd_payload_ba;
3808                 end
3809         endcase
3810 end
3811 always @(*) begin
3812         rhs_array_muxed9 <= 1'd0;
3813         case (sdram_choose_req_grant)
3814                 1'd0: begin
3815                         rhs_array_muxed9 <= sdram_bankmachine0_cmd_payload_is_read;
3816                 end
3817                 1'd1: begin
3818                         rhs_array_muxed9 <= sdram_bankmachine1_cmd_payload_is_read;
3819                 end
3820                 2'd2: begin
3821                         rhs_array_muxed9 <= sdram_bankmachine2_cmd_payload_is_read;
3822                 end
3823                 default: begin
3824                         rhs_array_muxed9 <= sdram_bankmachine3_cmd_payload_is_read;
3825                 end
3826         endcase
3827 end
3828 always @(*) begin
3829         rhs_array_muxed10 <= 1'd0;
3830         case (sdram_choose_req_grant)
3831                 1'd0: begin
3832                         rhs_array_muxed10 <= sdram_bankmachine0_cmd_payload_is_write;
3833                 end
3834                 1'd1: begin
3835                         rhs_array_muxed10 <= sdram_bankmachine1_cmd_payload_is_write;
3836                 end
3837                 2'd2: begin
3838                         rhs_array_muxed10 <= sdram_bankmachine2_cmd_payload_is_write;
3839                 end
3840                 default: begin
3841                         rhs_array_muxed10 <= sdram_bankmachine3_cmd_payload_is_write;
3842                 end
3843         endcase
3844 end
3845 always @(*) begin
3846         rhs_array_muxed11 <= 1'd0;
3847         case (sdram_choose_req_grant)
3848                 1'd0: begin
3849                         rhs_array_muxed11 <= sdram_bankmachine0_cmd_payload_is_cmd;
3850                 end
3851                 1'd1: begin
3852                         rhs_array_muxed11 <= sdram_bankmachine1_cmd_payload_is_cmd;
3853                 end
3854                 2'd2: begin
3855                         rhs_array_muxed11 <= sdram_bankmachine2_cmd_payload_is_cmd;
3856                 end
3857                 default: begin
3858                         rhs_array_muxed11 <= sdram_bankmachine3_cmd_payload_is_cmd;
3859                 end
3860         endcase
3861 end
3862 always @(*) begin
3863         t_array_muxed3 <= 1'd0;
3864         case (sdram_choose_req_grant)
3865                 1'd0: begin
3866                         t_array_muxed3 <= sdram_bankmachine0_cmd_payload_cas;
3867                 end
3868                 1'd1: begin
3869                         t_array_muxed3 <= sdram_bankmachine1_cmd_payload_cas;
3870                 end
3871                 2'd2: begin
3872                         t_array_muxed3 <= sdram_bankmachine2_cmd_payload_cas;
3873                 end
3874                 default: begin
3875                         t_array_muxed3 <= sdram_bankmachine3_cmd_payload_cas;
3876                 end
3877         endcase
3878 end
3879 always @(*) begin
3880         t_array_muxed4 <= 1'd0;
3881         case (sdram_choose_req_grant)
3882                 1'd0: begin
3883                         t_array_muxed4 <= sdram_bankmachine0_cmd_payload_ras;
3884                 end
3885                 1'd1: begin
3886                         t_array_muxed4 <= sdram_bankmachine1_cmd_payload_ras;
3887                 end
3888                 2'd2: begin
3889                         t_array_muxed4 <= sdram_bankmachine2_cmd_payload_ras;
3890                 end
3891                 default: begin
3892                         t_array_muxed4 <= sdram_bankmachine3_cmd_payload_ras;
3893                 end
3894         endcase
3895 end
3896 always @(*) begin
3897         t_array_muxed5 <= 1'd0;
3898         case (sdram_choose_req_grant)
3899                 1'd0: begin
3900                         t_array_muxed5 <= sdram_bankmachine0_cmd_payload_we;
3901                 end
3902                 1'd1: begin
3903                         t_array_muxed5 <= sdram_bankmachine1_cmd_payload_we;
3904                 end
3905                 2'd2: begin
3906                         t_array_muxed5 <= sdram_bankmachine2_cmd_payload_we;
3907                 end
3908                 default: begin
3909                         t_array_muxed5 <= sdram_bankmachine3_cmd_payload_we;
3910                 end
3911         endcase
3912 end
3913 always @(*) begin
3914         rhs_array_muxed12 <= 22'd0;
3915         case (subfragments_roundrobin0_grant)
3916                 default: begin
3917                         rhs_array_muxed12 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3918                 end
3919         endcase
3920 end
3921 always @(*) begin
3922         rhs_array_muxed13 <= 1'd0;
3923         case (subfragments_roundrobin0_grant)
3924                 default: begin
3925                         rhs_array_muxed13 <= port_cmd_payload_we;
3926                 end
3927         endcase
3928 end
3929 always @(*) begin
3930         rhs_array_muxed14 <= 1'd0;
3931         case (subfragments_roundrobin0_grant)
3932                 default: begin
3933                         rhs_array_muxed14 <= (((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid);
3934                 end
3935         endcase
3936 end
3937 always @(*) begin
3938         rhs_array_muxed15 <= 22'd0;
3939         case (subfragments_roundrobin1_grant)
3940                 default: begin
3941                         rhs_array_muxed15 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3942                 end
3943         endcase
3944 end
3945 always @(*) begin
3946         rhs_array_muxed16 <= 1'd0;
3947         case (subfragments_roundrobin1_grant)
3948                 default: begin
3949                         rhs_array_muxed16 <= port_cmd_payload_we;
3950                 end
3951         endcase
3952 end
3953 always @(*) begin
3954         rhs_array_muxed17 <= 1'd0;
3955         case (subfragments_roundrobin1_grant)
3956                 default: begin
3957                         rhs_array_muxed17 <= (((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid);
3958                 end
3959         endcase
3960 end
3961 always @(*) begin
3962         rhs_array_muxed18 <= 22'd0;
3963         case (subfragments_roundrobin2_grant)
3964                 default: begin
3965                         rhs_array_muxed18 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3966                 end
3967         endcase
3968 end
3969 always @(*) begin
3970         rhs_array_muxed19 <= 1'd0;
3971         case (subfragments_roundrobin2_grant)
3972                 default: begin
3973                         rhs_array_muxed19 <= port_cmd_payload_we;
3974                 end
3975         endcase
3976 end
3977 always @(*) begin
3978         rhs_array_muxed20 <= 1'd0;
3979         case (subfragments_roundrobin2_grant)
3980                 default: begin
3981                         rhs_array_muxed20 <= (((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid);
3982                 end
3983         endcase
3984 end
3985 always @(*) begin
3986         rhs_array_muxed21 <= 22'd0;
3987         case (subfragments_roundrobin3_grant)
3988                 default: begin
3989                         rhs_array_muxed21 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]};
3990                 end
3991         endcase
3992 end
3993 always @(*) begin
3994         rhs_array_muxed22 <= 1'd0;
3995         case (subfragments_roundrobin3_grant)
3996                 default: begin
3997                         rhs_array_muxed22 <= port_cmd_payload_we;
3998                 end
3999         endcase
4000 end
4001 always @(*) begin
4002         rhs_array_muxed23 <= 1'd0;
4003         case (subfragments_roundrobin3_grant)
4004                 default: begin
4005                         rhs_array_muxed23 <= (((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid);
4006                 end
4007         endcase
4008 end
4009 always @(*) begin
4010         rhs_array_muxed24 <= 30'd0;
4011         case (libresocsim_grant)
4012                 1'd0: begin
4013                         rhs_array_muxed24 <= libresocsim_interface0_converted_interface_adr;
4014                 end
4015                 1'd1: begin
4016                         rhs_array_muxed24 <= libresocsim_interface1_converted_interface_adr;
4017                 end
4018                 default: begin
4019                         rhs_array_muxed24 <= libresocsim_libresoc_jtag_wb_adr;
4020                 end
4021         endcase
4022 end
4023 always @(*) begin
4024         rhs_array_muxed25 <= 32'd0;
4025         case (libresocsim_grant)
4026                 1'd0: begin
4027                         rhs_array_muxed25 <= libresocsim_interface0_converted_interface_dat_w;
4028                 end
4029                 1'd1: begin
4030                         rhs_array_muxed25 <= libresocsim_interface1_converted_interface_dat_w;
4031                 end
4032                 default: begin
4033                         rhs_array_muxed25 <= libresocsim_libresoc_jtag_wb_dat_w;
4034                 end
4035         endcase
4036 end
4037 always @(*) begin
4038         rhs_array_muxed26 <= 4'd0;
4039         case (libresocsim_grant)
4040                 1'd0: begin
4041                         rhs_array_muxed26 <= libresocsim_interface0_converted_interface_sel;
4042                 end
4043                 1'd1: begin
4044                         rhs_array_muxed26 <= libresocsim_interface1_converted_interface_sel;
4045                 end
4046                 default: begin
4047                         rhs_array_muxed26 <= libresocsim_libresoc_jtag_wb_sel;
4048                 end
4049         endcase
4050 end
4051 always @(*) begin
4052         rhs_array_muxed27 <= 1'd0;
4053         case (libresocsim_grant)
4054                 1'd0: begin
4055                         rhs_array_muxed27 <= libresocsim_interface0_converted_interface_cyc;
4056                 end
4057                 1'd1: begin
4058                         rhs_array_muxed27 <= libresocsim_interface1_converted_interface_cyc;
4059                 end
4060                 default: begin
4061                         rhs_array_muxed27 <= libresocsim_libresoc_jtag_wb_cyc;
4062                 end
4063         endcase
4064 end
4065 always @(*) begin
4066         rhs_array_muxed28 <= 1'd0;
4067         case (libresocsim_grant)
4068                 1'd0: begin
4069                         rhs_array_muxed28 <= libresocsim_interface0_converted_interface_stb;
4070                 end
4071                 1'd1: begin
4072                         rhs_array_muxed28 <= libresocsim_interface1_converted_interface_stb;
4073                 end
4074                 default: begin
4075                         rhs_array_muxed28 <= libresocsim_libresoc_jtag_wb_stb;
4076                 end
4077         endcase
4078 end
4079 always @(*) begin
4080         rhs_array_muxed29 <= 1'd0;
4081         case (libresocsim_grant)
4082                 1'd0: begin
4083                         rhs_array_muxed29 <= libresocsim_interface0_converted_interface_we;
4084                 end
4085                 1'd1: begin
4086                         rhs_array_muxed29 <= libresocsim_interface1_converted_interface_we;
4087                 end
4088                 default: begin
4089                         rhs_array_muxed29 <= libresocsim_libresoc_jtag_wb_we;
4090                 end
4091         endcase
4092 end
4093 always @(*) begin
4094         rhs_array_muxed30 <= 3'd0;
4095         case (libresocsim_grant)
4096                 1'd0: begin
4097                         rhs_array_muxed30 <= libresocsim_interface0_converted_interface_cti;
4098                 end
4099                 1'd1: begin
4100                         rhs_array_muxed30 <= libresocsim_interface1_converted_interface_cti;
4101                 end
4102                 default: begin
4103                         rhs_array_muxed30 <= libresocsim_libresoc_jtag_wb_cti;
4104                 end
4105         endcase
4106 end
4107 always @(*) begin
4108         rhs_array_muxed31 <= 2'd0;
4109         case (libresocsim_grant)
4110                 1'd0: begin
4111                         rhs_array_muxed31 <= libresocsim_interface0_converted_interface_bte;
4112                 end
4113                 1'd1: begin
4114                         rhs_array_muxed31 <= libresocsim_interface1_converted_interface_bte;
4115                 end
4116                 default: begin
4117                         rhs_array_muxed31 <= libresocsim_libresoc_jtag_wb_bte;
4118                 end
4119         endcase
4120 end
4121 always @(*) begin
4122         array_muxed0 <= 2'd0;
4123         case (sdram_steerer_sel)
4124                 1'd0: begin
4125                         array_muxed0 <= sdram_nop_ba[1:0];
4126                 end
4127                 1'd1: begin
4128                         array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0];
4129                 end
4130                 2'd2: begin
4131                         array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0];
4132                 end
4133                 default: begin
4134                         array_muxed0 <= sdram_cmd_payload_ba[1:0];
4135                 end
4136         endcase
4137 end
4138 always @(*) begin
4139         array_muxed1 <= 13'd0;
4140         case (sdram_steerer_sel)
4141                 1'd0: begin
4142                         array_muxed1 <= sdram_nop_a;
4143                 end
4144                 1'd1: begin
4145                         array_muxed1 <= sdram_choose_req_cmd_payload_a;
4146                 end
4147                 2'd2: begin
4148                         array_muxed1 <= sdram_choose_req_cmd_payload_a;
4149                 end
4150                 default: begin
4151                         array_muxed1 <= sdram_cmd_payload_a;
4152                 end
4153         endcase
4154 end
4155 always @(*) begin
4156         array_muxed2 <= 1'd0;
4157         case (sdram_steerer_sel)
4158                 1'd0: begin
4159                         array_muxed2 <= 1'd0;
4160                 end
4161                 1'd1: begin
4162                         array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas);
4163                 end
4164                 2'd2: begin
4165                         array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas);
4166                 end
4167                 default: begin
4168                         array_muxed2 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas);
4169                 end
4170         endcase
4171 end
4172 always @(*) begin
4173         array_muxed3 <= 1'd0;
4174         case (sdram_steerer_sel)
4175                 1'd0: begin
4176                         array_muxed3 <= 1'd0;
4177                 end
4178                 1'd1: begin
4179                         array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras);
4180                 end
4181                 2'd2: begin
4182                         array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras);
4183                 end
4184                 default: begin
4185                         array_muxed3 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras);
4186                 end
4187         endcase
4188 end
4189 always @(*) begin
4190         array_muxed4 <= 1'd0;
4191         case (sdram_steerer_sel)
4192                 1'd0: begin
4193                         array_muxed4 <= 1'd0;
4194                 end
4195                 1'd1: begin
4196                         array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we);
4197                 end
4198                 2'd2: begin
4199                         array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we);
4200                 end
4201                 default: begin
4202                         array_muxed4 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we);
4203                 end
4204         endcase
4205 end
4206 always @(*) begin
4207         array_muxed5 <= 1'd0;
4208         case (sdram_steerer_sel)
4209                 1'd0: begin
4210                         array_muxed5 <= 1'd0;
4211                 end
4212                 1'd1: begin
4213                         array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read);
4214                 end
4215                 2'd2: begin
4216                         array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read);
4217                 end
4218                 default: begin
4219                         array_muxed5 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read);
4220                 end
4221         endcase
4222 end
4223 always @(*) begin
4224         array_muxed6 <= 1'd0;
4225         case (sdram_steerer_sel)
4226                 1'd0: begin
4227                         array_muxed6 <= 1'd0;
4228                 end
4229                 1'd1: begin
4230                         array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write);
4231                 end
4232                 2'd2: begin
4233                         array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write);
4234                 end
4235                 default: begin
4236                         array_muxed6 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write);
4237                 end
4238         endcase
4239 end
4240 assign sdrio_clk = sys_clk_1;
4241 assign sdrio_clk_1 = sys_clk_1;
4242 assign sdrio_clk_2 = sys_clk_1;
4243 assign sdrio_clk_3 = sys_clk_1;
4244 assign sdrio_clk_4 = sys_clk_1;
4245 assign sdrio_clk_5 = sys_clk_1;
4246 assign sdrio_clk_6 = sys_clk_1;
4247 assign sdrio_clk_7 = sys_clk_1;
4248 assign sdrio_clk_8 = sys_clk_1;
4249 assign sdrio_clk_9 = sys_clk_1;
4250 assign sdrio_clk_10 = sys_clk_1;
4251 assign sdrio_clk_11 = sys_clk_1;
4252 assign sdrio_clk_12 = sys_clk_1;
4253 assign sdrio_clk_13 = sys_clk_1;
4254 assign sdrio_clk_14 = sys_clk_1;
4255 assign sdrio_clk_15 = sys_clk_1;
4256 assign sdrio_clk_16 = sys_clk_1;
4257 assign sdrio_clk_17 = sys_clk_1;
4258 assign sdrio_clk_18 = sys_clk_1;
4259 assign sdrio_clk_19 = sys_clk_1;
4260 assign sdrio_clk_20 = sys_clk_1;
4261 assign sdrio_clk_21 = sys_clk_1;
4262 assign sdrio_clk_22 = sys_clk_1;
4263 assign sdrio_clk_23 = sys_clk_1;
4264 assign sdrio_clk_24 = sys_clk_1;
4265 assign sdrio_clk_25 = sys_clk_1;
4266 assign sdrio_clk_26 = sys_clk_1;
4267 assign sdrio_clk_27 = sys_clk_1;
4268 assign sdrio_clk_28 = sys_clk_1;
4269 assign sdrio_clk_29 = sys_clk_1;
4270 assign sdrio_clk_30 = sys_clk_1;
4271 assign sdrio_clk_31 = sys_clk_1;
4272 assign sdrio_clk_32 = sys_clk_1;
4273 assign sdrio_clk_33 = sys_clk_1;
4274 assign sdrio_clk_34 = sys_clk_1;
4275 assign sdrio_clk_35 = sys_clk_1;
4276 assign sdrio_clk_36 = sys_clk_1;
4277 assign sdrio_clk_37 = sys_clk_1;
4278 assign sdrio_clk_38 = sys_clk_1;
4279 assign sdrio_clk_39 = sys_clk_1;
4280 assign sdrio_clk_40 = sys_clk_1;
4281 assign sdrio_clk_41 = sys_clk_1;
4282 assign sdrio_clk_42 = sys_clk_1;
4283 assign sdrio_clk_43 = sys_clk_1;
4284 assign sdrio_clk_44 = sys_clk_1;
4285 assign sdrio_clk_45 = sys_clk_1;
4286 assign sdrio_clk_46 = sys_clk_1;
4287 assign sdrio_clk_47 = sys_clk_1;
4288 assign sdrio_clk_48 = sys_clk_1;
4289 assign sdrio_clk_49 = sys_clk_1;
4290 assign sdrio_clk_50 = sys_clk_1;
4291 assign sdrio_clk_51 = sys_clk_1;
4292 assign sdrio_clk_52 = sys_clk_1;
4293 assign sdrio_clk_53 = sys_clk_1;
4294 assign sdrio_clk_54 = sys_clk_1;
4295 assign sdrio_clk_55 = sys_clk_1;
4296 assign sdrio_clk_56 = sys_clk_1;
4297 assign sdrio_clk_57 = sys_clk_1;
4298 assign sdrio_clk_58 = sys_clk_1;
4299 assign sdrio_clk_59 = sys_clk_1;
4300 assign sdrio_clk_60 = sys_clk_1;
4301 assign sdrio_clk_61 = sys_clk_1;
4302 assign sdrio_clk_62 = sys_clk_1;
4303 assign sdrio_clk_63 = sys_clk_1;
4304 assign sdrio_clk_64 = sys_clk_1;
4305 assign sdrio_clk_65 = sys_clk_1;
4306 assign sdrio_clk_66 = sys_clk_1;
4307 assign sdrio_clk_67 = sys_clk_1;
4308 assign sdrio_clk_68 = sys_clk_1;
4309 assign sdrio_clk_69 = sys_clk_1;
4310 assign sdrio_clk_70 = sys_clk_1;
4311 assign uart_phy_rx = regs1;
4312 assign sdrio_clk_71 = sys_clk_1;
4313 assign sdrio_clk_72 = sys_clk_1;
4314 assign sdrio_clk_73 = sys_clk_1;
4315 assign sdrio_clk_74 = sys_clk_1;
4316 assign sdrio_clk_75 = sys_clk_1;
4317 assign sdrio_clk_76 = sys_clk_1;
4318 assign sdrio_clk_77 = sys_clk_1;
4319 assign sdrio_clk_78 = sys_clk_1;
4320 assign sdrio_clk_79 = sys_clk_1;
4321 assign sdrio_clk_80 = sys_clk_1;
4322 assign sdrio_clk_81 = sys_clk_1;
4323 assign sdrio_clk_82 = sys_clk_1;
4324 assign sdrio_clk_83 = sys_clk_1;
4325 assign sdrio_clk_84 = sys_clk_1;
4326 assign sdrio_clk_85 = sys_clk_1;
4327 assign sdrio_clk_86 = sys_clk_1;
4328 assign sdrio_clk_87 = sys_clk_1;
4329 assign sdrio_clk_88 = sys_clk_1;
4330 assign sdrio_clk_89 = sys_clk_1;
4331 assign sdrio_clk_90 = sys_clk_1;
4332 assign sdrio_clk_91 = sys_clk_1;
4333 assign sdrio_clk_92 = sys_clk_1;
4334 assign sdrio_clk_93 = sys_clk_1;
4335 assign sdrio_clk_94 = sys_clk_1;
4336 assign sdrio_clk_95 = sys_clk_1;
4337 assign sdrio_clk_96 = sys_clk_1;
4338 assign sdrio_clk_97 = sys_clk_1;
4339 assign sdrio_clk_98 = sys_clk_1;
4340 assign sdrio_clk_99 = sys_clk_1;
4341 assign sdrio_clk_100 = sys_clk_1;
4342 assign sdrio_clk_101 = sys_clk_1;
4343 assign sdrio_clk_102 = sys_clk_1;
4344 assign sdrio_clk_103 = sys_clk_1;
4345 assign sdrio_clk_104 = sys_clk_1;
4346 assign sdrio_clk_105 = sys_clk_1;
4347 assign sdrio_clk_106 = sys_clk_1;
4348 assign sdrio_clk_107 = sys_clk_1;
4349 assign sdrio_clk_108 = sys_clk_1;
4350 assign sdrio_clk_109 = sys_clk_1;
4351 assign sdrio_clk_110 = sys_clk_1;
4352 assign sdrio_clk_111 = sys_clk_1;
4353 assign sdrio_clk_112 = sys_clk_1;
4354 assign sdrio_clk_113 = sys_clk_1;
4355 assign sdrio_clk_114 = sys_clk_1;
4356 assign sdrio_clk_115 = sys_clk_1;
4357 assign sdrio_clk_116 = sys_clk_1;
4358 assign sdrio_clk_117 = sys_clk_1;
4359 assign sdrio_clk_118 = sys_clk_1;
4360
4361 always @(posedge por_clk) begin
4362         int_rst <= sys_rst;
4363 end
4364
4365 always @(posedge sdrio_clk) begin
4366         libresocsim_libresoc_constraintmanager_sdram_a[0] <= dfi_p0_address[0];
4367         libresocsim_libresoc_constraintmanager_sdram_a[1] <= dfi_p0_address[1];
4368         libresocsim_libresoc_constraintmanager_sdram_a[2] <= dfi_p0_address[2];
4369         libresocsim_libresoc_constraintmanager_sdram_a[3] <= dfi_p0_address[3];
4370         libresocsim_libresoc_constraintmanager_sdram_a[4] <= dfi_p0_address[4];
4371         libresocsim_libresoc_constraintmanager_sdram_a[5] <= dfi_p0_address[5];
4372         libresocsim_libresoc_constraintmanager_sdram_a[6] <= dfi_p0_address[6];
4373         libresocsim_libresoc_constraintmanager_sdram_a[7] <= dfi_p0_address[7];
4374         libresocsim_libresoc_constraintmanager_sdram_a[8] <= dfi_p0_address[8];
4375         libresocsim_libresoc_constraintmanager_sdram_a[9] <= dfi_p0_address[9];
4376         libresocsim_libresoc_constraintmanager_sdram_a[10] <= dfi_p0_address[10];
4377         libresocsim_libresoc_constraintmanager_sdram_a[11] <= dfi_p0_address[11];
4378         libresocsim_libresoc_constraintmanager_sdram_a[12] <= dfi_p0_address[12];
4379         libresocsim_libresoc_constraintmanager_sdram_ba[0] <= dfi_p0_bank[0];
4380         libresocsim_libresoc_constraintmanager_sdram_ba[1] <= dfi_p0_bank[1];
4381         libresocsim_libresoc_constraintmanager_sdram_cas_n <= dfi_p0_cas_n;
4382         libresocsim_libresoc_constraintmanager_sdram_ras_n <= dfi_p0_ras_n;
4383         libresocsim_libresoc_constraintmanager_sdram_we_n <= dfi_p0_we_n;
4384         libresocsim_libresoc_constraintmanager_sdram_cke <= dfi_p0_cke;
4385         libresocsim_libresoc_constraintmanager_sdram_cs_n <= dfi_p0_cs_n;
4386         libresocsim_libresoc_constraintmanager_sdram_dq_oe[0] <= dfi_p0_wrdata_en;
4387         libresocsim_libresoc_constraintmanager_sdram_dq_o[0] <= dfi_p0_wrdata[0];
4388         dfi_p0_rddata[0] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[0];
4389         libresocsim_libresoc_constraintmanager_sdram_dq_oe[1] <= dfi_p0_wrdata_en;
4390         libresocsim_libresoc_constraintmanager_sdram_dq_o[1] <= dfi_p0_wrdata[1];
4391         dfi_p0_rddata[1] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[1];
4392         libresocsim_libresoc_constraintmanager_sdram_dq_oe[2] <= dfi_p0_wrdata_en;
4393         libresocsim_libresoc_constraintmanager_sdram_dq_o[2] <= dfi_p0_wrdata[2];
4394         dfi_p0_rddata[2] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[2];
4395         libresocsim_libresoc_constraintmanager_sdram_dq_oe[3] <= dfi_p0_wrdata_en;
4396         libresocsim_libresoc_constraintmanager_sdram_dq_o[3] <= dfi_p0_wrdata[3];
4397         dfi_p0_rddata[3] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[3];
4398         libresocsim_libresoc_constraintmanager_sdram_dq_oe[4] <= dfi_p0_wrdata_en;
4399         libresocsim_libresoc_constraintmanager_sdram_dq_o[4] <= dfi_p0_wrdata[4];
4400         dfi_p0_rddata[4] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[4];
4401         libresocsim_libresoc_constraintmanager_sdram_dq_oe[5] <= dfi_p0_wrdata_en;
4402         libresocsim_libresoc_constraintmanager_sdram_dq_o[5] <= dfi_p0_wrdata[5];
4403         dfi_p0_rddata[5] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[5];
4404         libresocsim_libresoc_constraintmanager_sdram_dq_oe[6] <= dfi_p0_wrdata_en;
4405         libresocsim_libresoc_constraintmanager_sdram_dq_o[6] <= dfi_p0_wrdata[6];
4406         dfi_p0_rddata[6] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[6];
4407         libresocsim_libresoc_constraintmanager_sdram_dq_oe[7] <= dfi_p0_wrdata_en;
4408         libresocsim_libresoc_constraintmanager_sdram_dq_o[7] <= dfi_p0_wrdata[7];
4409         dfi_p0_rddata[7] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[7];
4410         libresocsim_libresoc_constraintmanager_sdram_dq_oe[8] <= dfi_p0_wrdata_en;
4411         libresocsim_libresoc_constraintmanager_sdram_dq_o[8] <= dfi_p0_wrdata[8];
4412         dfi_p0_rddata[8] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[8];
4413         libresocsim_libresoc_constraintmanager_sdram_dq_oe[9] <= dfi_p0_wrdata_en;
4414         libresocsim_libresoc_constraintmanager_sdram_dq_o[9] <= dfi_p0_wrdata[9];
4415         dfi_p0_rddata[9] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[9];
4416         libresocsim_libresoc_constraintmanager_sdram_dq_oe[10] <= dfi_p0_wrdata_en;
4417         libresocsim_libresoc_constraintmanager_sdram_dq_o[10] <= dfi_p0_wrdata[10];
4418         dfi_p0_rddata[10] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[10];
4419         libresocsim_libresoc_constraintmanager_sdram_dq_oe[11] <= dfi_p0_wrdata_en;
4420         libresocsim_libresoc_constraintmanager_sdram_dq_o[11] <= dfi_p0_wrdata[11];
4421         dfi_p0_rddata[11] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[11];
4422         libresocsim_libresoc_constraintmanager_sdram_dq_oe[12] <= dfi_p0_wrdata_en;
4423         libresocsim_libresoc_constraintmanager_sdram_dq_o[12] <= dfi_p0_wrdata[12];
4424         dfi_p0_rddata[12] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[12];
4425         libresocsim_libresoc_constraintmanager_sdram_dq_oe[13] <= dfi_p0_wrdata_en;
4426         libresocsim_libresoc_constraintmanager_sdram_dq_o[13] <= dfi_p0_wrdata[13];
4427         dfi_p0_rddata[13] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[13];
4428         libresocsim_libresoc_constraintmanager_sdram_dq_oe[14] <= dfi_p0_wrdata_en;
4429         libresocsim_libresoc_constraintmanager_sdram_dq_o[14] <= dfi_p0_wrdata[14];
4430         dfi_p0_rddata[14] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[14];
4431         libresocsim_libresoc_constraintmanager_sdram_dq_oe[15] <= dfi_p0_wrdata_en;
4432         libresocsim_libresoc_constraintmanager_sdram_dq_o[15] <= dfi_p0_wrdata[15];
4433         dfi_p0_rddata[15] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[15];
4434         libresocsim_libresoc_constraintmanager_sdram_dm[0] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[0]);
4435         libresocsim_libresoc_constraintmanager_sdram_dm[1] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[1]);
4436         libresocsim_libresoc_constraintmanager_sdram_clock <= sys_clk_1;
4437         gpio0_pads_gpio0oe[0] <= gpio0_oe_storage[0];
4438         gpio0_pads_gpio0o[0] <= gpio0_out_storage[0];
4439         gpio0_status[0] <= gpio0_pads_gpio0i[0];
4440         gpio0_pads_gpio0oe[1] <= gpio0_oe_storage[1];
4441         gpio0_pads_gpio0o[1] <= gpio0_out_storage[1];
4442         gpio0_status[1] <= gpio0_pads_gpio0i[1];
4443         gpio0_pads_gpio0oe[2] <= gpio0_oe_storage[2];
4444         gpio0_pads_gpio0o[2] <= gpio0_out_storage[2];
4445         gpio0_status[2] <= gpio0_pads_gpio0i[2];
4446         gpio0_pads_gpio0oe[3] <= gpio0_oe_storage[3];
4447         gpio0_pads_gpio0o[3] <= gpio0_out_storage[3];
4448         gpio0_status[3] <= gpio0_pads_gpio0i[3];
4449         gpio0_pads_gpio0oe[4] <= gpio0_oe_storage[4];
4450         gpio0_pads_gpio0o[4] <= gpio0_out_storage[4];
4451         gpio0_status[4] <= gpio0_pads_gpio0i[4];
4452         gpio0_pads_gpio0oe[5] <= gpio0_oe_storage[5];
4453         gpio0_pads_gpio0o[5] <= gpio0_out_storage[5];
4454         gpio0_status[5] <= gpio0_pads_gpio0i[5];
4455         gpio0_pads_gpio0oe[6] <= gpio0_oe_storage[6];
4456         gpio0_pads_gpio0o[6] <= gpio0_out_storage[6];
4457         gpio0_status[6] <= gpio0_pads_gpio0i[6];
4458         gpio0_pads_gpio0oe[7] <= gpio0_oe_storage[7];
4459         gpio0_pads_gpio0o[7] <= gpio0_out_storage[7];
4460         gpio0_status[7] <= gpio0_pads_gpio0i[7];
4461         gpio1_pads_gpio1oe[0] <= gpio1_oe_storage[0];
4462         gpio1_pads_gpio1o[0] <= gpio1_out_storage[0];
4463         gpio1_status[0] <= gpio1_pads_gpio1i[0];
4464         gpio1_pads_gpio1oe[1] <= gpio1_oe_storage[1];
4465         gpio1_pads_gpio1o[1] <= gpio1_out_storage[1];
4466         gpio1_status[1] <= gpio1_pads_gpio1i[1];
4467         gpio1_pads_gpio1oe[2] <= gpio1_oe_storage[2];
4468         gpio1_pads_gpio1o[2] <= gpio1_out_storage[2];
4469         gpio1_status[2] <= gpio1_pads_gpio1i[2];
4470         gpio1_pads_gpio1oe[3] <= gpio1_oe_storage[3];
4471         gpio1_pads_gpio1o[3] <= gpio1_out_storage[3];
4472         gpio1_status[3] <= gpio1_pads_gpio1i[3];
4473         gpio1_pads_gpio1oe[4] <= gpio1_oe_storage[4];
4474         gpio1_pads_gpio1o[4] <= gpio1_out_storage[4];
4475         gpio1_status[4] <= gpio1_pads_gpio1i[4];
4476         gpio1_pads_gpio1oe[5] <= gpio1_oe_storage[5];
4477         gpio1_pads_gpio1o[5] <= gpio1_out_storage[5];
4478         gpio1_status[5] <= gpio1_pads_gpio1i[5];
4479         gpio1_pads_gpio1oe[6] <= gpio1_oe_storage[6];
4480         gpio1_pads_gpio1o[6] <= gpio1_out_storage[6];
4481         gpio1_status[6] <= gpio1_pads_gpio1i[6];
4482         gpio1_pads_gpio1oe[7] <= gpio1_oe_storage[7];
4483         gpio1_pads_gpio1o[7] <= gpio1_out_storage[7];
4484         gpio1_status[7] <= gpio1_pads_gpio1i[7];
4485 end
4486
4487 always @(posedge sys_clk_1) begin
4488         dummy[0] <= (nc_1[0] | libresocsim_libresoc_interrupt[0]);
4489         dummy[1] <= (nc_1[1] | libresocsim_libresoc_interrupt[0]);
4490         dummy[2] <= (nc_1[2] | libresocsim_libresoc_interrupt[0]);
4491         dummy[3] <= (nc_1[3] | libresocsim_libresoc_interrupt[0]);
4492         dummy[4] <= (nc_1[4] | libresocsim_libresoc_interrupt[0]);
4493         dummy[5] <= (nc_1[5] | libresocsim_libresoc_interrupt[0]);
4494         dummy[6] <= (nc_1[6] | libresocsim_libresoc_interrupt[0]);
4495         dummy[7] <= (nc_1[7] | libresocsim_libresoc_interrupt[0]);
4496         dummy[8] <= (nc_1[8] | libresocsim_libresoc_interrupt[0]);
4497         dummy[9] <= (nc_1[9] | libresocsim_libresoc_interrupt[0]);
4498         dummy[10] <= (nc_1[10] | libresocsim_libresoc_interrupt[0]);
4499         dummy[11] <= (nc_1[11] | libresocsim_libresoc_interrupt[0]);
4500         dummy[12] <= (nc_1[12] | libresocsim_libresoc_interrupt[0]);
4501         dummy[13] <= (nc_1[13] | libresocsim_libresoc_interrupt[0]);
4502         dummy[14] <= (nc_1[14] | libresocsim_libresoc_interrupt[0]);
4503         dummy[15] <= (nc_1[15] | libresocsim_libresoc_interrupt[0]);
4504         dummy[16] <= (nc_1[16] | libresocsim_libresoc_interrupt[0]);
4505         dummy[17] <= (nc_1[17] | libresocsim_libresoc_interrupt[0]);
4506         dummy[18] <= (nc_1[18] | libresocsim_libresoc_interrupt[0]);
4507         dummy[19] <= (nc_1[19] | libresocsim_libresoc_interrupt[0]);
4508         dummy[20] <= (nc_1[20] | libresocsim_libresoc_interrupt[0]);
4509         dummy[21] <= (nc_1[21] | libresocsim_libresoc_interrupt[0]);
4510         dummy[22] <= (nc_1[22] | libresocsim_libresoc_interrupt[0]);
4511         dummy[23] <= (nc_1[23] | libresocsim_libresoc_interrupt[0]);
4512         dummy[24] <= (nc_1[24] | libresocsim_libresoc_interrupt[0]);
4513         dummy[25] <= (nc_1[25] | libresocsim_libresoc_interrupt[0]);
4514         dummy[26] <= (nc_1[26] | libresocsim_libresoc_interrupt[0]);
4515         dummy[27] <= (nc_1[27] | libresocsim_libresoc_interrupt[0]);
4516         dummy[28] <= (nc_1[28] | libresocsim_libresoc_interrupt[0]);
4517         dummy[29] <= (nc_1[29] | libresocsim_libresoc_interrupt[0]);
4518         dummy[30] <= (nc_1[30] | libresocsim_libresoc_interrupt[0]);
4519         dummy[31] <= (nc_1[31] | libresocsim_libresoc_interrupt[0]);
4520         dummy[32] <= (nc_1[32] | libresocsim_libresoc_interrupt[0]);
4521         dummy[33] <= (nc_1[33] | libresocsim_libresoc_interrupt[0]);
4522         dummy[34] <= (nc_1[34] | libresocsim_libresoc_interrupt[0]);
4523         dummy[35] <= (nc_1[35] | libresocsim_libresoc_interrupt[0]);
4524         if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin
4525                 libresocsim_converter0_dat_r <= libresocsim_libresoc_ibus_dat_r;
4526         end
4527         subfragments_converter0_state <= subfragments_converter0_next_state;
4528         if (libresocsim_converter0_counter_subfragments_converter0_next_value_ce) begin
4529                 libresocsim_converter0_counter <= libresocsim_converter0_counter_subfragments_converter0_next_value;
4530         end
4531         if (libresocsim_converter0_reset) begin
4532                 libresocsim_converter0_counter <= 1'd0;
4533                 subfragments_converter0_state <= 1'd0;
4534         end
4535         if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin
4536                 libresocsim_converter1_dat_r <= libresocsim_libresoc_dbus_dat_r;
4537         end
4538         subfragments_converter1_state <= subfragments_converter1_next_state;
4539         if (libresocsim_converter1_counter_subfragments_converter1_next_value_ce) begin
4540                 libresocsim_converter1_counter <= libresocsim_converter1_counter_subfragments_converter1_next_value;
4541         end
4542         if (libresocsim_converter1_reset) begin
4543                 libresocsim_converter1_counter <= 1'd0;
4544                 subfragments_converter1_state <= 1'd0;
4545         end
4546         if ((libresocsim_bus_errors != 32'd4294967295)) begin
4547                 if (libresocsim_bus_error) begin
4548                         libresocsim_bus_errors <= (libresocsim_bus_errors + 1'd1);
4549                 end
4550         end
4551         libresocsim_ram_bus_ack <= 1'd0;
4552         if (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & (~libresocsim_ram_bus_ack))) begin
4553                 libresocsim_ram_bus_ack <= 1'd1;
4554         end
4555         if (libresocsim_en_storage) begin
4556                 if ((libresocsim_value == 1'd0)) begin
4557                         libresocsim_value <= libresocsim_reload_storage;
4558                 end else begin
4559                         libresocsim_value <= (libresocsim_value - 1'd1);
4560                 end
4561         end else begin
4562                 libresocsim_value <= libresocsim_load_storage;
4563         end
4564         if (libresocsim_update_value_re) begin
4565                 libresocsim_value_status <= libresocsim_value;
4566         end
4567         if (libresocsim_zero_clear) begin
4568                 libresocsim_zero_pending <= 1'd0;
4569         end
4570         libresocsim_zero_old_trigger <= libresocsim_zero_trigger;
4571         if (((~libresocsim_zero_trigger) & libresocsim_zero_old_trigger)) begin
4572                 libresocsim_zero_pending <= 1'd1;
4573         end
4574         ram_bus_ram_bus_ack <= 1'd0;
4575         if (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & (~ram_bus_ram_bus_ack))) begin
4576                 ram_bus_ram_bus_ack <= 1'd1;
4577         end
4578         rddata_en <= {rddata_en, dfi_p0_rddata_en};
4579         dfi_p0_rddata_valid <= rddata_en[2];
4580         if (sdram_inti_p0_rddata_valid) begin
4581                 sdram_status <= sdram_inti_p0_rddata;
4582         end
4583         if ((sdram_timer_wait & (~sdram_timer_done0))) begin
4584                 sdram_timer_count1 <= (sdram_timer_count1 - 1'd1);
4585         end else begin
4586                 sdram_timer_count1 <= 10'd781;
4587         end
4588         sdram_postponer_req_o <= 1'd0;
4589         if (sdram_postponer_req_i) begin
4590                 sdram_postponer_count <= (sdram_postponer_count - 1'd1);
4591                 if ((sdram_postponer_count == 1'd0)) begin
4592                         sdram_postponer_count <= 1'd0;
4593                         sdram_postponer_req_o <= 1'd1;
4594                 end
4595         end
4596         if (sdram_sequencer_start0) begin
4597                 sdram_sequencer_count <= 1'd0;
4598         end else begin
4599                 if (sdram_sequencer_done1) begin
4600                         if ((sdram_sequencer_count != 1'd0)) begin
4601                                 sdram_sequencer_count <= (sdram_sequencer_count - 1'd1);
4602                         end
4603                 end
4604         end
4605         sdram_cmd_payload_a <= 1'd0;
4606         sdram_cmd_payload_ba <= 1'd0;
4607         sdram_cmd_payload_cas <= 1'd0;
4608         sdram_cmd_payload_ras <= 1'd0;
4609         sdram_cmd_payload_we <= 1'd0;
4610         sdram_sequencer_done1 <= 1'd0;
4611         if ((sdram_sequencer_start1 & (sdram_sequencer_counter == 1'd0))) begin
4612                 sdram_cmd_payload_a <= 11'd1024;
4613                 sdram_cmd_payload_ba <= 1'd0;
4614                 sdram_cmd_payload_cas <= 1'd0;
4615                 sdram_cmd_payload_ras <= 1'd1;
4616                 sdram_cmd_payload_we <= 1'd1;
4617         end
4618         if ((sdram_sequencer_counter == 2'd2)) begin
4619                 sdram_cmd_payload_a <= 1'd0;
4620                 sdram_cmd_payload_ba <= 1'd0;
4621                 sdram_cmd_payload_cas <= 1'd1;
4622                 sdram_cmd_payload_ras <= 1'd1;
4623                 sdram_cmd_payload_we <= 1'd0;
4624         end
4625         if ((sdram_sequencer_counter == 4'd8)) begin
4626                 sdram_cmd_payload_a <= 1'd0;
4627                 sdram_cmd_payload_ba <= 1'd0;
4628                 sdram_cmd_payload_cas <= 1'd0;
4629                 sdram_cmd_payload_ras <= 1'd0;
4630                 sdram_cmd_payload_we <= 1'd0;
4631                 sdram_sequencer_done1 <= 1'd1;
4632         end
4633         if ((sdram_sequencer_counter == 4'd8)) begin
4634                 sdram_sequencer_counter <= 1'd0;
4635         end else begin
4636                 if ((sdram_sequencer_counter != 1'd0)) begin
4637                         sdram_sequencer_counter <= (sdram_sequencer_counter + 1'd1);
4638                 end else begin
4639                         if (sdram_sequencer_start1) begin
4640                                 sdram_sequencer_counter <= 1'd1;
4641                         end
4642                 end
4643         end
4644         subfragments_refresher_state <= subfragments_refresher_next_state;
4645         if (sdram_bankmachine0_row_close) begin
4646                 sdram_bankmachine0_row_opened <= 1'd0;
4647         end else begin
4648                 if (sdram_bankmachine0_row_open) begin
4649                         sdram_bankmachine0_row_opened <= 1'd1;
4650                         sdram_bankmachine0_row <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
4651                 end
4652         end
4653         if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
4654                 sdram_bankmachine0_cmd_buffer_lookahead_produce <= (sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
4655         end
4656         if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
4657                 sdram_bankmachine0_cmd_buffer_lookahead_consume <= (sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
4658         end
4659         if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
4660                 if ((~sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
4661                         sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
4662                 end
4663         end else begin
4664                 if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
4665                         sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
4666                 end
4667         end
4668         if (((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready)) begin
4669                 sdram_bankmachine0_cmd_buffer_source_valid <= sdram_bankmachine0_cmd_buffer_sink_valid;
4670                 sdram_bankmachine0_cmd_buffer_source_first <= sdram_bankmachine0_cmd_buffer_sink_first;
4671                 sdram_bankmachine0_cmd_buffer_source_last <= sdram_bankmachine0_cmd_buffer_sink_last;
4672                 sdram_bankmachine0_cmd_buffer_source_payload_we <= sdram_bankmachine0_cmd_buffer_sink_payload_we;
4673                 sdram_bankmachine0_cmd_buffer_source_payload_addr <= sdram_bankmachine0_cmd_buffer_sink_payload_addr;
4674         end
4675         if (sdram_bankmachine0_twtpcon_valid) begin
4676                 sdram_bankmachine0_twtpcon_count <= 3'd4;
4677                 if (1'd0) begin
4678                         sdram_bankmachine0_twtpcon_ready <= 1'd1;
4679                 end else begin
4680                         sdram_bankmachine0_twtpcon_ready <= 1'd0;
4681                 end
4682         end else begin
4683                 if ((~sdram_bankmachine0_twtpcon_ready)) begin
4684                         sdram_bankmachine0_twtpcon_count <= (sdram_bankmachine0_twtpcon_count - 1'd1);
4685                         if ((sdram_bankmachine0_twtpcon_count == 1'd1)) begin
4686                                 sdram_bankmachine0_twtpcon_ready <= 1'd1;
4687                         end
4688                 end
4689         end
4690         subfragments_bankmachine0_state <= subfragments_bankmachine0_next_state;
4691         if (sdram_bankmachine1_row_close) begin
4692                 sdram_bankmachine1_row_opened <= 1'd0;
4693         end else begin
4694                 if (sdram_bankmachine1_row_open) begin
4695                         sdram_bankmachine1_row_opened <= 1'd1;
4696                         sdram_bankmachine1_row <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
4697                 end
4698         end
4699         if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
4700                 sdram_bankmachine1_cmd_buffer_lookahead_produce <= (sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
4701         end
4702         if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
4703                 sdram_bankmachine1_cmd_buffer_lookahead_consume <= (sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
4704         end
4705         if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
4706                 if ((~sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
4707                         sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
4708                 end
4709         end else begin
4710                 if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
4711                         sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
4712                 end
4713         end
4714         if (((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready)) begin
4715                 sdram_bankmachine1_cmd_buffer_source_valid <= sdram_bankmachine1_cmd_buffer_sink_valid;
4716                 sdram_bankmachine1_cmd_buffer_source_first <= sdram_bankmachine1_cmd_buffer_sink_first;
4717                 sdram_bankmachine1_cmd_buffer_source_last <= sdram_bankmachine1_cmd_buffer_sink_last;
4718                 sdram_bankmachine1_cmd_buffer_source_payload_we <= sdram_bankmachine1_cmd_buffer_sink_payload_we;
4719                 sdram_bankmachine1_cmd_buffer_source_payload_addr <= sdram_bankmachine1_cmd_buffer_sink_payload_addr;
4720         end
4721         if (sdram_bankmachine1_twtpcon_valid) begin
4722                 sdram_bankmachine1_twtpcon_count <= 3'd4;
4723                 if (1'd0) begin
4724                         sdram_bankmachine1_twtpcon_ready <= 1'd1;
4725                 end else begin
4726                         sdram_bankmachine1_twtpcon_ready <= 1'd0;
4727                 end
4728         end else begin
4729                 if ((~sdram_bankmachine1_twtpcon_ready)) begin
4730                         sdram_bankmachine1_twtpcon_count <= (sdram_bankmachine1_twtpcon_count - 1'd1);
4731                         if ((sdram_bankmachine1_twtpcon_count == 1'd1)) begin
4732                                 sdram_bankmachine1_twtpcon_ready <= 1'd1;
4733                         end
4734                 end
4735         end
4736         subfragments_bankmachine1_state <= subfragments_bankmachine1_next_state;
4737         if (sdram_bankmachine2_row_close) begin
4738                 sdram_bankmachine2_row_opened <= 1'd0;
4739         end else begin
4740                 if (sdram_bankmachine2_row_open) begin
4741                         sdram_bankmachine2_row_opened <= 1'd1;
4742                         sdram_bankmachine2_row <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
4743                 end
4744         end
4745         if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
4746                 sdram_bankmachine2_cmd_buffer_lookahead_produce <= (sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
4747         end
4748         if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
4749                 sdram_bankmachine2_cmd_buffer_lookahead_consume <= (sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
4750         end
4751         if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
4752                 if ((~sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
4753                         sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
4754                 end
4755         end else begin
4756                 if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
4757                         sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
4758                 end
4759         end
4760         if (((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready)) begin
4761                 sdram_bankmachine2_cmd_buffer_source_valid <= sdram_bankmachine2_cmd_buffer_sink_valid;
4762                 sdram_bankmachine2_cmd_buffer_source_first <= sdram_bankmachine2_cmd_buffer_sink_first;
4763                 sdram_bankmachine2_cmd_buffer_source_last <= sdram_bankmachine2_cmd_buffer_sink_last;
4764                 sdram_bankmachine2_cmd_buffer_source_payload_we <= sdram_bankmachine2_cmd_buffer_sink_payload_we;
4765                 sdram_bankmachine2_cmd_buffer_source_payload_addr <= sdram_bankmachine2_cmd_buffer_sink_payload_addr;
4766         end
4767         if (sdram_bankmachine2_twtpcon_valid) begin
4768                 sdram_bankmachine2_twtpcon_count <= 3'd4;
4769                 if (1'd0) begin
4770                         sdram_bankmachine2_twtpcon_ready <= 1'd1;
4771                 end else begin
4772                         sdram_bankmachine2_twtpcon_ready <= 1'd0;
4773                 end
4774         end else begin
4775                 if ((~sdram_bankmachine2_twtpcon_ready)) begin
4776                         sdram_bankmachine2_twtpcon_count <= (sdram_bankmachine2_twtpcon_count - 1'd1);
4777                         if ((sdram_bankmachine2_twtpcon_count == 1'd1)) begin
4778                                 sdram_bankmachine2_twtpcon_ready <= 1'd1;
4779                         end
4780                 end
4781         end
4782         subfragments_bankmachine2_state <= subfragments_bankmachine2_next_state;
4783         if (sdram_bankmachine3_row_close) begin
4784                 sdram_bankmachine3_row_opened <= 1'd0;
4785         end else begin
4786                 if (sdram_bankmachine3_row_open) begin
4787                         sdram_bankmachine3_row_opened <= 1'd1;
4788                         sdram_bankmachine3_row <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
4789                 end
4790         end
4791         if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
4792                 sdram_bankmachine3_cmd_buffer_lookahead_produce <= (sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
4793         end
4794         if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
4795                 sdram_bankmachine3_cmd_buffer_lookahead_consume <= (sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
4796         end
4797         if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
4798                 if ((~sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
4799                         sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
4800                 end
4801         end else begin
4802                 if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
4803                         sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
4804                 end
4805         end
4806         if (((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready)) begin
4807                 sdram_bankmachine3_cmd_buffer_source_valid <= sdram_bankmachine3_cmd_buffer_sink_valid;
4808                 sdram_bankmachine3_cmd_buffer_source_first <= sdram_bankmachine3_cmd_buffer_sink_first;
4809                 sdram_bankmachine3_cmd_buffer_source_last <= sdram_bankmachine3_cmd_buffer_sink_last;
4810                 sdram_bankmachine3_cmd_buffer_source_payload_we <= sdram_bankmachine3_cmd_buffer_sink_payload_we;
4811                 sdram_bankmachine3_cmd_buffer_source_payload_addr <= sdram_bankmachine3_cmd_buffer_sink_payload_addr;
4812         end
4813         if (sdram_bankmachine3_twtpcon_valid) begin
4814                 sdram_bankmachine3_twtpcon_count <= 3'd4;
4815                 if (1'd0) begin
4816                         sdram_bankmachine3_twtpcon_ready <= 1'd1;
4817                 end else begin
4818                         sdram_bankmachine3_twtpcon_ready <= 1'd0;
4819                 end
4820         end else begin
4821                 if ((~sdram_bankmachine3_twtpcon_ready)) begin
4822                         sdram_bankmachine3_twtpcon_count <= (sdram_bankmachine3_twtpcon_count - 1'd1);
4823                         if ((sdram_bankmachine3_twtpcon_count == 1'd1)) begin
4824                                 sdram_bankmachine3_twtpcon_ready <= 1'd1;
4825                         end
4826                 end
4827         end
4828         subfragments_bankmachine3_state <= subfragments_bankmachine3_next_state;
4829         if ((~sdram_en0)) begin
4830                 sdram_time0 <= 5'd31;
4831         end else begin
4832                 if ((~sdram_max_time0)) begin
4833                         sdram_time0 <= (sdram_time0 - 1'd1);
4834                 end
4835         end
4836         if ((~sdram_en1)) begin
4837                 sdram_time1 <= 4'd15;
4838         end else begin
4839                 if ((~sdram_max_time1)) begin
4840                         sdram_time1 <= (sdram_time1 - 1'd1);
4841                 end
4842         end
4843         if (sdram_choose_cmd_ce) begin
4844                 case (sdram_choose_cmd_grant)
4845                         1'd0: begin
4846                                 if (sdram_choose_cmd_request[1]) begin
4847                                         sdram_choose_cmd_grant <= 1'd1;
4848                                 end else begin
4849                                         if (sdram_choose_cmd_request[2]) begin
4850                                                 sdram_choose_cmd_grant <= 2'd2;
4851                                         end else begin
4852                                                 if (sdram_choose_cmd_request[3]) begin
4853                                                         sdram_choose_cmd_grant <= 2'd3;
4854                                                 end
4855                                         end
4856                                 end
4857                         end
4858                         1'd1: begin
4859                                 if (sdram_choose_cmd_request[2]) begin
4860                                         sdram_choose_cmd_grant <= 2'd2;
4861                                 end else begin
4862                                         if (sdram_choose_cmd_request[3]) begin
4863                                                 sdram_choose_cmd_grant <= 2'd3;
4864                                         end else begin
4865                                                 if (sdram_choose_cmd_request[0]) begin
4866                                                         sdram_choose_cmd_grant <= 1'd0;
4867                                                 end
4868                                         end
4869                                 end
4870                         end
4871                         2'd2: begin
4872                                 if (sdram_choose_cmd_request[3]) begin
4873                                         sdram_choose_cmd_grant <= 2'd3;
4874                                 end else begin
4875                                         if (sdram_choose_cmd_request[0]) begin
4876                                                 sdram_choose_cmd_grant <= 1'd0;
4877                                         end else begin
4878                                                 if (sdram_choose_cmd_request[1]) begin
4879                                                         sdram_choose_cmd_grant <= 1'd1;
4880                                                 end
4881                                         end
4882                                 end
4883                         end
4884                         2'd3: begin
4885                                 if (sdram_choose_cmd_request[0]) begin
4886                                         sdram_choose_cmd_grant <= 1'd0;
4887                                 end else begin
4888                                         if (sdram_choose_cmd_request[1]) begin
4889                                                 sdram_choose_cmd_grant <= 1'd1;
4890                                         end else begin
4891                                                 if (sdram_choose_cmd_request[2]) begin
4892                                                         sdram_choose_cmd_grant <= 2'd2;
4893                                                 end
4894                                         end
4895                                 end
4896                         end
4897                 endcase
4898         end
4899         if (sdram_choose_req_ce) begin
4900                 case (sdram_choose_req_grant)
4901                         1'd0: begin
4902                                 if (sdram_choose_req_request[1]) begin
4903                                         sdram_choose_req_grant <= 1'd1;
4904                                 end else begin
4905                                         if (sdram_choose_req_request[2]) begin
4906                                                 sdram_choose_req_grant <= 2'd2;
4907                                         end else begin
4908                                                 if (sdram_choose_req_request[3]) begin
4909                                                         sdram_choose_req_grant <= 2'd3;
4910                                                 end
4911                                         end
4912                                 end
4913                         end
4914                         1'd1: begin
4915                                 if (sdram_choose_req_request[2]) begin
4916                                         sdram_choose_req_grant <= 2'd2;
4917                                 end else begin
4918                                         if (sdram_choose_req_request[3]) begin
4919                                                 sdram_choose_req_grant <= 2'd3;
4920                                         end else begin
4921                                                 if (sdram_choose_req_request[0]) begin
4922                                                         sdram_choose_req_grant <= 1'd0;
4923                                                 end
4924                                         end
4925                                 end
4926                         end
4927                         2'd2: begin
4928                                 if (sdram_choose_req_request[3]) begin
4929                                         sdram_choose_req_grant <= 2'd3;
4930                                 end else begin
4931                                         if (sdram_choose_req_request[0]) begin
4932                                                 sdram_choose_req_grant <= 1'd0;
4933                                         end else begin
4934                                                 if (sdram_choose_req_request[1]) begin
4935                                                         sdram_choose_req_grant <= 1'd1;
4936                                                 end
4937                                         end
4938                                 end
4939                         end
4940                         2'd3: begin
4941                                 if (sdram_choose_req_request[0]) begin
4942                                         sdram_choose_req_grant <= 1'd0;
4943                                 end else begin
4944                                         if (sdram_choose_req_request[1]) begin
4945                                                 sdram_choose_req_grant <= 1'd1;
4946                                         end else begin
4947                                                 if (sdram_choose_req_request[2]) begin
4948                                                         sdram_choose_req_grant <= 2'd2;
4949                                                 end
4950                                         end
4951                                 end
4952                         end
4953                 endcase
4954         end
4955         sdram_dfi_p0_cs_n <= 1'd0;
4956         sdram_dfi_p0_bank <= array_muxed0;
4957         sdram_dfi_p0_address <= array_muxed1;
4958         sdram_dfi_p0_cas_n <= (~array_muxed2);
4959         sdram_dfi_p0_ras_n <= (~array_muxed3);
4960         sdram_dfi_p0_we_n <= (~array_muxed4);
4961         sdram_dfi_p0_rddata_en <= array_muxed5;
4962         sdram_dfi_p0_wrdata_en <= array_muxed6;
4963         if (sdram_tccdcon_valid) begin
4964                 sdram_tccdcon_count <= 1'd0;
4965                 if (1'd1) begin
4966                         sdram_tccdcon_ready <= 1'd1;
4967                 end else begin
4968                         sdram_tccdcon_ready <= 1'd0;
4969                 end
4970         end else begin
4971                 if ((~sdram_tccdcon_ready)) begin
4972                         sdram_tccdcon_count <= (sdram_tccdcon_count - 1'd1);
4973                         if ((sdram_tccdcon_count == 1'd1)) begin
4974                                 sdram_tccdcon_ready <= 1'd1;
4975                         end
4976                 end
4977         end
4978         if (sdram_twtrcon_valid) begin
4979                 sdram_twtrcon_count <= 3'd4;
4980                 if (1'd0) begin
4981                         sdram_twtrcon_ready <= 1'd1;
4982                 end else begin
4983                         sdram_twtrcon_ready <= 1'd0;
4984                 end
4985         end else begin
4986                 if ((~sdram_twtrcon_ready)) begin
4987                         sdram_twtrcon_count <= (sdram_twtrcon_count - 1'd1);
4988                         if ((sdram_twtrcon_count == 1'd1)) begin
4989                                 sdram_twtrcon_ready <= 1'd1;
4990                         end
4991                 end
4992         end
4993         subfragments_multiplexer_state <= subfragments_multiplexer_next_state;
4994         subfragments_new_master_wdata_ready <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_wdata_ready)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_wdata_ready)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_wdata_ready)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_wdata_ready));
4995         subfragments_new_master_rdata_valid0 <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_rdata_valid)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_rdata_valid)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_rdata_valid)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_rdata_valid));
4996         subfragments_new_master_rdata_valid1 <= subfragments_new_master_rdata_valid0;
4997         subfragments_new_master_rdata_valid2 <= subfragments_new_master_rdata_valid1;
4998         subfragments_new_master_rdata_valid3 <= subfragments_new_master_rdata_valid2;
4999         if ((litedram_wb_ack | converter_skip)) begin
5000                 converter_dat_r <= wb_sdram_dat_r;
5001         end
5002         subfragments_state <= subfragments_next_state;
5003         if (converter_counter_subfragments_next_value_ce) begin
5004                 converter_counter <= converter_counter_subfragments_next_value;
5005         end
5006         if (converter_reset) begin
5007                 converter_counter <= 1'd0;
5008                 subfragments_state <= 1'd0;
5009         end
5010         if (litedram_wb_ack) begin
5011                 cmd_consumed <= 1'd0;
5012                 wdata_consumed <= 1'd0;
5013         end else begin
5014                 if ((port_cmd_valid & port_cmd_ready)) begin
5015                         cmd_consumed <= 1'd1;
5016                 end
5017                 if ((port_wdata_valid & port_wdata_ready)) begin
5018                         wdata_consumed <= 1'd1;
5019                 end
5020         end
5021         uart_phy_sink_ready <= 1'd0;
5022         if (((uart_phy_sink_valid & (~uart_phy_tx_busy)) & (~uart_phy_sink_ready))) begin
5023                 uart_phy_tx_reg <= uart_phy_sink_payload_data;
5024                 uart_phy_tx_bitcount <= 1'd0;
5025                 uart_phy_tx_busy <= 1'd1;
5026                 libresocsim_libresoc_constraintmanager_uart_tx <= 1'd0;
5027         end else begin
5028                 if ((uart_phy_uart_clk_txen & uart_phy_tx_busy)) begin
5029                         uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1);
5030                         if ((uart_phy_tx_bitcount == 4'd8)) begin
5031                                 libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5032                         end else begin
5033                                 if ((uart_phy_tx_bitcount == 4'd9)) begin
5034                                         libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5035                                         uart_phy_tx_busy <= 1'd0;
5036                                         uart_phy_sink_ready <= 1'd1;
5037                                 end else begin
5038                                         libresocsim_libresoc_constraintmanager_uart_tx <= uart_phy_tx_reg[0];
5039                                         uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]};
5040                                 end
5041                         end
5042                 end
5043         end
5044         if (uart_phy_tx_busy) begin
5045                 {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= (uart_phy_phase_accumulator_tx + uart_phy_storage);
5046         end else begin
5047                 {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= uart_phy_storage;
5048         end
5049         uart_phy_source_valid <= 1'd0;
5050         uart_phy_rx_r <= uart_phy_rx;
5051         if ((~uart_phy_rx_busy)) begin
5052                 if (((~uart_phy_rx) & uart_phy_rx_r)) begin
5053                         uart_phy_rx_busy <= 1'd1;
5054                         uart_phy_rx_bitcount <= 1'd0;
5055                 end
5056         end else begin
5057                 if (uart_phy_uart_clk_rxen) begin
5058                         uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1);
5059                         if ((uart_phy_rx_bitcount == 1'd0)) begin
5060                                 if (uart_phy_rx) begin
5061                                         uart_phy_rx_busy <= 1'd0;
5062                                 end
5063                         end else begin
5064                                 if ((uart_phy_rx_bitcount == 4'd9)) begin
5065                                         uart_phy_rx_busy <= 1'd0;
5066                                         if (uart_phy_rx) begin
5067                                                 uart_phy_source_payload_data <= uart_phy_rx_reg;
5068                                                 uart_phy_source_valid <= 1'd1;
5069                                         end
5070                                 end else begin
5071                                         uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]};
5072                                 end
5073                         end
5074                 end
5075         end
5076         if (uart_phy_rx_busy) begin
5077                 {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= (uart_phy_phase_accumulator_rx + uart_phy_storage);
5078         end else begin
5079                 {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= 32'd2147483648;
5080         end
5081         if (tx_clear) begin
5082                 tx_pending <= 1'd0;
5083         end
5084         tx_old_trigger <= tx_trigger;
5085         if (((~tx_trigger) & tx_old_trigger)) begin
5086                 tx_pending <= 1'd1;
5087         end
5088         if (rx_clear) begin
5089                 rx_pending <= 1'd0;
5090         end
5091         rx_old_trigger <= rx_trigger;
5092         if (((~rx_trigger) & rx_old_trigger)) begin
5093                 rx_pending <= 1'd1;
5094         end
5095         if (tx_fifo_syncfifo_re) begin
5096                 tx_fifo_readable <= 1'd1;
5097         end else begin
5098                 if (tx_fifo_re) begin
5099                         tx_fifo_readable <= 1'd0;
5100                 end
5101         end
5102         if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin
5103                 tx_fifo_produce <= (tx_fifo_produce + 1'd1);
5104         end
5105         if (tx_fifo_do_read) begin
5106                 tx_fifo_consume <= (tx_fifo_consume + 1'd1);
5107         end
5108         if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin
5109                 if ((~tx_fifo_do_read)) begin
5110                         tx_fifo_level0 <= (tx_fifo_level0 + 1'd1);
5111                 end
5112         end else begin
5113                 if (tx_fifo_do_read) begin
5114                         tx_fifo_level0 <= (tx_fifo_level0 - 1'd1);
5115                 end
5116         end
5117         if (rx_fifo_syncfifo_re) begin
5118                 rx_fifo_readable <= 1'd1;
5119         end else begin
5120                 if (rx_fifo_re) begin
5121                         rx_fifo_readable <= 1'd0;
5122                 end
5123         end
5124         if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin
5125                 rx_fifo_produce <= (rx_fifo_produce + 1'd1);
5126         end
5127         if (rx_fifo_do_read) begin
5128                 rx_fifo_consume <= (rx_fifo_consume + 1'd1);
5129         end
5130         if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin
5131                 if ((~rx_fifo_do_read)) begin
5132                         rx_fifo_level0 <= (rx_fifo_level0 + 1'd1);
5133                 end
5134         end else begin
5135                 if (rx_fifo_do_read) begin
5136                         rx_fifo_level0 <= (rx_fifo_level0 - 1'd1);
5137                 end
5138         end
5139         if (reset) begin
5140                 tx_pending <= 1'd0;
5141                 tx_old_trigger <= 1'd0;
5142                 rx_pending <= 1'd0;
5143                 rx_old_trigger <= 1'd0;
5144                 tx_fifo_readable <= 1'd0;
5145                 tx_fifo_level0 <= 5'd0;
5146                 tx_fifo_produce <= 4'd0;
5147                 tx_fifo_consume <= 4'd0;
5148                 rx_fifo_readable <= 1'd0;
5149                 rx_fifo_level0 <= 5'd0;
5150                 rx_fifo_produce <= 4'd0;
5151                 rx_fifo_consume <= 4'd0;
5152         end
5153         libresocsim_state <= libresocsim_next_state;
5154         if (libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0) begin
5155                 libresocsim_libresocsim_dat_w <= libresocsim_libresocsim_dat_w_libresocsim_next_value0;
5156         end
5157         if (libresocsim_libresocsim_adr_libresocsim_next_value_ce1) begin
5158                 libresocsim_libresocsim_adr <= libresocsim_libresocsim_adr_libresocsim_next_value1;
5159         end
5160         if (libresocsim_libresocsim_we_libresocsim_next_value_ce2) begin
5161                 libresocsim_libresocsim_we <= libresocsim_libresocsim_we_libresocsim_next_value2;
5162         end
5163         case (libresocsim_grant)
5164                 1'd0: begin
5165                         if ((~libresocsim_request[0])) begin
5166                                 if (libresocsim_request[1]) begin
5167                                         libresocsim_grant <= 1'd1;
5168                                 end else begin
5169                                         if (libresocsim_request[2]) begin
5170                                                 libresocsim_grant <= 2'd2;
5171                                         end
5172                                 end
5173                         end
5174                 end
5175                 1'd1: begin
5176                         if ((~libresocsim_request[1])) begin
5177                                 if (libresocsim_request[2]) begin
5178                                         libresocsim_grant <= 2'd2;
5179                                 end else begin
5180                                         if (libresocsim_request[0]) begin
5181                                                 libresocsim_grant <= 1'd0;
5182                                         end
5183                                 end
5184                         end
5185                 end
5186                 2'd2: begin
5187                         if ((~libresocsim_request[2])) begin
5188                                 if (libresocsim_request[0]) begin
5189                                         libresocsim_grant <= 1'd0;
5190                                 end else begin
5191                                         if (libresocsim_request[1]) begin
5192                                                 libresocsim_grant <= 1'd1;
5193                                         end
5194                                 end
5195                         end
5196                 end
5197         endcase
5198         libresocsim_slave_sel_r <= libresocsim_slave_sel;
5199         if (libresocsim_wait) begin
5200                 if ((~libresocsim_done)) begin
5201                         libresocsim_count <= (libresocsim_count - 1'd1);
5202                 end
5203         end else begin
5204                 libresocsim_count <= 20'd1000000;
5205         end
5206         libresocsim_interface0_bank_bus_dat_r <= 1'd0;
5207         if (libresocsim_csrbank0_sel) begin
5208                 case (libresocsim_interface0_bank_bus_adr[3:0])
5209                         1'd0: begin
5210                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_reset0_w;
5211                         end
5212                         1'd1: begin
5213                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch3_w;
5214                         end
5215                         2'd2: begin
5216                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch2_w;
5217                         end
5218                         2'd3: begin
5219                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch1_w;
5220                         end
5221                         3'd4: begin
5222                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch0_w;
5223                         end
5224                         3'd5: begin
5225                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors3_w;
5226                         end
5227                         3'd6: begin
5228                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors2_w;
5229                         end
5230                         3'd7: begin
5231                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors1_w;
5232                         end
5233                         4'd8: begin
5234                                 libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors0_w;
5235                         end
5236                 endcase
5237         end
5238         if (libresocsim_csrbank0_reset0_re) begin
5239                 libresocsim_reset_storage <= libresocsim_csrbank0_reset0_r;
5240         end
5241         libresocsim_reset_re <= libresocsim_csrbank0_reset0_re;
5242         if (libresocsim_csrbank0_scratch3_re) begin
5243                 libresocsim_scratch_storage[31:24] <= libresocsim_csrbank0_scratch3_r;
5244         end
5245         if (libresocsim_csrbank0_scratch2_re) begin
5246                 libresocsim_scratch_storage[23:16] <= libresocsim_csrbank0_scratch2_r;
5247         end
5248         if (libresocsim_csrbank0_scratch1_re) begin
5249                 libresocsim_scratch_storage[15:8] <= libresocsim_csrbank0_scratch1_r;
5250         end
5251         if (libresocsim_csrbank0_scratch0_re) begin
5252                 libresocsim_scratch_storage[7:0] <= libresocsim_csrbank0_scratch0_r;
5253         end
5254         libresocsim_scratch_re <= libresocsim_csrbank0_scratch0_re;
5255         libresocsim_interface1_bank_bus_dat_r <= 1'd0;
5256         if (libresocsim_csrbank1_sel) begin
5257                 case (libresocsim_interface1_bank_bus_adr[1:0])
5258                         1'd0: begin
5259                                 libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_oe0_w;
5260                         end
5261                         1'd1: begin
5262                                 libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_in_w;
5263                         end
5264                         2'd2: begin
5265                                 libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_out0_w;
5266                         end
5267                 endcase
5268         end
5269         if (libresocsim_csrbank1_oe0_re) begin
5270                 gpio0_oe_storage[7:0] <= libresocsim_csrbank1_oe0_r;
5271         end
5272         gpio0_oe_re <= libresocsim_csrbank1_oe0_re;
5273         if (libresocsim_csrbank1_out0_re) begin
5274                 gpio0_out_storage[7:0] <= libresocsim_csrbank1_out0_r;
5275         end
5276         gpio0_out_re <= libresocsim_csrbank1_out0_re;
5277         libresocsim_interface2_bank_bus_dat_r <= 1'd0;
5278         if (libresocsim_csrbank2_sel) begin
5279                 case (libresocsim_interface2_bank_bus_adr[1:0])
5280                         1'd0: begin
5281                                 libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_oe0_w;
5282                         end
5283                         1'd1: begin
5284                                 libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_in_w;
5285                         end
5286                         2'd2: begin
5287                                 libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_out0_w;
5288                         end
5289                 endcase
5290         end
5291         if (libresocsim_csrbank2_oe0_re) begin
5292                 gpio1_oe_storage[7:0] <= libresocsim_csrbank2_oe0_r;
5293         end
5294         gpio1_oe_re <= libresocsim_csrbank2_oe0_re;
5295         if (libresocsim_csrbank2_out0_re) begin
5296                 gpio1_out_storage[7:0] <= libresocsim_csrbank2_out0_r;
5297         end
5298         gpio1_out_re <= libresocsim_csrbank2_out0_re;
5299         libresocsim_interface3_bank_bus_dat_r <= 1'd0;
5300         if (libresocsim_csrbank3_sel) begin
5301                 case (libresocsim_interface3_bank_bus_adr[0])
5302                         1'd0: begin
5303                                 libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_w0_w;
5304                         end
5305                         1'd1: begin
5306                                 libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_r_w;
5307                         end
5308                 endcase
5309         end
5310         if (libresocsim_csrbank3_w0_re) begin
5311                 i2c_storage[2:0] <= libresocsim_csrbank3_w0_r;
5312         end
5313         i2c_re <= libresocsim_csrbank3_w0_re;
5314         libresocsim_interface4_bank_bus_dat_r <= 1'd0;
5315         if (libresocsim_csrbank4_sel) begin
5316                 case (libresocsim_interface4_bank_bus_adr[3:0])
5317                         1'd0: begin
5318                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_control0_w;
5319                         end
5320                         1'd1: begin
5321                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_command0_w;
5322                         end
5323                         2'd2: begin
5324                                 libresocsim_interface4_bank_bus_dat_r <= sdram_command_issue_w;
5325                         end
5326                         2'd3: begin
5327                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address1_w;
5328                         end
5329                         3'd4: begin
5330                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address0_w;
5331                         end
5332                         3'd5: begin
5333                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_baddress0_w;
5334                         end
5335                         3'd6: begin
5336                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata1_w;
5337                         end
5338                         3'd7: begin
5339                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata0_w;
5340                         end
5341                         4'd8: begin
5342                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata1_w;
5343                         end
5344                         4'd9: begin
5345                                 libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata0_w;
5346                         end
5347                 endcase
5348         end
5349         if (libresocsim_csrbank4_dfii_control0_re) begin
5350                 sdram_storage[3:0] <= libresocsim_csrbank4_dfii_control0_r;
5351         end
5352         sdram_re <= libresocsim_csrbank4_dfii_control0_re;
5353         if (libresocsim_csrbank4_dfii_pi0_command0_re) begin
5354                 sdram_command_storage[5:0] <= libresocsim_csrbank4_dfii_pi0_command0_r;
5355         end
5356         sdram_command_re <= libresocsim_csrbank4_dfii_pi0_command0_re;
5357         if (libresocsim_csrbank4_dfii_pi0_address1_re) begin
5358                 sdram_address_storage[12:8] <= libresocsim_csrbank4_dfii_pi0_address1_r;
5359         end
5360         if (libresocsim_csrbank4_dfii_pi0_address0_re) begin
5361                 sdram_address_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_address0_r;
5362         end
5363         sdram_address_re <= libresocsim_csrbank4_dfii_pi0_address0_re;
5364         if (libresocsim_csrbank4_dfii_pi0_baddress0_re) begin
5365                 sdram_baddress_storage[1:0] <= libresocsim_csrbank4_dfii_pi0_baddress0_r;
5366         end
5367         sdram_baddress_re <= libresocsim_csrbank4_dfii_pi0_baddress0_re;
5368         if (libresocsim_csrbank4_dfii_pi0_wrdata1_re) begin
5369                 sdram_wrdata_storage[15:8] <= libresocsim_csrbank4_dfii_pi0_wrdata1_r;
5370         end
5371         if (libresocsim_csrbank4_dfii_pi0_wrdata0_re) begin
5372                 sdram_wrdata_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_wrdata0_r;
5373         end
5374         sdram_wrdata_re <= libresocsim_csrbank4_dfii_pi0_wrdata0_re;
5375         libresocsim_interface5_bank_bus_dat_r <= 1'd0;
5376         if (libresocsim_csrbank5_sel) begin
5377                 case (libresocsim_interface5_bank_bus_adr[4:0])
5378                         1'd0: begin
5379                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load3_w;
5380                         end
5381                         1'd1: begin
5382                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load2_w;
5383                         end
5384                         2'd2: begin
5385                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load1_w;
5386                         end
5387                         2'd3: begin
5388                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load0_w;
5389                         end
5390                         3'd4: begin
5391                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload3_w;
5392                         end
5393                         3'd5: begin
5394                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload2_w;
5395                         end
5396                         3'd6: begin
5397                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload1_w;
5398                         end
5399                         3'd7: begin
5400                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload0_w;
5401                         end
5402                         4'd8: begin
5403                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_en0_w;
5404                         end
5405                         4'd9: begin
5406                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_update_value0_w;
5407                         end
5408                         4'd10: begin
5409                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value3_w;
5410                         end
5411                         4'd11: begin
5412                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value2_w;
5413                         end
5414                         4'd12: begin
5415                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value1_w;
5416                         end
5417                         4'd13: begin
5418                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value0_w;
5419                         end
5420                         4'd14: begin
5421                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_status_w;
5422                         end
5423                         4'd15: begin
5424                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_pending_w;
5425                         end
5426                         5'd16: begin
5427                                 libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_ev_enable0_w;
5428                         end
5429                 endcase
5430         end
5431         if (libresocsim_csrbank5_load3_re) begin
5432                 libresocsim_load_storage[31:24] <= libresocsim_csrbank5_load3_r;
5433         end
5434         if (libresocsim_csrbank5_load2_re) begin
5435                 libresocsim_load_storage[23:16] <= libresocsim_csrbank5_load2_r;
5436         end
5437         if (libresocsim_csrbank5_load1_re) begin
5438                 libresocsim_load_storage[15:8] <= libresocsim_csrbank5_load1_r;
5439         end
5440         if (libresocsim_csrbank5_load0_re) begin
5441                 libresocsim_load_storage[7:0] <= libresocsim_csrbank5_load0_r;
5442         end
5443         libresocsim_load_re <= libresocsim_csrbank5_load0_re;
5444         if (libresocsim_csrbank5_reload3_re) begin
5445                 libresocsim_reload_storage[31:24] <= libresocsim_csrbank5_reload3_r;
5446         end
5447         if (libresocsim_csrbank5_reload2_re) begin
5448                 libresocsim_reload_storage[23:16] <= libresocsim_csrbank5_reload2_r;
5449         end
5450         if (libresocsim_csrbank5_reload1_re) begin
5451                 libresocsim_reload_storage[15:8] <= libresocsim_csrbank5_reload1_r;
5452         end
5453         if (libresocsim_csrbank5_reload0_re) begin
5454                 libresocsim_reload_storage[7:0] <= libresocsim_csrbank5_reload0_r;
5455         end
5456         libresocsim_reload_re <= libresocsim_csrbank5_reload0_re;
5457         if (libresocsim_csrbank5_en0_re) begin
5458                 libresocsim_en_storage <= libresocsim_csrbank5_en0_r;
5459         end
5460         libresocsim_en_re <= libresocsim_csrbank5_en0_re;
5461         if (libresocsim_csrbank5_update_value0_re) begin
5462                 libresocsim_update_value_storage <= libresocsim_csrbank5_update_value0_r;
5463         end
5464         libresocsim_update_value_re <= libresocsim_csrbank5_update_value0_re;
5465         if (libresocsim_csrbank5_ev_enable0_re) begin
5466                 libresocsim_eventmanager_storage <= libresocsim_csrbank5_ev_enable0_r;
5467         end
5468         libresocsim_eventmanager_re <= libresocsim_csrbank5_ev_enable0_re;
5469         libresocsim_interface6_bank_bus_dat_r <= 1'd0;
5470         if (libresocsim_csrbank6_sel) begin
5471                 case (libresocsim_interface6_bank_bus_adr[2:0])
5472                         1'd0: begin
5473                                 libresocsim_interface6_bank_bus_dat_r <= rxtx_w;
5474                         end
5475                         1'd1: begin
5476                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txfull_w;
5477                         end
5478                         2'd2: begin
5479                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxempty_w;
5480                         end
5481                         2'd3: begin
5482                                 libresocsim_interface6_bank_bus_dat_r <= eventmanager_status_w;
5483                         end
5484                         3'd4: begin
5485                                 libresocsim_interface6_bank_bus_dat_r <= eventmanager_pending_w;
5486                         end
5487                         3'd5: begin
5488                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_ev_enable0_w;
5489                         end
5490                         3'd6: begin
5491                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txempty_w;
5492                         end
5493                         3'd7: begin
5494                                 libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxfull_w;
5495                         end
5496                 endcase
5497         end
5498         if (libresocsim_csrbank6_ev_enable0_re) begin
5499                 eventmanager_storage[1:0] <= libresocsim_csrbank6_ev_enable0_r;
5500         end
5501         eventmanager_re <= libresocsim_csrbank6_ev_enable0_re;
5502         libresocsim_interface7_bank_bus_dat_r <= 1'd0;
5503         if (libresocsim_csrbank7_sel) begin
5504                 case (libresocsim_interface7_bank_bus_adr[1:0])
5505                         1'd0: begin
5506                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word3_w;
5507                         end
5508                         1'd1: begin
5509                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word2_w;
5510                         end
5511                         2'd2: begin
5512                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word1_w;
5513                         end
5514                         2'd3: begin
5515                                 libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word0_w;
5516                         end
5517                 endcase
5518         end
5519         if (libresocsim_csrbank7_tuning_word3_re) begin
5520                 uart_phy_storage[31:24] <= libresocsim_csrbank7_tuning_word3_r;
5521         end
5522         if (libresocsim_csrbank7_tuning_word2_re) begin
5523                 uart_phy_storage[23:16] <= libresocsim_csrbank7_tuning_word2_r;
5524         end
5525         if (libresocsim_csrbank7_tuning_word1_re) begin
5526                 uart_phy_storage[15:8] <= libresocsim_csrbank7_tuning_word1_r;
5527         end
5528         if (libresocsim_csrbank7_tuning_word0_re) begin
5529                 uart_phy_storage[7:0] <= libresocsim_csrbank7_tuning_word0_r;
5530         end
5531         uart_phy_re <= libresocsim_csrbank7_tuning_word0_re;
5532         if (sys_rst_1) begin
5533                 libresocsim_reset_storage <= 1'd0;
5534                 libresocsim_reset_re <= 1'd0;
5535                 libresocsim_scratch_storage <= 32'd305419896;
5536                 libresocsim_scratch_re <= 1'd0;
5537                 libresocsim_bus_errors <= 32'd0;
5538                 libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1;
5539                 libresocsim_converter0_counter <= 1'd0;
5540                 libresocsim_converter1_counter <= 1'd0;
5541                 libresocsim_ram_bus_ack <= 1'd0;
5542                 libresocsim_load_storage <= 32'd0;
5543                 libresocsim_load_re <= 1'd0;
5544                 libresocsim_reload_storage <= 32'd0;
5545                 libresocsim_reload_re <= 1'd0;
5546                 libresocsim_en_storage <= 1'd0;
5547                 libresocsim_en_re <= 1'd0;
5548                 libresocsim_update_value_storage <= 1'd0;
5549                 libresocsim_update_value_re <= 1'd0;
5550                 libresocsim_value_status <= 32'd0;
5551                 libresocsim_zero_pending <= 1'd0;
5552                 libresocsim_zero_old_trigger <= 1'd0;
5553                 libresocsim_eventmanager_storage <= 1'd0;
5554                 libresocsim_eventmanager_re <= 1'd0;
5555                 libresocsim_value <= 32'd0;
5556                 ram_bus_ram_bus_ack <= 1'd0;
5557                 dfi_p0_rddata_valid <= 1'd0;
5558                 rddata_en <= 3'd0;
5559                 sdram_storage <= 4'd1;
5560                 sdram_re <= 1'd0;
5561                 sdram_command_storage <= 6'd0;
5562                 sdram_command_re <= 1'd0;
5563                 sdram_address_re <= 1'd0;
5564                 sdram_baddress_re <= 1'd0;
5565                 sdram_wrdata_re <= 1'd0;
5566                 sdram_status <= 16'd0;
5567                 sdram_dfi_p0_address <= 13'd0;
5568                 sdram_dfi_p0_bank <= 2'd0;
5569                 sdram_dfi_p0_cas_n <= 1'd1;
5570                 sdram_dfi_p0_cs_n <= 1'd1;
5571                 sdram_dfi_p0_ras_n <= 1'd1;
5572                 sdram_dfi_p0_we_n <= 1'd1;
5573                 sdram_dfi_p0_wrdata_en <= 1'd0;
5574                 sdram_dfi_p0_rddata_en <= 1'd0;
5575                 sdram_timer_count1 <= 10'd781;
5576                 sdram_postponer_req_o <= 1'd0;
5577                 sdram_postponer_count <= 1'd0;
5578                 sdram_sequencer_done1 <= 1'd0;
5579                 sdram_sequencer_counter <= 4'd0;
5580                 sdram_sequencer_count <= 1'd0;
5581                 sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0;
5582                 sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0;
5583                 sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0;
5584                 sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0;
5585                 sdram_bankmachine0_row <= 13'd0;
5586                 sdram_bankmachine0_row_opened <= 1'd0;
5587                 sdram_bankmachine0_twtpcon_ready <= 1'd0;
5588                 sdram_bankmachine0_twtpcon_count <= 3'd0;
5589                 sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0;
5590                 sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0;
5591                 sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0;
5592                 sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0;
5593                 sdram_bankmachine1_row <= 13'd0;
5594                 sdram_bankmachine1_row_opened <= 1'd0;
5595                 sdram_bankmachine1_twtpcon_ready <= 1'd0;
5596                 sdram_bankmachine1_twtpcon_count <= 3'd0;
5597                 sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0;
5598                 sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0;
5599                 sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0;
5600                 sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0;
5601                 sdram_bankmachine2_row <= 13'd0;
5602                 sdram_bankmachine2_row_opened <= 1'd0;
5603                 sdram_bankmachine2_twtpcon_ready <= 1'd0;
5604                 sdram_bankmachine2_twtpcon_count <= 3'd0;
5605                 sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0;
5606                 sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0;
5607                 sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0;
5608                 sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0;
5609                 sdram_bankmachine3_row <= 13'd0;
5610                 sdram_bankmachine3_row_opened <= 1'd0;
5611                 sdram_bankmachine3_twtpcon_ready <= 1'd0;
5612                 sdram_bankmachine3_twtpcon_count <= 3'd0;
5613                 sdram_choose_cmd_grant <= 2'd0;
5614                 sdram_choose_req_grant <= 2'd0;
5615                 sdram_tccdcon_ready <= 1'd0;
5616                 sdram_tccdcon_count <= 1'd0;
5617                 sdram_twtrcon_ready <= 1'd0;
5618                 sdram_twtrcon_count <= 3'd0;
5619                 sdram_time0 <= 5'd0;
5620                 sdram_time1 <= 4'd0;
5621                 converter_counter <= 1'd0;
5622                 cmd_consumed <= 1'd0;
5623                 wdata_consumed <= 1'd0;
5624                 uart_phy_storage <= 32'd9895604;
5625                 uart_phy_re <= 1'd0;
5626                 uart_phy_sink_ready <= 1'd0;
5627                 uart_phy_uart_clk_txen <= 1'd0;
5628                 uart_phy_tx_busy <= 1'd0;
5629                 uart_phy_source_valid <= 1'd0;
5630                 uart_phy_uart_clk_rxen <= 1'd0;
5631                 uart_phy_rx_r <= 1'd0;
5632                 uart_phy_rx_busy <= 1'd0;
5633                 tx_pending <= 1'd0;
5634                 tx_old_trigger <= 1'd0;
5635                 rx_pending <= 1'd0;
5636                 rx_old_trigger <= 1'd0;
5637                 eventmanager_storage <= 2'd0;
5638                 eventmanager_re <= 1'd0;
5639                 tx_fifo_readable <= 1'd0;
5640                 tx_fifo_level0 <= 5'd0;
5641                 tx_fifo_produce <= 4'd0;
5642                 tx_fifo_consume <= 4'd0;
5643                 rx_fifo_readable <= 1'd0;
5644                 rx_fifo_level0 <= 5'd0;
5645                 rx_fifo_produce <= 4'd0;
5646                 rx_fifo_consume <= 4'd0;
5647                 gpio0_oe_storage <= 8'd0;
5648                 gpio0_oe_re <= 1'd0;
5649                 gpio0_out_storage <= 8'd0;
5650                 gpio0_out_re <= 1'd0;
5651                 gpio1_oe_storage <= 8'd0;
5652                 gpio1_oe_re <= 1'd0;
5653                 gpio1_out_storage <= 8'd0;
5654                 gpio1_out_re <= 1'd0;
5655                 dummy <= 36'd0;
5656                 i2c_storage <= 3'd0;
5657                 i2c_re <= 1'd0;
5658                 subfragments_converter0_state <= 1'd0;
5659                 subfragments_converter1_state <= 1'd0;
5660                 subfragments_refresher_state <= 2'd0;
5661                 subfragments_bankmachine0_state <= 3'd0;
5662                 subfragments_bankmachine1_state <= 3'd0;
5663                 subfragments_bankmachine2_state <= 3'd0;
5664                 subfragments_bankmachine3_state <= 3'd0;
5665                 subfragments_multiplexer_state <= 3'd0;
5666                 subfragments_new_master_wdata_ready <= 1'd0;
5667                 subfragments_new_master_rdata_valid0 <= 1'd0;
5668                 subfragments_new_master_rdata_valid1 <= 1'd0;
5669                 subfragments_new_master_rdata_valid2 <= 1'd0;
5670                 subfragments_new_master_rdata_valid3 <= 1'd0;
5671                 subfragments_state <= 1'd0;
5672                 libresocsim_libresocsim_we <= 1'd0;
5673                 libresocsim_grant <= 2'd0;
5674                 libresocsim_slave_sel_r <= 10'd0;
5675                 libresocsim_count <= 20'd1000000;
5676                 libresocsim_state <= 2'd0;
5677         end
5678         regs0 <= libresocsim_libresoc_constraintmanager_uart_rx;
5679         regs1 <= regs0;
5680 end
5681
5682 reg [31:0] mem[0:31];
5683 reg [4:0] memadr;
5684 always @(posedge sys_clk_1) begin
5685         if (libresocsim_we[0])
5686                 mem[libresocsim_adr][7:0] <= libresocsim_dat_w[7:0];
5687         if (libresocsim_we[1])
5688                 mem[libresocsim_adr][15:8] <= libresocsim_dat_w[15:8];
5689         if (libresocsim_we[2])
5690                 mem[libresocsim_adr][23:16] <= libresocsim_dat_w[23:16];
5691         if (libresocsim_we[3])
5692                 mem[libresocsim_adr][31:24] <= libresocsim_dat_w[31:24];
5693         memadr <= libresocsim_adr;
5694 end
5695
5696 assign libresocsim_dat_r = mem[memadr];
5697
5698 initial begin
5699         $readmemh("mem.init", mem);
5700 end
5701
5702 reg [31:0] mem_1[0:31];
5703 reg [4:0] memadr_1;
5704 always @(posedge sys_clk_1) begin
5705         if (ram_we[0])
5706                 mem_1[ram_adr][7:0] <= ram_dat_w[7:0];
5707         if (ram_we[1])
5708                 mem_1[ram_adr][15:8] <= ram_dat_w[15:8];
5709         if (ram_we[2])
5710                 mem_1[ram_adr][23:16] <= ram_dat_w[23:16];
5711         if (ram_we[3])
5712                 mem_1[ram_adr][31:24] <= ram_dat_w[31:24];
5713         memadr_1 <= ram_adr;
5714 end
5715
5716 assign ram_dat_r = mem_1[memadr_1];
5717
5718 initial begin
5719         $readmemh("mem_1.init", mem_1);
5720 end
5721
5722 reg [24:0] storage[0:7];
5723 reg [24:0] memdat;
5724 always @(posedge sys_clk_1) begin
5725         if (sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
5726                 storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
5727         memdat <= storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
5728 end
5729
5730 always @(posedge sys_clk_1) begin
5731 end
5732
5733 assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
5734 assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
5735
5736 reg [24:0] storage_1[0:7];
5737 reg [24:0] memdat_1;
5738 always @(posedge sys_clk_1) begin
5739         if (sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
5740                 storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
5741         memdat_1 <= storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
5742 end
5743
5744 always @(posedge sys_clk_1) begin
5745 end
5746
5747 assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
5748 assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
5749
5750 reg [24:0] storage_2[0:7];
5751 reg [24:0] memdat_2;
5752 always @(posedge sys_clk_1) begin
5753         if (sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
5754                 storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
5755         memdat_2 <= storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
5756 end
5757
5758 always @(posedge sys_clk_1) begin
5759 end
5760
5761 assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
5762 assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
5763
5764 reg [24:0] storage_3[0:7];
5765 reg [24:0] memdat_3;
5766 always @(posedge sys_clk_1) begin
5767         if (sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
5768                 storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
5769         memdat_3 <= storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
5770 end
5771
5772 always @(posedge sys_clk_1) begin
5773 end
5774
5775 assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
5776 assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
5777
5778 reg [9:0] storage_4[0:15];
5779 reg [9:0] memdat_4;
5780 reg [9:0] memdat_5;
5781 always @(posedge sys_clk_1) begin
5782         if (tx_fifo_wrport_we)
5783                 storage_4[tx_fifo_wrport_adr] <= tx_fifo_wrport_dat_w;
5784         memdat_4 <= storage_4[tx_fifo_wrport_adr];
5785 end
5786
5787 always @(posedge sys_clk_1) begin
5788         if (tx_fifo_rdport_re)
5789                 memdat_5 <= storage_4[tx_fifo_rdport_adr];
5790 end
5791
5792 assign tx_fifo_wrport_dat_r = memdat_4;
5793 assign tx_fifo_rdport_dat_r = memdat_5;
5794
5795 reg [9:0] storage_5[0:15];
5796 reg [9:0] memdat_6;
5797 reg [9:0] memdat_7;
5798 always @(posedge sys_clk_1) begin
5799         if (rx_fifo_wrport_we)
5800                 storage_5[rx_fifo_wrport_adr] <= rx_fifo_wrport_dat_w;
5801         memdat_6 <= storage_5[rx_fifo_wrport_adr];
5802 end
5803
5804 always @(posedge sys_clk_1) begin
5805         if (rx_fifo_rdport_re)
5806                 memdat_7 <= storage_5[rx_fifo_rdport_adr];
5807 end
5808
5809 assign rx_fifo_wrport_dat_r = memdat_6;
5810 assign rx_fifo_rdport_dat_r = memdat_7;
5811
5812 test_issuer test_issuer(
5813         .TAP_bus__tck(libresocsim_libresoc_jtag_tck),
5814         .TAP_bus__tdi(libresocsim_libresoc_jtag_tdi),
5815         .TAP_bus__tms(libresocsim_libresoc_jtag_tms),
5816         .clk(sys_clk_1),
5817         .ref_clk(sys_clk),
5818         .clk_sel_i(libresocsim_libresoc_clk_sel),
5819         .core_bigendian_i(1'd0),
5820         .dbus__ack(libresocsim_libresoc_dbus_ack),
5821         .dbus__bte(1'd0),
5822         .dbus__cti(1'd0),
5823         .dbus__dat_r(libresocsim_libresoc_dbus_dat_r),
5824         .dbus__err(libresocsim_libresoc_dbus_err),
5825         .eint_0__pad__i(eint_0),
5826         .eint_1__pad__i(eint_1),
5827         .eint_2__pad__i(eint_2),
5828         .gpio_e10__core__o(libresocsim_libresoc_constraintmanager_gpio_o[10]),
5829         .gpio_e10__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[10]),
5830         .gpio_e10__pad__i(gpio_i[10]),
5831         .gpio_e11__core__o(libresocsim_libresoc_constraintmanager_gpio_o[11]),
5832         .gpio_e11__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[11]),
5833         .gpio_e11__pad__i(gpio_i[11]),
5834         .gpio_e12__core__o(libresocsim_libresoc_constraintmanager_gpio_o[12]),
5835         .gpio_e12__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[12]),
5836         .gpio_e12__pad__i(gpio_i[12]),
5837         .gpio_e13__core__o(libresocsim_libresoc_constraintmanager_gpio_o[13]),
5838         .gpio_e13__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[13]),
5839         .gpio_e13__pad__i(gpio_i[13]),
5840         .gpio_e14__core__o(libresocsim_libresoc_constraintmanager_gpio_o[14]),
5841         .gpio_e14__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[14]),
5842         .gpio_e14__pad__i(gpio_i[14]),
5843         .gpio_e15__core__o(libresocsim_libresoc_constraintmanager_gpio_o[15]),
5844         .gpio_e15__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[15]),
5845         .gpio_e15__pad__i(gpio_i[15]),
5846         .gpio_e8__core__o(libresocsim_libresoc_constraintmanager_gpio_o[8]),
5847         .gpio_e8__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[8]),
5848         .gpio_e8__pad__i(gpio_i[8]),
5849         .gpio_e9__core__o(libresocsim_libresoc_constraintmanager_gpio_o[9]),
5850         .gpio_e9__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[9]),
5851         .gpio_e9__pad__i(gpio_i[9]),
5852         .gpio_s0__core__o(libresocsim_libresoc_constraintmanager_gpio_o[0]),
5853         .gpio_s0__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[0]),
5854         .gpio_s0__pad__i(gpio_i[0]),
5855         .gpio_s1__core__o(libresocsim_libresoc_constraintmanager_gpio_o[1]),
5856         .gpio_s1__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[1]),
5857         .gpio_s1__pad__i(gpio_i[1]),
5858         .gpio_s2__core__o(libresocsim_libresoc_constraintmanager_gpio_o[2]),
5859         .gpio_s2__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[2]),
5860         .gpio_s2__pad__i(gpio_i[2]),
5861         .gpio_s3__core__o(libresocsim_libresoc_constraintmanager_gpio_o[3]),
5862         .gpio_s3__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[3]),
5863         .gpio_s3__pad__i(gpio_i[3]),
5864         .gpio_s4__core__o(libresocsim_libresoc_constraintmanager_gpio_o[4]),
5865         .gpio_s4__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[4]),
5866         .gpio_s4__pad__i(gpio_i[4]),
5867         .gpio_s5__core__o(libresocsim_libresoc_constraintmanager_gpio_o[5]),
5868         .gpio_s5__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[5]),
5869         .gpio_s5__pad__i(gpio_i[5]),
5870         .gpio_s6__core__o(libresocsim_libresoc_constraintmanager_gpio_o[6]),
5871         .gpio_s6__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[6]),
5872         .gpio_s6__pad__i(gpio_i[6]),
5873         .gpio_s7__core__o(libresocsim_libresoc_constraintmanager_gpio_o[7]),
5874         .gpio_s7__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[7]),
5875         .gpio_s7__pad__i(gpio_i[7]),
5876         .ibus__ack(libresocsim_libresoc_ibus_ack),
5877         .ibus__bte(1'd0),
5878         .ibus__cti(1'd0),
5879         .ibus__dat_r(libresocsim_libresoc_ibus_dat_r),
5880         .ibus__err(libresocsim_libresoc_ibus_err),
5881         .icp_wb__adr(libresocsim_libresoc_xics_icp_adr),
5882         .icp_wb__cyc(libresocsim_libresoc_xics_icp_cyc),
5883         .icp_wb__dat_w(libresocsim_libresoc_xics_icp_dat_w),
5884         .icp_wb__sel(libresocsim_libresoc_xics_icp_sel),
5885         .icp_wb__stb(libresocsim_libresoc_xics_icp_stb),
5886         .icp_wb__we(libresocsim_libresoc_xics_icp_we),
5887         .ics_wb__adr(libresocsim_libresoc_xics_ics_adr),
5888         .ics_wb__cyc(libresocsim_libresoc_xics_ics_cyc),
5889         .ics_wb__dat_w(libresocsim_libresoc_xics_ics_dat_w),
5890         .ics_wb__sel(libresocsim_libresoc_xics_ics_sel),
5891         .ics_wb__stb(libresocsim_libresoc_xics_ics_stb),
5892         .ics_wb__we(libresocsim_libresoc_xics_ics_we),
5893         .int_level_i(libresocsim_libresoc_interrupt),
5894         .jtag_wb__ack(libresocsim_libresoc_jtag_wb_ack),
5895         .jtag_wb__dat_r(libresocsim_libresoc_jtag_wb_dat_r),
5896         .jtag_wb__err(libresocsim_libresoc_jtag_wb_err),
5897         .mspi0_clk__core__o(libresocsim_libresoc_constraintmanager_spimaster_clk),
5898         .mspi0_cs_n__core__o(libresocsim_libresoc_constraintmanager_spimaster_cs_n),
5899         .mspi0_miso__pad__i(spimaster_miso),
5900         .mspi0_mosi__core__o(libresocsim_libresoc_constraintmanager_spimaster_mosi),
5901         .mtwi_scl__core__o(libresocsim_libresoc_constraintmanager_i2c_scl),
5902         .mtwi_sda__core__o(libresocsim_libresoc_constraintmanager_i2c_sda_o),
5903         .mtwi_sda__core__oe(libresocsim_libresoc_constraintmanager_i2c_sda_oe),
5904         .mtwi_sda__pad__i(i2c_sda_i),
5905         .pc_i(libresocsim_libresoc0),
5906         .pc_i_ok(1'd0),
5907         .rst((sys_rst_1 | libresocsim_libresoc_reset)),
5908         .sdr_a_0__core__o(libresocsim_libresoc_constraintmanager_sdram_a[0]),
5909         .sdr_a_10__core__o(libresocsim_libresoc_constraintmanager_sdram_a[10]),
5910         .sdr_a_11__core__o(libresocsim_libresoc_constraintmanager_sdram_a[11]),
5911         .sdr_a_12__core__o(libresocsim_libresoc_constraintmanager_sdram_a[12]),
5912         .sdr_a_1__core__o(libresocsim_libresoc_constraintmanager_sdram_a[1]),
5913         .sdr_a_2__core__o(libresocsim_libresoc_constraintmanager_sdram_a[2]),
5914         .sdr_a_3__core__o(libresocsim_libresoc_constraintmanager_sdram_a[3]),
5915         .sdr_a_4__core__o(libresocsim_libresoc_constraintmanager_sdram_a[4]),
5916         .sdr_a_5__core__o(libresocsim_libresoc_constraintmanager_sdram_a[5]),
5917         .sdr_a_6__core__o(libresocsim_libresoc_constraintmanager_sdram_a[6]),
5918         .sdr_a_7__core__o(libresocsim_libresoc_constraintmanager_sdram_a[7]),
5919         .sdr_a_8__core__o(libresocsim_libresoc_constraintmanager_sdram_a[8]),
5920         .sdr_a_9__core__o(libresocsim_libresoc_constraintmanager_sdram_a[9]),
5921         .sdr_ba_0__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[0]),
5922         .sdr_ba_1__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[1]),
5923         .sdr_cas_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cas_n),
5924         .sdr_cke__core__o(libresocsim_libresoc_constraintmanager_sdram_cke),
5925         .sdr_clock__core__o(libresocsim_libresoc_constraintmanager_sdram_clock),
5926         .sdr_cs_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cs_n),
5927         .sdr_dm_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[0]),
5928         .sdr_dm_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[1]),
5929         .sdr_dq_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[0]),
5930         .sdr_dq_0__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[0]),
5931         .sdr_dq_0__pad__i(sdram_dq_i[0]),
5932         .sdr_dq_10__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[10]),
5933         .sdr_dq_10__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[10]),
5934         .sdr_dq_10__pad__i(sdram_dq_i[10]),
5935         .sdr_dq_11__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[11]),
5936         .sdr_dq_11__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[11]),
5937         .sdr_dq_11__pad__i(sdram_dq_i[11]),
5938         .sdr_dq_12__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[12]),
5939         .sdr_dq_12__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[12]),
5940         .sdr_dq_12__pad__i(sdram_dq_i[12]),
5941         .sdr_dq_13__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[13]),
5942         .sdr_dq_13__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[13]),
5943         .sdr_dq_13__pad__i(sdram_dq_i[13]),
5944         .sdr_dq_14__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[14]),
5945         .sdr_dq_14__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[14]),
5946         .sdr_dq_14__pad__i(sdram_dq_i[14]),
5947         .sdr_dq_15__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[15]),
5948         .sdr_dq_15__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[15]),
5949         .sdr_dq_15__pad__i(sdram_dq_i[15]),
5950         .sdr_dq_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[1]),
5951         .sdr_dq_1__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[1]),
5952         .sdr_dq_1__pad__i(sdram_dq_i[1]),
5953         .sdr_dq_2__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[2]),
5954         .sdr_dq_2__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[2]),
5955         .sdr_dq_2__pad__i(sdram_dq_i[2]),
5956         .sdr_dq_3__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[3]),
5957         .sdr_dq_3__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[3]),
5958         .sdr_dq_3__pad__i(sdram_dq_i[3]),
5959         .sdr_dq_4__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[4]),
5960         .sdr_dq_4__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[4]),
5961         .sdr_dq_4__pad__i(sdram_dq_i[4]),
5962         .sdr_dq_5__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[5]),
5963         .sdr_dq_5__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[5]),
5964         .sdr_dq_5__pad__i(sdram_dq_i[5]),
5965         .sdr_dq_6__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[6]),
5966         .sdr_dq_6__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[6]),
5967         .sdr_dq_6__pad__i(sdram_dq_i[6]),
5968         .sdr_dq_7__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[7]),
5969         .sdr_dq_7__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[7]),
5970         .sdr_dq_7__pad__i(sdram_dq_i[7]),
5971         .sdr_dq_8__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[8]),
5972         .sdr_dq_8__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[8]),
5973         .sdr_dq_8__pad__i(sdram_dq_i[8]),
5974         .sdr_dq_9__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[9]),
5975         .sdr_dq_9__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[9]),
5976         .sdr_dq_9__pad__i(sdram_dq_i[9]),
5977         .sdr_ras_n__core__o(libresocsim_libresoc_constraintmanager_sdram_ras_n),
5978         .sdr_we_n__core__o(libresocsim_libresoc_constraintmanager_sdram_we_n),
5979         .sram4k_0_wb__adr(libresocsim_libresoc_interface0_adr),
5980         .sram4k_0_wb__cyc(libresocsim_libresoc_interface0_cyc),
5981         .sram4k_0_wb__dat_w(libresocsim_libresoc_interface0_dat_w),
5982         .sram4k_0_wb__sel(libresocsim_libresoc_interface0_sel),
5983         .sram4k_0_wb__stb(libresocsim_libresoc_interface0_stb),
5984         .sram4k_0_wb__we(libresocsim_libresoc_interface0_we),
5985         .sram4k_1_wb__adr(libresocsim_libresoc_interface1_adr),
5986         .sram4k_1_wb__cyc(libresocsim_libresoc_interface1_cyc),
5987         .sram4k_1_wb__dat_w(libresocsim_libresoc_interface1_dat_w),
5988         .sram4k_1_wb__sel(libresocsim_libresoc_interface1_sel),
5989         .sram4k_1_wb__stb(libresocsim_libresoc_interface1_stb),
5990         .sram4k_1_wb__we(libresocsim_libresoc_interface1_we),
5991         .sram4k_2_wb__adr(libresocsim_libresoc_interface2_adr),
5992         .sram4k_2_wb__cyc(libresocsim_libresoc_interface2_cyc),
5993         .sram4k_2_wb__dat_w(libresocsim_libresoc_interface2_dat_w),
5994         .sram4k_2_wb__sel(libresocsim_libresoc_interface2_sel),
5995         .sram4k_2_wb__stb(libresocsim_libresoc_interface2_stb),
5996         .sram4k_2_wb__we(libresocsim_libresoc_interface2_we),
5997         .sram4k_3_wb__adr(libresocsim_libresoc_interface3_adr),
5998         .sram4k_3_wb__cyc(libresocsim_libresoc_interface3_cyc),
5999         .sram4k_3_wb__dat_w(libresocsim_libresoc_interface3_dat_w),
6000         .sram4k_3_wb__sel(libresocsim_libresoc_interface3_sel),
6001         .sram4k_3_wb__stb(libresocsim_libresoc_interface3_stb),
6002         .sram4k_3_wb__we(libresocsim_libresoc_interface3_we),
6003         .TAP_bus__tdo(libresocsim_libresoc_jtag_tdo),
6004         .busy_o(libresocsim_libresoc1),
6005         .dbus__adr(libresocsim_libresoc_dbus_adr),
6006         .dbus__cyc(libresocsim_libresoc_dbus_cyc),
6007         .dbus__dat_w(libresocsim_libresoc_dbus_dat_w),
6008         .dbus__sel(libresocsim_libresoc_dbus_sel),
6009         .dbus__stb(libresocsim_libresoc_dbus_stb),
6010         .dbus__we(libresocsim_libresoc_dbus_we),
6011         .eint_0__core__i(libresocsim_libresoc_constraintmanager_eint_0),
6012         .eint_1__core__i(libresocsim_libresoc_constraintmanager_eint_1),
6013         .eint_2__core__i(libresocsim_libresoc_constraintmanager_eint_2),
6014         .gpio_e10__core__i(libresocsim_libresoc_constraintmanager_gpio_i[10]),
6015         .gpio_e10__pad__o(gpio_o[10]),
6016         .gpio_e10__pad__oe(gpio_oe[10]),
6017         .gpio_e11__core__i(libresocsim_libresoc_constraintmanager_gpio_i[11]),
6018         .gpio_e11__pad__o(gpio_o[11]),
6019         .gpio_e11__pad__oe(gpio_oe[11]),
6020         .gpio_e12__core__i(libresocsim_libresoc_constraintmanager_gpio_i[12]),
6021         .gpio_e12__pad__o(gpio_o[12]),
6022         .gpio_e12__pad__oe(gpio_oe[12]),
6023         .gpio_e13__core__i(libresocsim_libresoc_constraintmanager_gpio_i[13]),
6024         .gpio_e13__pad__o(gpio_o[13]),
6025         .gpio_e13__pad__oe(gpio_oe[13]),
6026         .gpio_e14__core__i(libresocsim_libresoc_constraintmanager_gpio_i[14]),
6027         .gpio_e14__pad__o(gpio_o[14]),
6028         .gpio_e14__pad__oe(gpio_oe[14]),
6029         .gpio_e15__core__i(libresocsim_libresoc_constraintmanager_gpio_i[15]),
6030         .gpio_e15__pad__o(gpio_o[15]),
6031         .gpio_e15__pad__oe(gpio_oe[15]),
6032         .gpio_e8__core__i(libresocsim_libresoc_constraintmanager_gpio_i[8]),
6033         .gpio_e8__pad__o(gpio_o[8]),
6034         .gpio_e8__pad__oe(gpio_oe[8]),
6035         .gpio_e9__core__i(libresocsim_libresoc_constraintmanager_gpio_i[9]),
6036         .gpio_e9__pad__o(gpio_o[9]),
6037         .gpio_e9__pad__oe(gpio_oe[9]),
6038         .gpio_s0__core__i(libresocsim_libresoc_constraintmanager_gpio_i[0]),
6039         .gpio_s0__pad__o(gpio_o[0]),
6040         .gpio_s0__pad__oe(gpio_oe[0]),
6041         .gpio_s1__core__i(libresocsim_libresoc_constraintmanager_gpio_i[1]),
6042         .gpio_s1__pad__o(gpio_o[1]),
6043         .gpio_s1__pad__oe(gpio_oe[1]),
6044         .gpio_s2__core__i(libresocsim_libresoc_constraintmanager_gpio_i[2]),
6045         .gpio_s2__pad__o(gpio_o[2]),
6046         .gpio_s2__pad__oe(gpio_oe[2]),
6047         .gpio_s3__core__i(libresocsim_libresoc_constraintmanager_gpio_i[3]),
6048         .gpio_s3__pad__o(gpio_o[3]),
6049         .gpio_s3__pad__oe(gpio_oe[3]),
6050         .gpio_s4__core__i(libresocsim_libresoc_constraintmanager_gpio_i[4]),
6051         .gpio_s4__pad__o(gpio_o[4]),
6052         .gpio_s4__pad__oe(gpio_oe[4]),
6053         .gpio_s5__core__i(libresocsim_libresoc_constraintmanager_gpio_i[5]),
6054         .gpio_s5__pad__o(gpio_o[5]),
6055         .gpio_s5__pad__oe(gpio_oe[5]),
6056         .gpio_s6__core__i(libresocsim_libresoc_constraintmanager_gpio_i[6]),
6057         .gpio_s6__pad__o(gpio_o[6]),
6058         .gpio_s6__pad__oe(gpio_oe[6]),
6059         .gpio_s7__core__i(libresocsim_libresoc_constraintmanager_gpio_i[7]),
6060         .gpio_s7__pad__o(gpio_o[7]),
6061         .gpio_s7__pad__oe(gpio_oe[7]),
6062         .ibus__adr(libresocsim_libresoc_ibus_adr),
6063         .ibus__cyc(libresocsim_libresoc_ibus_cyc),
6064         .ibus__dat_w(libresocsim_libresoc_ibus_dat_w),
6065         .ibus__sel(libresocsim_libresoc_ibus_sel),
6066         .ibus__stb(libresocsim_libresoc_ibus_stb),
6067         .ibus__we(libresocsim_libresoc_ibus_we),
6068         .icp_wb__ack(libresocsim_libresoc_xics_icp_ack),
6069         .icp_wb__dat_r(libresocsim_libresoc_xics_icp_dat_r),
6070         .icp_wb__err(libresocsim_libresoc_xics_icp_err),
6071         .ics_wb__ack(libresocsim_libresoc_xics_ics_ack),
6072         .ics_wb__dat_r(libresocsim_libresoc_xics_ics_dat_r),
6073         .ics_wb__err(libresocsim_libresoc_xics_ics_err),
6074         .jtag_wb__adr(libresocsim_libresoc_jtag_wb_adr),
6075         .jtag_wb__cyc(libresocsim_libresoc_jtag_wb_cyc),
6076         .jtag_wb__dat_w(libresocsim_libresoc_jtag_wb_dat_w),
6077         .jtag_wb__sel(libresocsim_libresoc_jtag_wb_sel),
6078         .jtag_wb__stb(libresocsim_libresoc_jtag_wb_stb),
6079         .jtag_wb__we(libresocsim_libresoc_jtag_wb_we),
6080         .memerr_o(libresocsim_libresoc2),
6081         .mspi0_clk__pad__o(spimaster_clk),
6082         .mspi0_cs_n__pad__o(spimaster_cs_n),
6083         .mspi0_miso__core__i(libresocsim_libresoc_constraintmanager_spimaster_miso),
6084         .mspi0_mosi__pad__o(spimaster_mosi),
6085         .mtwi_scl__pad__o(i2c_scl),
6086         .mtwi_sda__core__i(libresocsim_libresoc_constraintmanager_i2c_sda_i),
6087         .mtwi_sda__pad__o(i2c_sda_o),
6088         .mtwi_sda__pad__oe(i2c_sda_oe),
6089         .pc_o(libresocsim_libresoc3),
6090         .pll_test_o(libresocsim_libresoc_pll_test_o),
6091         .pll_vco_o(libresocsim_libresoc_pll_vco_o),
6092         .pllclk_clk(sys_clk_0),
6093         .sdr_a_0__pad__o(sdram_a[0]),
6094         .sdr_a_10__pad__o(sdram_a[10]),
6095         .sdr_a_11__pad__o(sdram_a[11]),
6096         .sdr_a_12__pad__o(sdram_a[12]),
6097         .sdr_a_1__pad__o(sdram_a[1]),
6098         .sdr_a_2__pad__o(sdram_a[2]),
6099         .sdr_a_3__pad__o(sdram_a[3]),
6100         .sdr_a_4__pad__o(sdram_a[4]),
6101         .sdr_a_5__pad__o(sdram_a[5]),
6102         .sdr_a_6__pad__o(sdram_a[6]),
6103         .sdr_a_7__pad__o(sdram_a[7]),
6104         .sdr_a_8__pad__o(sdram_a[8]),
6105         .sdr_a_9__pad__o(sdram_a[9]),
6106         .sdr_ba_0__pad__o(sdram_ba[0]),
6107         .sdr_ba_1__pad__o(sdram_ba[1]),
6108         .sdr_cas_n__pad__o(sdram_cas_n),
6109         .sdr_cke__pad__o(sdram_cke),
6110         .sdr_clock__pad__o(sdram_clock),
6111         .sdr_cs_n__pad__o(sdram_cs_n),
6112         .sdr_dm_0__pad__o(sdram_dm[0]),
6113         .sdr_dm_1__pad__o(sdram_dm[1]),
6114         .sdr_dq_0__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[0]),
6115         .sdr_dq_0__pad__o(sdram_dq_o[0]),
6116         .sdr_dq_0__pad__oe(sdram_dq_oe[0]),
6117         .sdr_dq_10__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[10]),
6118         .sdr_dq_10__pad__o(sdram_dq_o[10]),
6119         .sdr_dq_10__pad__oe(sdram_dq_oe[10]),
6120         .sdr_dq_11__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[11]),
6121         .sdr_dq_11__pad__o(sdram_dq_o[11]),
6122         .sdr_dq_11__pad__oe(sdram_dq_oe[11]),
6123         .sdr_dq_12__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[12]),
6124         .sdr_dq_12__pad__o(sdram_dq_o[12]),
6125         .sdr_dq_12__pad__oe(sdram_dq_oe[12]),
6126         .sdr_dq_13__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[13]),
6127         .sdr_dq_13__pad__o(sdram_dq_o[13]),
6128         .sdr_dq_13__pad__oe(sdram_dq_oe[13]),
6129         .sdr_dq_14__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[14]),
6130         .sdr_dq_14__pad__o(sdram_dq_o[14]),
6131         .sdr_dq_14__pad__oe(sdram_dq_oe[14]),
6132         .sdr_dq_15__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[15]),
6133         .sdr_dq_15__pad__o(sdram_dq_o[15]),
6134         .sdr_dq_15__pad__oe(sdram_dq_oe[15]),
6135         .sdr_dq_1__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[1]),
6136         .sdr_dq_1__pad__o(sdram_dq_o[1]),
6137         .sdr_dq_1__pad__oe(sdram_dq_oe[1]),
6138         .sdr_dq_2__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[2]),
6139         .sdr_dq_2__pad__o(sdram_dq_o[2]),
6140         .sdr_dq_2__pad__oe(sdram_dq_oe[2]),
6141         .sdr_dq_3__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[3]),
6142         .sdr_dq_3__pad__o(sdram_dq_o[3]),
6143         .sdr_dq_3__pad__oe(sdram_dq_oe[3]),
6144         .sdr_dq_4__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[4]),
6145         .sdr_dq_4__pad__o(sdram_dq_o[4]),
6146         .sdr_dq_4__pad__oe(sdram_dq_oe[4]),
6147         .sdr_dq_5__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[5]),
6148         .sdr_dq_5__pad__o(sdram_dq_o[5]),
6149         .sdr_dq_5__pad__oe(sdram_dq_oe[5]),
6150         .sdr_dq_6__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[6]),
6151         .sdr_dq_6__pad__o(sdram_dq_o[6]),
6152         .sdr_dq_6__pad__oe(sdram_dq_oe[6]),
6153         .sdr_dq_7__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[7]),
6154         .sdr_dq_7__pad__o(sdram_dq_o[7]),
6155         .sdr_dq_7__pad__oe(sdram_dq_oe[7]),
6156         .sdr_dq_8__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[8]),
6157         .sdr_dq_8__pad__o(sdram_dq_o[8]),
6158         .sdr_dq_8__pad__oe(sdram_dq_oe[8]),
6159         .sdr_dq_9__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[9]),
6160         .sdr_dq_9__pad__o(sdram_dq_o[9]),
6161         .sdr_dq_9__pad__oe(sdram_dq_oe[9]),
6162         .sdr_ras_n__pad__o(sdram_ras_n),
6163         .sdr_we_n__pad__o(sdram_we_n),
6164         .sram4k_0_wb__ack(libresocsim_libresoc_interface0_ack),
6165         .sram4k_0_wb__dat_r(libresocsim_libresoc_interface0_dat_r),
6166         .sram4k_1_wb__ack(libresocsim_libresoc_interface1_ack),
6167         .sram4k_1_wb__dat_r(libresocsim_libresoc_interface1_dat_r),
6168         .sram4k_2_wb__ack(libresocsim_libresoc_interface2_ack),
6169         .sram4k_2_wb__dat_r(libresocsim_libresoc_interface2_dat_r),
6170         .sram4k_3_wb__ack(libresocsim_libresoc_interface3_ack),
6171         .sram4k_3_wb__dat_r(libresocsim_libresoc_interface3_dat_r)
6172 );
6173
6174 endmodule