experiments9/tsmc_c018/Makefile

   1
   2                 USE_DEBUG = No
   3              USE_VALGRIND = No
   4
   5         LOGICAL_SYNTHESIS = Yosys
   6        PHYSICAL_SYNTHESIS = Coriolis
   7                DESIGN_KIT = FlexLib018
   8             YOSYS_FLATTEN = No
   9          YOSYS_BLACKBOXES = pll \
  10                             spblock_512w64b8w
  11 #           YOSYS_SET_TOP = Yes
  12                     CHIP  = chip
  13                     CORE  = ls180
  14             USE_CLOCKTREE = Yes
  15                   RM_CHIP = Yes
  16                 VST_FLAGS = --vst-uniquify-uppercase
  17
  18                 #NETLISTS = $(shell cat cells.lst)
  19                  NETLISTS = ls180 libresoc
  20 #           YOSYS_FLATTEN = $(shell cat flatten.lst)
  21
  22  include ./mk/design-flow.mk
  23
  24
  25 chip_cts_r.vst: ls180.vst
  26         -$(call scl_cols,$(call c2env, $(VALGRIND_COMMAND) cgt -tV --script=doDesign))
  27
  28 chip_cts_r.gds: chip_cts_r.vst
  29         -@echo "[INFO] Overriden default GDS rule (for use with FlexLib)."
  30
  31 chip_r.ap: chip_r.vst
  32
  33 pinmux:
  34         (cd coriolis2 && python ../../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
  35         ln -f -s ../../../pinmux/src/parse.py coriolis2/pinparse.py
  36         ln -f -s coriolis2/ls180 ls180
  37
  38 blif:      ls180.blif
  39 vst:       ls180.vst
  40 gds:       chip_cts_r.gds