experiments9/tsmc_c018/build_full_4ksram_recon.sh

   1 #!/bin/sh
   2
   3 # full core build including QTY 4of 4k SRAMs: please remember to alter
   4 # doDesign.py before running!
   5 # change the settings to the larger chip/corona size
   6 #
   7 # also contains Staf's manually re-connected PLL edits to the verilog
   8 # see  commits 24cbbcc and 227a0f69
   9 #
  10 # Include tweaks dedicated to jpc's slightly different build environment.
  11
  12 echo "remember to check doDesign core size"
  13 echo "also use yosys 049e3abf9"
  14 if [ "${USER}" = "jpc" ]; then echo "Using \"jpc\" configuration."; fi
  15
  16 # fetch GDS-II files
  17 echo "fetching GDS-II files"
  18 wget http://ftp.libre-soc.org/C4MLogo.gds
  19 wget http://ftp.libre-soc.org/lip6.gds
  20 wget http://ftp.libre-soc.org/sorbonne_logo.gds
  21
  22 # initialise/update the pinmux submodule
  23 if [ "${USER}" = "jpc" ]; then
  24   # Must be done in the root of the repository when cloning anew.
  25   (cd ../..; git submodule update --init --remote)
  26 else
  27   git submodule update --init --remote
  28 fi
  29
  30 # makes symlinks to alliance
  31 if [ ! -e "./mk" ]; then
  32   if [ "${USER}" = "jpc" ]; then
  33     ln -s ../../../../alliance-check-toolkit/etc/mk .
  34   else
  35     ./mksyms.sh
  36   fi
  37 fi
  38
  39 # generates the io pads needed for ioring.py
  40 make pinmux
  41
  42 # clear out
  43 make clean
  44 rm -f *.vst *.ap
  45
  46 # copies over a "full" core
  47 #cp non_generated/full_core_4_4ksram_ls180.il ls180.il
  48 cp non_generated/full_core_4_4ksram_ls180.v ls180.v
  49 cp non_generated/full_core_4_4ksram_litex_ls180_recon.v litex_ls180.v
  50 cp non_generated/full_core_4_4ksram_libresoc_recon.v libresoc.v
  51 cp non_generated/spblock*.v .
  52 cp non_generated/spblock*.vbe .
  53 cp non_generated/pll.v .
  54 touch mem.init
  55 touch mem_1.init
  56 touch mem_2.init
  57 touch mem_3.init
  58 touch mem_4.init
  59 touch mem_5.init
  60
  61 if [ "${USER}" != "jpc" ]; then
  62   # make the vst from verilog
  63   make vst
  64
  65   # starts the build.
  66   make layout
  67 fi