fpga/top-arty.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library unisim;
   6 use unisim.vcomponents.all;
   7
   8 library work;
   9 use work.wishbone_types.all;
  10
  11 entity toplevel is
  12     generic (
  13         MEMORY_SIZE        : integer  := 16384;
  14         RAM_INIT_FILE      : string   := "firmware.hex";
  15         RESET_LOW          : boolean  := true;
  16         CLK_FREQUENCY      : positive := 100000000;
  17         HAS_FPU            : boolean  := true;
  18         HAS_BTC            : boolean  := true;
  19         USE_LITEDRAM       : boolean  := false;
  20         NO_BRAM            : boolean  := false;
  21         DISABLE_FLATTEN_CORE : boolean := false;
  22         SCLK_STARTUPE2     : boolean := false;
  23         SPI_FLASH_OFFSET   : integer := 4194304;
  24         SPI_FLASH_DEF_CKDV : natural := 1;
  25         SPI_FLASH_DEF_QUAD : boolean := true;
  26         LOG_LENGTH         : natural := 512;
  27         USE_LITEETH        : boolean  := false;
  28         UART_IS_16550      : boolean  := false;
  29         HAS_UART1          : boolean  := true
  30         );
  31     port(
  32         ext_clk   : in  std_ulogic;
  33         ext_rst_n : in  std_ulogic;
  34
  35         -- UART0 signals:
  36         uart_main_tx : out std_ulogic;
  37         uart_main_rx : in  std_ulogic;
  38
  39         -- UART1 signals:
  40         uart_pmod_tx    : out std_ulogic;
  41         uart_pmod_rx    : in std_ulogic;
  42         uart_pmod_cts_n : in std_ulogic;
  43         uart_pmod_rts_n : out std_ulogic;
  44
  45         -- LEDs
  46         led0_b  : out std_ulogic;
  47         led0_g  : out std_ulogic;
  48         led0_r  : out std_ulogic;
  49         led4    : out std_ulogic;
  50         led5    : out std_ulogic;
  51         led6    : out std_ulogic;
  52         led7    : out std_ulogic;
  53
  54         -- SPI
  55         spi_flash_cs_n   : out std_ulogic;
  56         spi_flash_clk    : out std_ulogic;
  57         spi_flash_mosi   : inout std_ulogic;
  58         spi_flash_miso   : inout std_ulogic;
  59         spi_flash_wp_n   : inout std_ulogic;
  60         spi_flash_hold_n : inout std_ulogic;
  61
  62         -- Ethernet
  63         eth_ref_clk      : out std_ulogic;
  64         eth_clocks_tx    : in std_ulogic;
  65         eth_clocks_rx    : in std_ulogic;
  66         eth_rst_n        : out std_ulogic;
  67         eth_mdio         : inout std_ulogic;
  68         eth_mdc          : out std_ulogic;
  69         eth_rx_dv        : in std_ulogic;
  70         eth_rx_er        : in std_ulogic;
  71         eth_rx_data      : in std_ulogic_vector(3 downto 0);
  72         eth_tx_en        : out std_ulogic;
  73         eth_tx_data      : out std_ulogic_vector(3 downto 0);
  74         eth_col          : in std_ulogic;
  75         eth_crs          : in std_ulogic;
  76
  77         -- DRAM wires
  78         ddram_a       : out std_ulogic_vector(13 downto 0);
  79         ddram_ba      : out std_ulogic_vector(2 downto 0);
  80         ddram_ras_n   : out std_ulogic;
  81         ddram_cas_n   : out std_ulogic;
  82         ddram_we_n    : out std_ulogic;
  83         ddram_cs_n    : out std_ulogic;
  84         ddram_dm      : out std_ulogic_vector(1 downto 0);
  85         ddram_dq      : inout std_ulogic_vector(15 downto 0);
  86         ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
  87         ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
  88         ddram_clk_p   : out std_ulogic;
  89         ddram_clk_n   : out std_ulogic;
  90         ddram_cke     : out std_ulogic;
  91         ddram_odt     : out std_ulogic;
  92         ddram_reset_n : out std_ulogic
  93         );
  94 end entity toplevel;
  95
  96 architecture behaviour of toplevel is
  97
  98     -- Reset signals:
  99     signal soc_rst : std_ulogic;
 100     signal pll_rst : std_ulogic;
 101
 102     -- Internal clock signals:
 103     signal system_clk        : std_ulogic;
 104     signal system_clk_locked : std_ulogic;
 105     signal eth_clk_locked    : std_ulogic;
 106
 107     -- External IOs from the SoC
 108     signal wb_ext_io_in        : wb_io_master_out;
 109     signal wb_ext_io_out       : wb_io_slave_out;
 110     signal wb_ext_is_dram_csr  : std_ulogic;
 111     signal wb_ext_is_dram_init : std_ulogic;
 112     signal wb_ext_is_eth       : std_ulogic;
 113
 114     -- DRAM main data wishbone connection
 115     signal wb_dram_in          : wishbone_master_out;
 116     signal wb_dram_out         : wishbone_slave_out;
 117
 118     -- DRAM control wishbone connection
 119     signal wb_dram_ctrl_out    : wb_io_slave_out := wb_io_slave_out_init;
 120
 121     -- LiteEth connection
 122     signal ext_irq_eth         : std_ulogic;
 123     signal wb_eth_out          : wb_io_slave_out := wb_io_slave_out_init;
 124
 125     -- Control/status
 126     signal core_alt_reset : std_ulogic;
 127
 128     -- Status LED
 129     signal led0_b_pwm : std_ulogic;
 130     signal led0_r_pwm : std_ulogic;
 131     signal led0_g_pwm : std_ulogic;
 132
 133     -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
 134     signal pwm_counter  : std_ulogic_vector(8 downto 0);
 135
 136     -- SPI flash
 137     signal spi_sck     : std_ulogic;
 138     signal spi_cs_n    : std_ulogic;
 139     signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
 140     signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
 141     signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
 142
 143     -- Fixup various memory sizes based on generics
 144     function get_bram_size return natural is
 145     begin
 146         if USE_LITEDRAM and NO_BRAM then
 147             return 0;
 148         else
 149             return MEMORY_SIZE;
 150         end if;
 151     end function;
 152
 153     function get_payload_size return natural is
 154     begin
 155         if USE_LITEDRAM and NO_BRAM then
 156             return MEMORY_SIZE;
 157         else
 158             return 0;
 159         end if;
 160     end function;
 161
 162     constant BRAM_SIZE    : natural := get_bram_size;
 163     constant PAYLOAD_SIZE : natural := get_payload_size;
 164 begin
 165
 166     -- Main SoC
 167     soc0: entity work.soc
 168         generic map(
 169             MEMORY_SIZE        => BRAM_SIZE,
 170             RAM_INIT_FILE      => RAM_INIT_FILE,
 171             SIM                => false,
 172             CLK_FREQ           => CLK_FREQUENCY,
 173             HAS_FPU            => HAS_FPU,
 174             HAS_BTC            => HAS_BTC,
 175             HAS_DRAM           => USE_LITEDRAM,
 176             DRAM_SIZE          => 256 * 1024 * 1024,
 177             DRAM_INIT_SIZE     => PAYLOAD_SIZE,
 178             DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
 179             HAS_SPI_FLASH      => true,
 180             SPI_FLASH_DLINES   => 4,
 181             SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
 182             SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
 183             SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
 184             LOG_LENGTH         => LOG_LENGTH,
 185             HAS_LITEETH        => USE_LITEETH,
 186             UART0_IS_16550     => UART_IS_16550,
 187             HAS_UART1          => HAS_UART1
 188             )
 189         port map (
 190             -- System signals
 191             system_clk        => system_clk,
 192             rst               => soc_rst,
 193
 194             -- UART signals
 195             uart0_txd         => uart_main_tx,
 196             uart0_rxd         => uart_main_rx,
 197
 198             -- UART1 signals
 199             uart1_txd         => uart_pmod_tx,
 200             uart1_rxd         => uart_pmod_rx,
 201
 202             -- SPI signals
 203             spi_flash_sck     => spi_sck,
 204             spi_flash_cs_n    => spi_cs_n,
 205             spi_flash_sdat_o  => spi_sdat_o,
 206             spi_flash_sdat_oe => spi_sdat_oe,
 207             spi_flash_sdat_i  => spi_sdat_i,
 208
 209             -- External interrupts
 210             ext_irq_eth       => ext_irq_eth,
 211
 212             -- DRAM wishbone
 213             wb_dram_in           => wb_dram_in,
 214             wb_dram_out          => wb_dram_out,
 215             wb_ext_io_in         => wb_ext_io_in,
 216             wb_ext_io_out        => wb_ext_io_out,
 217             wb_ext_is_dram_csr   => wb_ext_is_dram_csr,
 218             wb_ext_is_dram_init  => wb_ext_is_dram_init,
 219             wb_ext_is_eth        => wb_ext_is_eth,
 220             alt_reset            => core_alt_reset
 221             );
 222
 223     uart_pmod_rts_n <= '0';
 224
 225     -- SPI Flash
 226     --
 227     -- Note: Unlike many other boards, the SPI flash on the Arty has
 228     -- an actual pin to generate the clock and doesn't require to use
 229     -- the STARTUPE2 primitive.
 230     --
 231     spi_flash_cs_n   <= spi_cs_n;
 232     spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
 233     spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
 234     spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
 235     spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
 236     spi_sdat_i(0)    <= spi_flash_mosi;
 237     spi_sdat_i(1)    <= spi_flash_miso;
 238     spi_sdat_i(2)    <= spi_flash_wp_n;
 239     spi_sdat_i(3)    <= spi_flash_hold_n;
 240
 241     spi_sclk_startupe2: if SCLK_STARTUPE2 generate
 242         spi_flash_clk    <= 'Z';
 243
 244         STARTUPE2_INST: STARTUPE2
 245             port map (
 246                 CLK => '0',
 247                 GSR => '0',
 248                 GTS => '0',
 249                 KEYCLEARB => '0',
 250                 PACK => '0',
 251                 USRCCLKO => spi_sck,
 252                 USRCCLKTS => '0',
 253                 USRDONEO => '1',
 254                 USRDONETS => '0'
 255                 );
 256     end generate;
 257
 258     spi_direct_sclk: if not SCLK_STARTUPE2 generate
 259         spi_flash_clk    <= spi_sck;
 260     end generate;
 261
 262     nodram: if not USE_LITEDRAM generate
 263         signal ddram_clk_dummy : std_ulogic;
 264     begin
 265         reset_controller: entity work.soc_reset
 266             generic map(
 267                 RESET_LOW => RESET_LOW
 268                 )
 269             port map(
 270                 ext_clk => ext_clk,
 271                 pll_clk => system_clk,
 272                 pll_locked_in => system_clk_locked and eth_clk_locked,
 273                 ext_rst_in => ext_rst_n,
 274                 pll_rst_out => pll_rst,
 275                 rst_out => soc_rst
 276                 );
 277
 278         clkgen: entity work.clock_generator
 279             generic map(
 280                 CLK_INPUT_HZ => 100000000,
 281                 CLK_OUTPUT_HZ => CLK_FREQUENCY
 282                 )
 283             port map(
 284                 ext_clk => ext_clk,
 285                 pll_rst_in => pll_rst,
 286                 pll_clk_out => system_clk,
 287                 pll_locked_out => system_clk_locked
 288                 );
 289
 290         led0_b_pwm <= '1';
 291         led0_r_pwm <= '1';
 292         led0_g_pwm <= '0';
 293         core_alt_reset <= '0';
 294
 295         -- Vivado barfs on those differential signals if left
 296         -- unconnected. So instanciate a diff. buffer and feed
 297         -- it a constant '0'.
 298         dummy_dram_clk: OBUFDS
 299             port map (
 300                 O => ddram_clk_p,
 301                 OB => ddram_clk_n,
 302                 I => ddram_clk_dummy
 303                 );
 304         ddram_clk_dummy <= '0';
 305
 306     end generate;
 307
 308     has_dram: if USE_LITEDRAM generate
 309         signal dram_init_done  : std_ulogic;
 310         signal dram_init_error : std_ulogic;
 311         signal dram_sys_rst    : std_ulogic;
 312         signal rst_gen_rst     : std_ulogic;
 313     begin
 314
 315         -- Eventually dig out the frequency from the generator
 316         -- but for now, assert it's 100Mhz
 317         assert CLK_FREQUENCY = 100000000;
 318
 319         reset_controller: entity work.soc_reset
 320             generic map(
 321                 RESET_LOW => RESET_LOW,
 322                 PLL_RESET_BITS => 18,
 323                 SOC_RESET_BITS => 1
 324                 )
 325             port map(
 326                 ext_clk => ext_clk,
 327                 pll_clk => system_clk,
 328                 pll_locked_in => eth_clk_locked,
 329                 ext_rst_in => ext_rst_n,
 330                 pll_rst_out => pll_rst,
 331                 rst_out => rst_gen_rst
 332                 );
 333
 334         -- Generate SoC reset
 335         soc_rst_gen: process(system_clk)
 336         begin
 337             if ext_rst_n = '0' then
 338                 soc_rst <= '1';
 339             elsif rising_edge(system_clk) then
 340                 soc_rst <= dram_sys_rst or not eth_clk_locked or not system_clk_locked;
 341             end if;
 342         end process;
 343
 344         dram: entity work.litedram_wrapper
 345             generic map(
 346                 DRAM_ABITS => 24,
 347                 DRAM_ALINES => 14,
 348                 DRAM_DLINES => 16,
 349                 DRAM_PORT_WIDTH => 128,
 350                 PAYLOAD_FILE => RAM_INIT_FILE,
 351                 PAYLOAD_SIZE => PAYLOAD_SIZE
 352                 )
 353             port map(
 354                 clk_in          => ext_clk,
 355                 rst             => pll_rst,
 356                 system_clk      => system_clk,
 357                 system_reset    => dram_sys_rst,
 358                 core_alt_reset  => core_alt_reset,
 359                 pll_locked      => system_clk_locked,
 360
 361                 wb_in           => wb_dram_in,
 362                 wb_out          => wb_dram_out,
 363                 wb_ctrl_in      => wb_ext_io_in,
 364                 wb_ctrl_out     => wb_dram_ctrl_out,
 365                 wb_ctrl_is_csr  => wb_ext_is_dram_csr,
 366                 wb_ctrl_is_init => wb_ext_is_dram_init,
 367
 368                 init_done       => dram_init_done,
 369                 init_error      => dram_init_error,
 370
 371                 ddram_a         => ddram_a,
 372                 ddram_ba        => ddram_ba,
 373                 ddram_ras_n     => ddram_ras_n,
 374                 ddram_cas_n     => ddram_cas_n,
 375                 ddram_we_n      => ddram_we_n,
 376                 ddram_cs_n      => ddram_cs_n,
 377                 ddram_dm        => ddram_dm,
 378                 ddram_dq        => ddram_dq,
 379                 ddram_dqs_p     => ddram_dqs_p,
 380                 ddram_dqs_n     => ddram_dqs_n,
 381                 ddram_clk_p     => ddram_clk_p,
 382                 ddram_clk_n     => ddram_clk_n,
 383                 ddram_cke       => ddram_cke,
 384                 ddram_odt       => ddram_odt,
 385                 ddram_reset_n   => ddram_reset_n
 386                 );
 387
 388         led0_b_pwm <= not dram_init_done;
 389         led0_r_pwm <= dram_init_error;
 390         led0_g_pwm <= dram_init_done and not dram_init_error;
 391
 392     end generate;
 393
 394     has_liteeth : if USE_LITEETH generate
 395
 396         component liteeth_core port (
 397             sys_clock           : in std_ulogic;
 398             sys_reset           : in std_ulogic;
 399             mii_eth_clocks_tx   : in std_ulogic;
 400             mii_eth_clocks_rx   : in std_ulogic;
 401             mii_eth_rst_n       : out std_ulogic;
 402             mii_eth_mdio        : in std_ulogic;
 403             mii_eth_mdc         : out std_ulogic;
 404             mii_eth_rx_dv       : in std_ulogic;
 405             mii_eth_rx_er       : in std_ulogic;
 406             mii_eth_rx_data     : in std_ulogic_vector(3 downto 0);
 407             mii_eth_tx_en       : out std_ulogic;
 408             mii_eth_tx_data     : out std_ulogic_vector(3 downto 0);
 409             mii_eth_col         : in std_ulogic;
 410             mii_eth_crs         : in std_ulogic;
 411             wishbone_adr        : in std_ulogic_vector(29 downto 0);
 412             wishbone_dat_w      : in std_ulogic_vector(31 downto 0);
 413             wishbone_dat_r      : out std_ulogic_vector(31 downto 0);
 414             wishbone_sel        : in std_ulogic_vector(3 downto 0);
 415             wishbone_cyc        : in std_ulogic;
 416             wishbone_stb        : in std_ulogic;
 417             wishbone_ack        : out std_ulogic;
 418             wishbone_we         : in std_ulogic;
 419             wishbone_cti        : in std_ulogic_vector(2 downto 0);
 420             wishbone_bte        : in std_ulogic_vector(1 downto 0);
 421             wishbone_err        : out std_ulogic;
 422             interrupt           : out std_ulogic
 423             );
 424         end component;
 425
 426         signal wb_eth_cyc     : std_ulogic;
 427         signal wb_eth_adr     : std_ulogic_vector(29 downto 0);
 428
 429         -- Change this to use a PLL instead of a BUFR to generate the 25Mhz
 430         -- reference clock to the PHY.
 431         constant USE_PLL : boolean := false;
 432     begin
 433         eth_use_pll: if USE_PLL generate
 434             signal eth_clk_25     : std_ulogic;
 435             signal eth_clkfb      : std_ulogic;
 436         begin
 437             pll_eth : PLLE2_BASE
 438                 generic map (
 439                     BANDWIDTH          => "OPTIMIZED",
 440                     CLKFBOUT_MULT      => 16,
 441                     CLKIN1_PERIOD      => 10.0,
 442                     CLKOUT0_DIVIDE     => 64,
 443                     DIVCLK_DIVIDE      => 1,
 444                     STARTUP_WAIT       => "FALSE")
 445                 port map (
 446                     CLKOUT0  => eth_clk_25,
 447                     CLKOUT1  => open,
 448                     CLKOUT2  => open,
 449                     CLKOUT3  => open,
 450                     CLKOUT4  => open,
 451                     CLKOUT5  => open,
 452                     CLKFBOUT => eth_clkfb,
 453                     LOCKED   => eth_clk_locked,
 454                     CLKIN1   => ext_clk,
 455                     PWRDWN   => '0',
 456                     RST      => pll_rst,
 457                     CLKFBIN  => eth_clkfb);
 458
 459             eth_clk_buf: BUFG
 460                 port map (
 461                     I => eth_clk_25,
 462                     O => eth_ref_clk
 463                     );
 464         end generate;
 465
 466         eth_use_bufr: if not USE_PLL generate
 467             eth_clk_div: BUFR
 468                 generic map (
 469                     BUFR_DIVIDE => "4"
 470                     )
 471                 port map (
 472                     I => system_clk,
 473                     O => eth_ref_clk,
 474                     CE => '1',
 475                     CLR => '0'
 476                     );
 477             eth_clk_locked <= '1';
 478         end generate;
 479
 480         liteeth :  liteeth_core
 481             port map(
 482                 sys_clock         => system_clk,
 483                 sys_reset         => soc_rst,
 484                 mii_eth_clocks_tx => eth_clocks_tx,
 485                 mii_eth_clocks_rx => eth_clocks_rx,
 486                 mii_eth_rst_n     => eth_rst_n,
 487                 mii_eth_mdio      => eth_mdio,
 488                 mii_eth_mdc       => eth_mdc,
 489                 mii_eth_rx_dv     => eth_rx_dv,
 490                 mii_eth_rx_er     => eth_rx_er,
 491                 mii_eth_rx_data   => eth_rx_data,
 492                 mii_eth_tx_en     => eth_tx_en,
 493                 mii_eth_tx_data   => eth_tx_data,
 494                 mii_eth_col       => eth_col,
 495                 mii_eth_crs       => eth_crs,
 496                 wishbone_adr      => wb_eth_adr,
 497                 wishbone_dat_w    => wb_ext_io_in.dat,
 498                 wishbone_dat_r    => wb_eth_out.dat,
 499                 wishbone_sel      => wb_ext_io_in.sel,
 500                 wishbone_cyc      => wb_eth_cyc,
 501                 wishbone_stb      => wb_ext_io_in.stb,
 502                 wishbone_ack      => wb_eth_out.ack,
 503                 wishbone_we       => wb_ext_io_in.we,
 504                 wishbone_cti      => "000",
 505                 wishbone_bte      => "00",
 506                 wishbone_err      => open,
 507                 interrupt         => ext_irq_eth
 508                 );
 509
 510         -- Gate cyc with "chip select" from soc
 511         wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
 512
 513         -- Remove top address bits as liteeth decoder doesn't know about them
 514         wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(16 downto 2);
 515
 516         -- LiteETH isn't pipelined
 517         wb_eth_out.stall <= not wb_eth_out.ack;
 518
 519     end generate;
 520
 521     no_liteeth : if not USE_LITEETH generate
 522         eth_clk_locked <= '1';
 523         ext_irq_eth    <= '0';
 524     end generate;
 525
 526     -- Mux WB response on the IO bus
 527     wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else wb_dram_ctrl_out;
 528
 529     leds_pwm : process(system_clk)
 530     begin
 531         if rising_edge(system_clk) then
 532             pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
 533             if pwm_counter(8 downto 4) = "00000" then
 534                 led0_b <= led0_b_pwm;
 535                 led0_r <= led0_r_pwm;
 536                 led0_g <= led0_g_pwm;
 537             else
 538                 led0_b <= '0';
 539                 led0_r <= '0';
 540                 led0_g <= '0';
 541             end if;
 542         end if;
 543     end process;
 544
 545     led4 <= system_clk_locked;
 546     led5 <= eth_clk_locked;
 547     led6 <= not soc_rst;
 548     led7 <= not spi_flash_cs_n;
 549
 550 end architecture behaviour;