fpga/top-nexys-video.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library unisim;
   6 use unisim.vcomponents.all;
   7
   8 library work;
   9 use work.wishbone_types.all;
  10
  11 entity toplevel is
  12     generic (
  13         MEMORY_SIZE   : integer := 16384;
  14         RAM_INIT_FILE : string   := "firmware.hex";
  15         RESET_LOW     : boolean  := true;
  16         CLK_FREQUENCY : positive := 100000000;
  17         HAS_FPU       : boolean  := true;
  18         HAS_BTC       : boolean  := true;
  19         USE_LITEDRAM  : boolean  := false;
  20         NO_BRAM       : boolean  := false;
  21         DISABLE_FLATTEN_CORE : boolean := false;
  22         SPI_FLASH_OFFSET   : integer := 10485760;
  23         SPI_FLASH_DEF_CKDV : natural := 1;
  24         SPI_FLASH_DEF_QUAD : boolean := true;
  25         LOG_LENGTH         : natural := 2048;
  26         UART_IS_16550      : boolean := true
  27         );
  28     port(
  29         ext_clk   : in  std_ulogic;
  30         ext_rst   : in  std_ulogic;
  31
  32         -- UART0 signals:
  33         uart_main_tx : out std_ulogic;
  34         uart_main_rx : in  std_ulogic;
  35
  36         -- LEDs
  37         led0    : out std_logic;
  38         led1    : out std_logic;
  39
  40         -- SPI
  41         spi_flash_cs_n   : out std_ulogic;
  42         spi_flash_mosi   : inout std_ulogic;
  43         spi_flash_miso   : inout std_ulogic;
  44         spi_flash_wp_n   : inout std_ulogic;
  45         spi_flash_hold_n : inout std_ulogic;
  46
  47         -- DRAM wires
  48         ddram_a       : out std_logic_vector(14 downto 0);
  49         ddram_ba      : out std_logic_vector(2 downto 0);
  50         ddram_ras_n   : out std_logic;
  51         ddram_cas_n   : out std_logic;
  52         ddram_we_n    : out std_logic;
  53         ddram_dm      : out std_logic_vector(1 downto 0);
  54         ddram_dq      : inout std_logic_vector(15 downto 0);
  55         ddram_dqs_p   : inout std_logic_vector(1 downto 0);
  56         ddram_dqs_n   : inout std_logic_vector(1 downto 0);
  57         ddram_clk_p   : out std_logic;
  58         ddram_clk_n   : out std_logic;
  59         ddram_cke     : out std_logic;
  60         ddram_odt     : out std_logic;
  61         ddram_reset_n : out std_logic
  62         );
  63 end entity toplevel;
  64
  65 architecture behaviour of toplevel is
  66
  67     -- Reset signals:
  68     signal soc_rst : std_ulogic;
  69     signal pll_rst : std_ulogic;
  70
  71     -- Internal clock signals:
  72     signal system_clk : std_ulogic;
  73     signal system_clk_locked : std_ulogic;
  74
  75     -- DRAM main data wishbone connection
  76     signal wb_dram_in       : wishbone_master_out;
  77     signal wb_dram_out      : wishbone_slave_out;
  78
  79     -- DRAM control wishbone connection
  80     signal wb_ext_io_in        : wb_io_master_out;
  81     signal wb_ext_io_out       : wb_io_slave_out;
  82     signal wb_ext_is_dram_csr  : std_ulogic;
  83     signal wb_ext_is_dram_init : std_ulogic;
  84
  85     -- Control/status
  86     signal core_alt_reset : std_ulogic;
  87
  88     -- SPI flash
  89     signal spi_sck     : std_ulogic;
  90     signal spi_cs_n    : std_ulogic;
  91     signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
  92     signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
  93     signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
  94
  95     -- Fixup various memory sizes based on generics
  96     function get_bram_size return natural is
  97     begin
  98         if USE_LITEDRAM and NO_BRAM then
  99             return 0;
 100         else
 101             return MEMORY_SIZE;
 102         end if;
 103     end function;
 104
 105     function get_payload_size return natural is
 106     begin
 107         if USE_LITEDRAM and NO_BRAM then
 108             return MEMORY_SIZE;
 109         else
 110             return 0;
 111         end if;
 112     end function;
 113
 114     constant BRAM_SIZE    : natural := get_bram_size;
 115     constant PAYLOAD_SIZE : natural := get_payload_size;
 116 begin
 117
 118     -- Main SoC
 119     soc0: entity work.soc
 120         generic map(
 121             MEMORY_SIZE   => BRAM_SIZE,
 122             RAM_INIT_FILE => RAM_INIT_FILE,
 123             SIM           => false,
 124             CLK_FREQ      => CLK_FREQUENCY,
 125             HAS_FPU       => HAS_FPU,
 126             HAS_BTC       => HAS_BTC,
 127             HAS_DRAM      => USE_LITEDRAM,
 128             DRAM_SIZE     => 512 * 1024 * 1024,
 129             DRAM_INIT_SIZE => PAYLOAD_SIZE,
 130             DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
 131             HAS_SPI_FLASH      => true,
 132             SPI_FLASH_DLINES   => 4,
 133             SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
 134             SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
 135             SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
 136             LOG_LENGTH         => LOG_LENGTH,
 137             UART0_IS_16550     => UART_IS_16550
 138             )
 139         port map (
 140             -- System signals
 141             system_clk        => system_clk,
 142             rst               => soc_rst,
 143
 144             -- UART signals
 145             uart0_txd         => uart_main_tx,
 146             uart0_rxd         => uart_main_rx,
 147
 148             -- SPI signals
 149             spi_flash_sck     => spi_sck,
 150             spi_flash_cs_n    => spi_cs_n,
 151             spi_flash_sdat_o  => spi_sdat_o,
 152             spi_flash_sdat_oe => spi_sdat_oe,
 153             spi_flash_sdat_i  => spi_sdat_i,
 154
 155             -- DRAM wishbone
 156             wb_dram_in          => wb_dram_in,
 157             wb_dram_out         => wb_dram_out,
 158             wb_ext_io_in        => wb_ext_io_in,
 159             wb_ext_io_out       => wb_ext_io_out,
 160             wb_ext_is_dram_csr  => wb_ext_is_dram_csr,
 161             wb_ext_is_dram_init => wb_ext_is_dram_init,
 162             alt_reset           => core_alt_reset
 163             );
 164
 165     -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2
 166     -- primitive of the FPGA as it's not a normal pin
 167     --
 168     spi_flash_cs_n   <= spi_cs_n;
 169     spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
 170     spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
 171     spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
 172     spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
 173     spi_sdat_i(0)    <= spi_flash_mosi;
 174     spi_sdat_i(1)    <= spi_flash_miso;
 175     spi_sdat_i(2)    <= spi_flash_wp_n;
 176     spi_sdat_i(3)    <= spi_flash_hold_n;
 177
 178     STARTUPE2_INST: STARTUPE2
 179         port map (
 180             CLK => '0',
 181             GSR => '0',
 182             GTS => '0',
 183             KEYCLEARB => '0',
 184             PACK => '0',
 185             USRCCLKO => spi_sck,
 186             USRCCLKTS => '0',
 187             USRDONEO => '1',
 188             USRDONETS => '0'
 189             );
 190
 191     nodram: if not USE_LITEDRAM generate
 192         signal ddram_clk_dummy : std_ulogic;
 193     begin
 194         reset_controller: entity work.soc_reset
 195             generic map(
 196                 RESET_LOW => RESET_LOW
 197                 )
 198             port map(
 199                 ext_clk => ext_clk,
 200                 pll_clk => system_clk,
 201                 pll_locked_in => system_clk_locked,
 202                 ext_rst_in => ext_rst,
 203                 pll_rst_out => pll_rst,
 204                 rst_out => soc_rst
 205                 );
 206
 207         clkgen: entity work.clock_generator
 208             generic map(
 209                 CLK_INPUT_HZ => 100000000,
 210                 CLK_OUTPUT_HZ => CLK_FREQUENCY
 211                 )
 212             port map(
 213                 ext_clk => ext_clk,
 214                 pll_rst_in => pll_rst,
 215                 pll_clk_out => system_clk,
 216                 pll_locked_out => system_clk_locked
 217                 );
 218
 219         led0 <= '1';
 220         led1 <= not soc_rst;
 221         core_alt_reset <= '0';
 222
 223         -- Vivado barfs on those differential signals if left
 224         -- unconnected. So instanciate a diff. buffer and feed
 225         -- it a constant '0'.
 226         dummy_dram_clk: OBUFDS
 227             port map (
 228                 O => ddram_clk_p,
 229                 OB => ddram_clk_n,
 230                 I => ddram_clk_dummy
 231                 );
 232         ddram_clk_dummy <= '0';
 233
 234     end generate;
 235
 236     has_dram: if USE_LITEDRAM generate
 237         signal dram_init_done  : std_ulogic;
 238         signal dram_init_error : std_ulogic;
 239         signal dram_sys_rst    : std_ulogic;
 240     begin
 241
 242         -- Eventually dig out the frequency from the generator
 243         -- but for now, assert it's 100Mhz
 244         assert CLK_FREQUENCY = 100000000;
 245
 246         reset_controller: entity work.soc_reset
 247             generic map(
 248                 RESET_LOW => RESET_LOW,
 249                 PLL_RESET_BITS => 18,
 250                 SOC_RESET_BITS => 1
 251                 )
 252             port map(
 253                 ext_clk => ext_clk,
 254                 pll_clk => system_clk,
 255                 pll_locked_in => '1',
 256                 ext_rst_in => ext_rst,
 257                 pll_rst_out => pll_rst,
 258                 rst_out => open
 259                 );
 260
 261         dram: entity work.litedram_wrapper
 262             generic map(
 263                 DRAM_ABITS => 25,
 264                 DRAM_ALINES => 15,
 265                 DRAM_DLINES => 16,
 266                 DRAM_PORT_WIDTH => 128,
 267                 PAYLOAD_FILE => RAM_INIT_FILE,
 268                 PAYLOAD_SIZE => PAYLOAD_SIZE
 269                 )
 270             port map(
 271                 clk_in          => ext_clk,
 272                 rst             => pll_rst,
 273                 system_clk      => system_clk,
 274                 system_reset    => soc_rst,
 275                 core_alt_reset  => core_alt_reset,
 276                 pll_locked      => system_clk_locked,
 277
 278                 wb_in           => wb_dram_in,
 279                 wb_out          => wb_dram_out,
 280                 wb_ctrl_in      => wb_ext_io_in,
 281                 wb_ctrl_out     => wb_ext_io_out,
 282                 wb_ctrl_is_csr  => wb_ext_is_dram_csr,
 283                 wb_ctrl_is_init => wb_ext_is_dram_init,
 284
 285                 init_done       => dram_init_done,
 286                 init_error      => dram_init_error,
 287
 288                 ddram_a         => ddram_a,
 289                 ddram_ba        => ddram_ba,
 290                 ddram_ras_n     => ddram_ras_n,
 291                 ddram_cas_n     => ddram_cas_n,
 292                 ddram_we_n      => ddram_we_n,
 293                 ddram_cs_n      => open,
 294                 ddram_dm        => ddram_dm,
 295                 ddram_dq        => ddram_dq,
 296                 ddram_dqs_p     => ddram_dqs_p,
 297                 ddram_dqs_n     => ddram_dqs_n,
 298                 ddram_clk_p     => ddram_clk_p,
 299                 ddram_clk_n     => ddram_clk_n,
 300                 ddram_cke       => ddram_cke,
 301                 ddram_odt       => ddram_odt,
 302                 ddram_reset_n   => ddram_reset_n
 303                 );
 304
 305         led0 <= dram_init_done and not dram_init_error;
 306         led1 <= dram_init_error; -- Make it blink ?
 307
 308     end generate;
 309 end architecture behaviour;