1 // See LICENSE for license details.
5 module sdio_spi_bridge (
10 inout wire [3:0] sd_dat,
14 input wire [3:0] spi_dq_o,
15 output wire [3:0] spi_dq_i,
22 assign mosi = spi_dq_o[0];
23 assign spi_dq_i = {2'b00, miso_sync[1], 1'b0};
25 assign sd_sck = spi_sck;
48 always @(posedge clk) begin
54 miso_sync[1] <= miso_sync[0];