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verific: allow memories to be inferred in loops
[yosys.git] / frontends / verific / verific.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/log.h"
24 #include "libs/sha1/sha1.h"
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #ifndef _WIN32
30 # include <unistd.h>
31 # include <dirent.h>
32 #endif
33
34 #include "frontends/verific/verific.h"
35
36 USING_YOSYS_NAMESPACE
37
38 #ifdef YOSYS_ENABLE_VERIFIC
39
40 #ifdef __clang__
41 #pragma clang diagnostic push
42 #pragma clang diagnostic ignored "-Woverloaded-virtual"
43 #endif
44
45 #include "veri_file.h"
46 #include "hier_tree.h"
47 #include "VeriModule.h"
48 #include "VeriWrite.h"
49 #include "VeriLibrary.h"
50
51 #ifdef VERIFIC_VHDL_SUPPORT
52 #include "vhdl_file.h"
53 #include "VhdlUnits.h"
54 #endif
55
56 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
57 #include "InitialAssertions.h"
58 #endif
59
60 #ifndef YOSYSHQ_VERIFIC_API_VERSION
61 # error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
62 #endif
63
64 #if YOSYSHQ_VERIFIC_API_VERSION < 20210801
65 # error "Please update your version of YosysHQ flavored Verific."
66 #endif
67
68 #ifdef __clang__
69 #pragma clang diagnostic pop
70 #endif
71
72 #ifdef VERIFIC_NAMESPACE
73 using namespace Verific;
74 #endif
75
76 #endif
77
78 #ifdef YOSYS_ENABLE_VERIFIC
79 YOSYS_NAMESPACE_BEGIN
80
81 int verific_verbose;
82 bool verific_import_pending;
83 string verific_error_msg;
84 int verific_sva_fsm_limit;
85
86 vector<string> verific_incdirs, verific_libdirs;
87
88 void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
89 {
90 string message_prefix = stringf("VERIFIC-%s [%s] ",
91 msg_type == VERIFIC_NONE ? "NONE" :
92 msg_type == VERIFIC_ERROR ? "ERROR" :
93 msg_type == VERIFIC_WARNING ? "WARNING" :
94 msg_type == VERIFIC_IGNORE ? "IGNORE" :
95 msg_type == VERIFIC_INFO ? "INFO" :
96 msg_type == VERIFIC_COMMENT ? "COMMENT" :
97 msg_type == VERIFIC_PROGRAM_ERROR ? "PROGRAM_ERROR" : "UNKNOWN", message_id);
98
99 string message = linefile ? stringf("%s:%d: ", LineFile::GetFileName(linefile), LineFile::GetLineNo(linefile)) : "";
100 message += vstringf(msg, args);
101
102 if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR)
103 log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str());
104 else
105 log("%s%s\n", message_prefix.c_str(), message.c_str());
106
107 if (verific_error_msg.empty() && (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_PROGRAM_ERROR))
108 verific_error_msg = message;
109 }
110
111 string get_full_netlist_name(Netlist *nl)
112 {
113 if (nl->NumOfRefs() == 1) {
114 Instance *inst = (Instance*)nl->GetReferences()->GetLast();
115 return get_full_netlist_name(inst->Owner()) + "." + inst->Name();
116 }
117
118 return nl->CellBaseName();
119 }
120
121 // ==================================================================
122
123 VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit) :
124 mode_gates(mode_gates), mode_keep(mode_keep), mode_nosva(mode_nosva),
125 mode_names(mode_names), mode_verific(mode_verific), mode_autocover(mode_autocover),
126 mode_fullinit(mode_fullinit)
127 {
128 }
129
130 RTLIL::SigBit VerificImporter::net_map_at(Net *net)
131 {
132 if (net->IsExternalTo(netlist))
133 log_error("Found external reference to '%s.%s' in netlist '%s', please use -flatten or -extnets.\n",
134 get_full_netlist_name(net->Owner()).c_str(), net->Name(), get_full_netlist_name(netlist).c_str());
135
136 return net_map.at(net);
137 }
138
139 bool is_blackbox(Netlist *nl)
140 {
141 if (nl->IsBlackBox() || nl->IsEmptyBox())
142 return true;
143
144 const char *attr = nl->GetAttValue("blackbox");
145 if (attr != nullptr && strcmp(attr, "0"))
146 return true;
147
148 return false;
149 }
150
151 RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
152 {
153 std::string s = stringf("$verific$%s", obj->Name());
154 if (obj->Linefile())
155 s += stringf("$%s:%d", Verific::LineFile::GetFileName(obj->Linefile()), Verific::LineFile::GetLineNo(obj->Linefile()));
156 s += stringf("$%d", autoidx++);
157 return s;
158 }
159
160 void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl)
161 {
162 MapIter mi;
163 Att *attr;
164
165 if (obj->Linefile())
166 attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
167
168 // FIXME: Parse numeric attributes
169 FOREACH_ATTRIBUTE(obj, mi, attr) {
170 if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
171 continue;
172 std::string val = std::string(attr->Value());
173 if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
174 val = val.substr(1,val.size()-2);
175 attributes[RTLIL::escape_id(attr->Key())] = RTLIL::Const(val);
176 }
177
178 if (nl) {
179 auto type_range = nl->GetTypeRange(obj->Name());
180 if (!type_range)
181 return;
182 if (!type_range->IsTypeEnum())
183 return;
184 #ifdef VERIFIC_VHDL_SUPPORT
185 if (nl->IsFromVhdl() && strcmp(type_range->GetTypeName(), "STD_LOGIC") == 0)
186 return;
187 #endif
188 auto type_name = type_range->GetTypeName();
189 if (!type_name)
190 return;
191 attributes.emplace(ID::wiretype, RTLIL::escape_id(type_name));
192
193 MapIter mi;
194 const char *k, *v;
195 FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mi, &k, &v) {
196 if (nl->IsFromVerilog()) {
197 // Expect <decimal>'b<binary>
198 auto p = strchr(v, '\'');
199 if (p) {
200 if (*(p+1) != 'b')
201 p = nullptr;
202 else
203 for (auto q = p+2; *q != '\0'; q++)
204 if (*q != '0' && *q != '1' && *q != 'x' && *q != 'z') {
205 p = nullptr;
206 break;
207 }
208 }
209 if (p == nullptr)
210 log_error("Expected TypeRange value '%s' to be of form <decimal>'b<binary>.\n", v);
211 attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k));
212 }
213 #ifdef VERIFIC_VHDL_SUPPORT
214 else if (nl->IsFromVhdl()) {
215 // Expect "<binary>" or plain <binary>
216 auto p = v;
217 if (p) {
218 if (*p != '"') {
219 auto l = strlen(p);
220 auto q = (char*)malloc(l+1);
221 strncpy(q, p, l);
222 q[l] = '\0';
223 for(char *ptr = q; *ptr; ++ptr )*ptr = tolower(*ptr);
224 attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k));
225 } else {
226 auto *q = p+1;
227 for (; *q != '"'; q++)
228 if (*q != '0' && *q != '1') {
229 p = nullptr;
230 break;
231 }
232 if (p && *(q+1) != '\0')
233 p = nullptr;
234
235 if (p != nullptr)
236 {
237 auto l = strlen(p);
238 auto q = (char*)malloc(l+1-2);
239 strncpy(q, p+1, l-2);
240 q[l-2] = '\0';
241 attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k));
242 free(q);
243 }
244 }
245 }
246 if (p == nullptr)
247 log_error("Expected TypeRange value '%s' to be of form \"<binary>\" or <binary>.\n", v);
248 }
249 #endif
250 }
251 }
252 }
253
254 RTLIL::SigSpec VerificImporter::operatorInput(Instance *inst)
255 {
256 RTLIL::SigSpec sig;
257 for (int i = int(inst->InputSize())-1; i >= 0; i--)
258 if (inst->GetInputBit(i))
259 sig.append(net_map_at(inst->GetInputBit(i)));
260 else
261 sig.append(RTLIL::State::Sz);
262 return sig;
263 }
264
265 RTLIL::SigSpec VerificImporter::operatorInput1(Instance *inst)
266 {
267 RTLIL::SigSpec sig;
268 for (int i = int(inst->Input1Size())-1; i >= 0; i--)
269 if (inst->GetInput1Bit(i))
270 sig.append(net_map_at(inst->GetInput1Bit(i)));
271 else
272 sig.append(RTLIL::State::Sz);
273 return sig;
274 }
275
276 RTLIL::SigSpec VerificImporter::operatorInput2(Instance *inst)
277 {
278 RTLIL::SigSpec sig;
279 for (int i = int(inst->Input2Size())-1; i >= 0; i--)
280 if (inst->GetInput2Bit(i))
281 sig.append(net_map_at(inst->GetInput2Bit(i)));
282 else
283 sig.append(RTLIL::State::Sz);
284 return sig;
285 }
286
287 RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portname)
288 {
289 PortBus *portbus = inst->View()->GetPortBus(portname);
290 if (portbus) {
291 RTLIL::SigSpec sig;
292 for (unsigned i = 0; i < portbus->Size(); i++) {
293 Net *net = inst->GetNet(portbus->ElementAtIndex(i));
294 if (net) {
295 if (net->IsGnd())
296 sig.append(RTLIL::State::S0);
297 else if (net->IsPwr())
298 sig.append(RTLIL::State::S1);
299 else
300 sig.append(net_map_at(net));
301 } else
302 sig.append(RTLIL::State::Sz);
303 }
304 return sig;
305 } else {
306 Port *port = inst->View()->GetPort(portname);
307 log_assert(port != NULL);
308 Net *net = inst->GetNet(port);
309 return net_map_at(net);
310 }
311 }
312
313 RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst, const pool<Net*, hash_ptr_ops> *any_all_nets)
314 {
315 RTLIL::SigSpec sig;
316 RTLIL::Wire *dummy_wire = NULL;
317 for (int i = int(inst->OutputSize())-1; i >= 0; i--)
318 if (inst->GetOutputBit(i) && (!any_all_nets || !any_all_nets->count(inst->GetOutputBit(i)))) {
319 sig.append(net_map_at(inst->GetOutputBit(i)));
320 dummy_wire = NULL;
321 } else {
322 if (dummy_wire == NULL)
323 dummy_wire = module->addWire(new_verific_id(inst));
324 else
325 dummy_wire->width++;
326 sig.append(RTLIL::SigSpec(dummy_wire, dummy_wire->width - 1));
327 }
328 return sig;
329 }
330
331 bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdString inst_name)
332 {
333 if (inst->Type() == PRIM_AND) {
334 module->addAndGate(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
335 return true;
336 }
337
338 if (inst->Type() == PRIM_NAND) {
339 RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst));
340 module->addAndGate(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
341 module->addNotGate(inst_name, tmp, net_map_at(inst->GetOutput()));
342 return true;
343 }
344
345 if (inst->Type() == PRIM_OR) {
346 module->addOrGate(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
347 return true;
348 }
349
350 if (inst->Type() == PRIM_NOR) {
351 RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst));
352 module->addOrGate(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
353 module->addNotGate(inst_name, tmp, net_map_at(inst->GetOutput()));
354 return true;
355 }
356
357 if (inst->Type() == PRIM_XOR) {
358 module->addXorGate(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
359 return true;
360 }
361
362 if (inst->Type() == PRIM_XNOR) {
363 module->addXnorGate(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
364 return true;
365 }
366
367 if (inst->Type() == PRIM_BUF) {
368 auto outnet = inst->GetOutput();
369 if (!any_all_nets.count(outnet))
370 module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet));
371 return true;
372 }
373
374 if (inst->Type() == PRIM_INV) {
375 module->addNotGate(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
376 return true;
377 }
378
379 if (inst->Type() == PRIM_MUX) {
380 module->addMuxGate(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
381 return true;
382 }
383
384 if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
385 module->addMuxGate(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
386 return true;
387 }
388
389 if (inst->Type() == PRIM_FADD)
390 {
391 RTLIL::SigSpec a = net_map_at(inst->GetInput1()), b = net_map_at(inst->GetInput2()), c = net_map_at(inst->GetCin());
392 RTLIL::SigSpec x = inst->GetCout() ? net_map_at(inst->GetCout()) : module->addWire(new_verific_id(inst));
393 RTLIL::SigSpec y = inst->GetOutput() ? net_map_at(inst->GetOutput()) : module->addWire(new_verific_id(inst));
394 RTLIL::SigSpec tmp1 = module->addWire(new_verific_id(inst));
395 RTLIL::SigSpec tmp2 = module->addWire(new_verific_id(inst));
396 RTLIL::SigSpec tmp3 = module->addWire(new_verific_id(inst));
397 module->addXorGate(new_verific_id(inst), a, b, tmp1);
398 module->addXorGate(inst_name, tmp1, c, y);
399 module->addAndGate(new_verific_id(inst), tmp1, c, tmp2);
400 module->addAndGate(new_verific_id(inst), a, b, tmp3);
401 module->addOrGate(new_verific_id(inst), tmp2, tmp3, x);
402 return true;
403 }
404
405 if (inst->Type() == PRIM_DFFRS)
406 {
407 VerificClocking clocking(this, inst->GetClock());
408 log_assert(clocking.disable_sig == State::S0);
409 log_assert(clocking.body_net == nullptr);
410
411 if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
412 clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
413 else if (inst->GetSet()->IsGnd())
414 clocking.addAdff(inst_name, net_map_at(inst->GetReset()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), State::S0);
415 else if (inst->GetReset()->IsGnd())
416 clocking.addAdff(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), State::S1);
417 else
418 clocking.addDffsr(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
419 net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
420 return true;
421 }
422
423 if (inst->Type() == PRIM_DLATCHRS)
424 {
425 if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
426 module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
427 else
428 module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
429 net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
430 return true;
431 }
432
433 if (inst->Type() == PRIM_DFF)
434 {
435 VerificClocking clocking(this, inst->GetClock());
436 log_assert(clocking.disable_sig == State::S0);
437 log_assert(clocking.body_net == nullptr);
438
439 if (inst->GetAsyncCond()->IsGnd())
440 clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
441 else
442 clocking.addAldff(inst_name, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()),
443 net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
444 return true;
445 }
446
447 if (inst->Type() == PRIM_DLATCH)
448 {
449 if (inst->GetAsyncCond()->IsGnd()) {
450 module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
451 } else {
452 RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
453 RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal())));
454 module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
455 }
456 return true;
457 }
458
459 return false;
460 }
461
462 bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdString inst_name)
463 {
464 RTLIL::Cell *cell = nullptr;
465
466 if (inst->Type() == PRIM_AND) {
467 cell = module->addAnd(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
468 import_attributes(cell->attributes, inst);
469 return true;
470 }
471
472 if (inst->Type() == PRIM_NAND) {
473 RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst));
474 cell = module->addAnd(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
475 import_attributes(cell->attributes, inst);
476 cell = module->addNot(inst_name, tmp, net_map_at(inst->GetOutput()));
477 import_attributes(cell->attributes, inst);
478 return true;
479 }
480
481 if (inst->Type() == PRIM_OR) {
482 cell = module->addOr(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
483 import_attributes(cell->attributes, inst);
484 return true;
485 }
486
487 if (inst->Type() == PRIM_NOR) {
488 RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst));
489 cell = module->addOr(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
490 import_attributes(cell->attributes, inst);
491 cell = module->addNot(inst_name, tmp, net_map_at(inst->GetOutput()));
492 import_attributes(cell->attributes, inst);
493 return true;
494 }
495
496 if (inst->Type() == PRIM_XOR) {
497 cell = module->addXor(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
498 import_attributes(cell->attributes, inst);
499 return true;
500 }
501
502 if (inst->Type() == PRIM_XNOR) {
503 cell = module->addXnor(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
504 import_attributes(cell->attributes, inst);
505 return true;
506 }
507
508 if (inst->Type() == PRIM_INV) {
509 cell = module->addNot(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
510 import_attributes(cell->attributes, inst);
511 return true;
512 }
513
514 if (inst->Type() == PRIM_MUX) {
515 cell = module->addMux(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
516 import_attributes(cell->attributes, inst);
517 return true;
518 }
519
520 if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
521 cell = module->addMux(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
522 import_attributes(cell->attributes, inst);
523 return true;
524 }
525
526 if (inst->Type() == PRIM_FADD)
527 {
528 RTLIL::SigSpec a_plus_b = module->addWire(new_verific_id(inst), 2);
529 RTLIL::SigSpec y = inst->GetOutput() ? net_map_at(inst->GetOutput()) : module->addWire(new_verific_id(inst));
530 if (inst->GetCout())
531 y.append(net_map_at(inst->GetCout()));
532 cell = module->addAdd(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), a_plus_b);
533 import_attributes(cell->attributes, inst);
534 cell = module->addAdd(inst_name, a_plus_b, net_map_at(inst->GetCin()), y);
535 import_attributes(cell->attributes, inst);
536 return true;
537 }
538
539 if (inst->Type() == PRIM_DFFRS)
540 {
541 VerificClocking clocking(this, inst->GetClock());
542 log_assert(clocking.disable_sig == State::S0);
543 log_assert(clocking.body_net == nullptr);
544
545 if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
546 cell = clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
547 else if (inst->GetSet()->IsGnd())
548 cell = clocking.addAdff(inst_name, net_map_at(inst->GetReset()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S0);
549 else if (inst->GetReset()->IsGnd())
550 cell = clocking.addAdff(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S1);
551 else
552 cell = clocking.addDffsr(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
553 net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
554 import_attributes(cell->attributes, inst);
555 return true;
556 }
557
558 if (inst->Type() == PRIM_DLATCHRS)
559 {
560 if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
561 cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
562 else
563 cell = module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
564 net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
565 import_attributes(cell->attributes, inst);
566 return true;
567 }
568
569 if (inst->Type() == PRIM_DFF)
570 {
571 VerificClocking clocking(this, inst->GetClock());
572 log_assert(clocking.disable_sig == State::S0);
573 log_assert(clocking.body_net == nullptr);
574
575 if (inst->GetAsyncCond()->IsGnd())
576 cell = clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
577 else
578 cell = clocking.addAldff(inst_name, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()),
579 net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
580 import_attributes(cell->attributes, inst);
581 return true;
582 }
583
584 if (inst->Type() == PRIM_DLATCH)
585 {
586 if (inst->GetAsyncCond()->IsGnd()) {
587 cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
588 } else {
589 RTLIL::SigSpec sig_set = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()));
590 RTLIL::SigSpec sig_clr = module->And(NEW_ID, net_map_at(inst->GetAsyncCond()), module->Not(NEW_ID, net_map_at(inst->GetAsyncVal())));
591 cell = module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
592 }
593 import_attributes(cell->attributes, inst);
594 return true;
595 }
596
597 #define IN operatorInput(inst)
598 #define IN1 operatorInput1(inst)
599 #define IN2 operatorInput2(inst)
600 #define OUT operatorOutput(inst)
601 #define FILTERED_OUT operatorOutput(inst, &any_all_nets)
602 #define SIGNED inst->View()->IsSigned()
603
604 if (inst->Type() == OPER_ADDER) {
605 RTLIL::SigSpec out = OUT;
606 if (inst->GetCout() != NULL)
607 out.append(net_map_at(inst->GetCout()));
608 if (inst->GetCin()->IsGnd()) {
609 cell = module->addAdd(inst_name, IN1, IN2, out, SIGNED);
610 import_attributes(cell->attributes, inst);
611 } else {
612 RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst), GetSize(out));
613 cell = module->addAdd(new_verific_id(inst), IN1, IN2, tmp, SIGNED);
614 import_attributes(cell->attributes, inst);
615 cell = module->addAdd(inst_name, tmp, net_map_at(inst->GetCin()), out, false);
616 import_attributes(cell->attributes, inst);
617 }
618 return true;
619 }
620
621 if (inst->Type() == OPER_MULTIPLIER) {
622 cell = module->addMul(inst_name, IN1, IN2, OUT, SIGNED);
623 import_attributes(cell->attributes, inst);
624 return true;
625 }
626
627 if (inst->Type() == OPER_DIVIDER) {
628 cell = module->addDiv(inst_name, IN1, IN2, OUT, SIGNED);
629 import_attributes(cell->attributes, inst);
630 return true;
631 }
632
633 if (inst->Type() == OPER_MODULO) {
634 cell = module->addMod(inst_name, IN1, IN2, OUT, SIGNED);
635 import_attributes(cell->attributes, inst);
636 return true;
637 }
638
639 if (inst->Type() == OPER_REMAINDER) {
640 cell = module->addMod(inst_name, IN1, IN2, OUT, SIGNED);
641 import_attributes(cell->attributes, inst);
642 return true;
643 }
644
645 if (inst->Type() == OPER_SHIFT_LEFT) {
646 cell = module->addShl(inst_name, IN1, IN2, OUT, false);
647 import_attributes(cell->attributes, inst);
648 return true;
649 }
650
651 if (inst->Type() == OPER_ENABLED_DECODER) {
652 RTLIL::SigSpec vec;
653 vec.append(net_map_at(inst->GetControl()));
654 for (unsigned i = 1; i < inst->OutputSize(); i++) {
655 vec.append(RTLIL::State::S0);
656 }
657 cell = module->addShl(inst_name, vec, IN, OUT, false);
658 import_attributes(cell->attributes, inst);
659 return true;
660 }
661
662 if (inst->Type() == OPER_DECODER) {
663 RTLIL::SigSpec vec;
664 vec.append(RTLIL::State::S1);
665 for (unsigned i = 1; i < inst->OutputSize(); i++) {
666 vec.append(RTLIL::State::S0);
667 }
668 cell = module->addShl(inst_name, vec, IN, OUT, false);
669 import_attributes(cell->attributes, inst);
670 return true;
671 }
672
673 if (inst->Type() == OPER_SHIFT_RIGHT) {
674 Net *net_cin = inst->GetCin();
675 Net *net_a_msb = inst->GetInput1Bit(0);
676 if (net_cin->IsGnd())
677 cell = module->addShr(inst_name, IN1, IN2, OUT, false);
678 else if (net_cin == net_a_msb)
679 cell = module->addSshr(inst_name, IN1, IN2, OUT, true);
680 else
681 log_error("Can't import Verific OPER_SHIFT_RIGHT instance %s: carry_in is neither 0 nor msb of left input\n", inst->Name());
682 import_attributes(cell->attributes, inst);
683 return true;
684 }
685
686 if (inst->Type() == OPER_REDUCE_AND) {
687 cell = module->addReduceAnd(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
688 import_attributes(cell->attributes, inst);
689 return true;
690 }
691
692 if (inst->Type() == OPER_REDUCE_NAND) {
693 Wire *tmp = module->addWire(NEW_ID);
694 cell = module->addReduceAnd(inst_name, IN, tmp, SIGNED);
695 module->addNot(NEW_ID, tmp, net_map_at(inst->GetOutput()));
696 import_attributes(cell->attributes, inst);
697 return true;
698 }
699
700 if (inst->Type() == OPER_REDUCE_OR) {
701 cell = module->addReduceOr(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
702 import_attributes(cell->attributes, inst);
703 return true;
704 }
705
706 if (inst->Type() == OPER_REDUCE_XOR) {
707 cell = module->addReduceXor(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
708 import_attributes(cell->attributes, inst);
709 return true;
710 }
711
712 if (inst->Type() == OPER_REDUCE_XNOR) {
713 cell = module->addReduceXnor(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
714 import_attributes(cell->attributes, inst);
715 return true;
716 }
717
718 if (inst->Type() == OPER_REDUCE_NOR) {
719 SigSpec t = module->ReduceOr(new_verific_id(inst), IN, SIGNED);
720 cell = module->addNot(inst_name, t, net_map_at(inst->GetOutput()));
721 import_attributes(cell->attributes, inst);
722 return true;
723 }
724
725 if (inst->Type() == OPER_LESSTHAN) {
726 Net *net_cin = inst->GetCin();
727 if (net_cin->IsGnd())
728 cell = module->addLt(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
729 else if (net_cin->IsPwr())
730 cell = module->addLe(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
731 else
732 log_error("Can't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", inst->Name());
733 import_attributes(cell->attributes, inst);
734 return true;
735 }
736
737 if (inst->Type() == OPER_WIDE_AND) {
738 cell = module->addAnd(inst_name, IN1, IN2, OUT, SIGNED);
739 import_attributes(cell->attributes, inst);
740 return true;
741 }
742
743 if (inst->Type() == OPER_WIDE_OR) {
744 cell = module->addOr(inst_name, IN1, IN2, OUT, SIGNED);
745 import_attributes(cell->attributes, inst);
746 return true;
747 }
748
749 if (inst->Type() == OPER_WIDE_XOR) {
750 cell = module->addXor(inst_name, IN1, IN2, OUT, SIGNED);
751 import_attributes(cell->attributes, inst);
752 return true;
753 }
754
755 if (inst->Type() == OPER_WIDE_XNOR) {
756 cell = module->addXnor(inst_name, IN1, IN2, OUT, SIGNED);
757 import_attributes(cell->attributes, inst);
758 return true;
759 }
760
761 if (inst->Type() == OPER_WIDE_BUF) {
762 cell = module->addPos(inst_name, IN, FILTERED_OUT, SIGNED);
763 import_attributes(cell->attributes, inst);
764 return true;
765 }
766
767 if (inst->Type() == OPER_WIDE_INV) {
768 cell = module->addNot(inst_name, IN, OUT, SIGNED);
769 import_attributes(cell->attributes, inst);
770 return true;
771 }
772
773 if (inst->Type() == OPER_MINUS) {
774 cell = module->addSub(inst_name, IN1, IN2, OUT, SIGNED);
775 import_attributes(cell->attributes, inst);
776 return true;
777 }
778
779 if (inst->Type() == OPER_UMINUS) {
780 cell = module->addNeg(inst_name, IN, OUT, SIGNED);
781 import_attributes(cell->attributes, inst);
782 return true;
783 }
784
785 if (inst->Type() == OPER_EQUAL) {
786 cell = module->addEq(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
787 import_attributes(cell->attributes, inst);
788 return true;
789 }
790
791 if (inst->Type() == OPER_NEQUAL) {
792 cell = module->addNe(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
793 import_attributes(cell->attributes, inst);
794 return true;
795 }
796
797 if (inst->Type() == OPER_WIDE_MUX) {
798 cell = module->addMux(inst_name, IN1, IN2, net_map_at(inst->GetControl()), OUT);
799 import_attributes(cell->attributes, inst);
800 return true;
801 }
802
803 if (inst->Type() == OPER_NTO1MUX) {
804 cell = module->addBmux(inst_name, IN2, IN1, net_map_at(inst->GetOutput()));
805 import_attributes(cell->attributes, inst);
806 return true;
807 }
808
809 if (inst->Type() == OPER_WIDE_NTO1MUX)
810 {
811 cell = module->addBmux(inst_name, IN2, IN1, OUT);
812 import_attributes(cell->attributes, inst);
813 return true;
814 }
815
816 if (inst->Type() == OPER_SELECTOR)
817 {
818 cell = module->addPmux(inst_name, State::S0, IN2, IN1, net_map_at(inst->GetOutput()));
819 import_attributes(cell->attributes, inst);
820 return true;
821 }
822
823 if (inst->Type() == OPER_WIDE_SELECTOR)
824 {
825 SigSpec out = OUT;
826 cell = module->addPmux(inst_name, SigSpec(State::S0, GetSize(out)), IN2, IN1, out);
827 import_attributes(cell->attributes, inst);
828 return true;
829 }
830
831 if (inst->Type() == OPER_WIDE_TRI) {
832 cell = module->addMux(inst_name, RTLIL::SigSpec(RTLIL::State::Sz, inst->OutputSize()), IN, net_map_at(inst->GetControl()), OUT);
833 import_attributes(cell->attributes, inst);
834 return true;
835 }
836
837 if (inst->Type() == OPER_WIDE_DFFRS)
838 {
839 VerificClocking clocking(this, inst->GetClock());
840 log_assert(clocking.disable_sig == State::S0);
841 log_assert(clocking.body_net == nullptr);
842
843 RTLIL::SigSpec sig_set = operatorInport(inst, "set");
844 RTLIL::SigSpec sig_reset = operatorInport(inst, "reset");
845
846 if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_reset.is_fully_const() && !sig_reset.as_bool())
847 cell = clocking.addDff(inst_name, IN, OUT);
848 else
849 cell = clocking.addDffsr(inst_name, sig_set, sig_reset, IN, OUT);
850 import_attributes(cell->attributes, inst);
851
852 return true;
853 }
854
855 if (inst->Type() == OPER_WIDE_DLATCHRS)
856 {
857 RTLIL::SigSpec sig_set = operatorInport(inst, "set");
858 RTLIL::SigSpec sig_reset = operatorInport(inst, "reset");
859
860 if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_reset.is_fully_const() && !sig_reset.as_bool())
861 cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), IN, OUT);
862 else
863 cell = module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_reset, IN, OUT);
864 import_attributes(cell->attributes, inst);
865
866 return true;
867 }
868
869 if (inst->Type() == OPER_WIDE_DFF)
870 {
871 VerificClocking clocking(this, inst->GetClock());
872 log_assert(clocking.disable_sig == State::S0);
873 log_assert(clocking.body_net == nullptr);
874
875 RTLIL::SigSpec sig_d = IN;
876 RTLIL::SigSpec sig_q = OUT;
877 RTLIL::SigSpec sig_adata = IN1;
878 RTLIL::SigSpec sig_acond = IN2;
879
880 if (sig_acond.is_fully_const() && !sig_acond.as_bool()) {
881 cell = clocking.addDff(inst_name, sig_d, sig_q);
882 import_attributes(cell->attributes, inst);
883 } else {
884 int offset = 0, width = 0;
885 for (offset = 0; offset < GetSize(sig_acond); offset += width) {
886 for (width = 1; offset+width < GetSize(sig_acond); width++)
887 if (sig_acond[offset] != sig_acond[offset+width]) break;
888 cell = clocking.addAldff(module->uniquify(inst_name), sig_acond[offset], sig_adata.extract(offset, width),
889 sig_d.extract(offset, width), sig_q.extract(offset, width));
890 import_attributes(cell->attributes, inst);
891 }
892 }
893
894 return true;
895 }
896
897 if (inst->Type() == OPER_WIDE_DLATCH)
898 {
899 RTLIL::SigSpec sig_d = IN;
900 RTLIL::SigSpec sig_q = OUT;
901 RTLIL::SigSpec sig_adata = IN1;
902 RTLIL::SigSpec sig_acond = IN2;
903
904 if (sig_acond.is_fully_const() && !sig_acond.as_bool()) {
905 cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), sig_d, sig_q);
906 import_attributes(cell->attributes, inst);
907 } else {
908 int offset = 0, width = 0;
909 for (offset = 0; offset < GetSize(sig_acond); offset += width) {
910 for (width = 1; offset+width < GetSize(sig_acond); width++)
911 if (sig_acond[offset] != sig_acond[offset+width]) break;
912 RTLIL::SigSpec sig_set = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), sig_adata.extract(offset, width), sig_acond[offset]);
913 RTLIL::SigSpec sig_clr = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), module->Not(NEW_ID, sig_adata.extract(offset, width)), sig_acond[offset]);
914 cell = module->addDlatchsr(module->uniquify(inst_name), net_map_at(inst->GetControl()), sig_set, sig_clr,
915 sig_d.extract(offset, width), sig_q.extract(offset, width));
916 import_attributes(cell->attributes, inst);
917 }
918 }
919
920 return true;
921 }
922
923 #undef IN
924 #undef IN1
925 #undef IN2
926 #undef OUT
927 #undef SIGNED
928
929 return false;
930 }
931
932 void VerificImporter::merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol)
933 {
934 bool keep_running = true;
935 SigMap sigmap;
936
937 while (keep_running)
938 {
939 keep_running = false;
940
941 dict<SigBit, pool<RTLIL::Cell*>> dbits_db;
942 SigSpec dbits;
943
944 for (auto cell : candidates) {
945 SigBit bit = sigmap(cell->getPort(ID::D));
946 dbits_db[bit].insert(cell);
947 dbits.append(bit);
948 }
949
950 dbits.sort_and_unify();
951
952 for (auto chunk : dbits.chunks())
953 {
954 SigSpec sig_d = chunk;
955
956 if (chunk.wire == nullptr || GetSize(sig_d) == 1)
957 continue;
958
959 SigSpec sig_q = module->addWire(NEW_ID, GetSize(sig_d));
960 RTLIL::Cell *new_ff = module->addDff(NEW_ID, clock, sig_d, sig_q, clock_pol);
961
962 if (verific_verbose)
963 log(" merging single-bit past_ffs into new %d-bit ff %s.\n", GetSize(sig_d), log_id(new_ff));
964
965 for (int i = 0; i < GetSize(sig_d); i++)
966 for (auto old_ff : dbits_db[sig_d[i]])
967 {
968 if (verific_verbose)
969 log(" replacing old ff %s on bit %d.\n", log_id(old_ff), i);
970
971 SigBit old_q = old_ff->getPort(ID::Q);
972 SigBit new_q = sig_q[i];
973
974 sigmap.add(old_q, new_q);
975 module->connect(old_q, new_q);
976 candidates.erase(old_ff);
977 module->remove(old_ff);
978 keep_running = true;
979 }
980 }
981 }
982 }
983
984 void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
985 {
986 dict<pair<SigBit, int>, pool<RTLIL::Cell*>> database;
987
988 for (auto cell : candidates)
989 {
990 SigBit clock = cell->getPort(ID::CLK);
991 bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool();
992 database[make_pair(clock, int(clock_pol))].insert(cell);
993 }
994
995 for (auto it : database)
996 merge_past_ffs_clock(it.second, it.first.first, it.first.second);
997 }
998
999 static std::string sha1_if_contain_spaces(std::string str)
1000 {
1001 if(str.find_first_of(' ') != std::string::npos) {
1002 std::size_t open = str.find_first_of('(');
1003 std::size_t closed = str.find_last_of(')');
1004 if (open != std::string::npos && closed != std::string::npos) {
1005 std::string content = str.substr(open + 1, closed - open - 1);
1006 return str.substr(0, open + 1) + sha1(content) + str.substr(closed);
1007 } else {
1008 return sha1(str);
1009 }
1010 }
1011 return str;
1012 }
1013
1014 void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::map<std::string,Netlist*> &nl_todo, bool norename)
1015 {
1016 std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name();
1017 std::string module_name = netlist_name;
1018
1019 if (nl->IsOperator() || nl->IsPrimitive()) {
1020 module_name = "$verific$" + module_name;
1021 } else {
1022 if (!norename && *nl->Name()) {
1023 module_name += "(";
1024 module_name += nl->Name();
1025 module_name += ")";
1026 }
1027 module_name = "\\" + sha1_if_contain_spaces(module_name);
1028 }
1029
1030 netlist = nl;
1031
1032 if (design->has(module_name)) {
1033 if (!nl->IsOperator() && !is_blackbox(nl))
1034 log_cmd_error("Re-definition of module `%s'.\n", netlist_name.c_str());
1035 return;
1036 }
1037
1038 module = new RTLIL::Module;
1039 module->name = module_name;
1040 design->add(module);
1041
1042 if (is_blackbox(nl)) {
1043 log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
1044 module->set_bool_attribute(ID::blackbox);
1045 } else {
1046 log("Importing module %s.\n", RTLIL::id2cstr(module->name));
1047 }
1048 import_attributes(module->attributes, nl, nl);
1049
1050 SetIter si;
1051 MapIter mi, mi2;
1052 Port *port;
1053 PortBus *portbus;
1054 Net *net;
1055 NetBus *netbus;
1056 Instance *inst;
1057 PortRef *pr;
1058
1059 FOREACH_PORT_OF_NETLIST(nl, mi, port)
1060 {
1061 if (port->Bus())
1062 continue;
1063
1064 if (verific_verbose)
1065 log(" importing port %s.\n", port->Name());
1066
1067 RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(port->Name()));
1068 import_attributes(wire->attributes, port, nl);
1069
1070 wire->port_id = nl->IndexOf(port) + 1;
1071
1072 if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_IN)
1073 wire->port_input = true;
1074 if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_OUT)
1075 wire->port_output = true;
1076
1077 if (port->GetNet()) {
1078 net = port->GetNet();
1079 if (net_map.count(net) == 0)
1080 net_map[net] = wire;
1081 else if (wire->port_input)
1082 module->connect(net_map_at(net), wire);
1083 else
1084 module->connect(wire, net_map_at(net));
1085 }
1086 }
1087
1088 FOREACH_PORTBUS_OF_NETLIST(nl, mi, portbus)
1089 {
1090 if (verific_verbose)
1091 log(" importing portbus %s.\n", portbus->Name());
1092
1093 RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(portbus->Name()), portbus->Size());
1094 wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
1095 import_attributes(wire->attributes, portbus, nl);
1096
1097 bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN;
1098 if (portbus_input)
1099 wire->port_input = true;
1100 if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_OUT)
1101 wire->port_output = true;
1102
1103 for (int i = portbus->LeftIndex();; i += portbus->IsUp() ? +1 : -1) {
1104 if (portbus->ElementAtIndex(i) && portbus->ElementAtIndex(i)->GetNet()) {
1105 bool bit_input = portbus_input;
1106 if (portbus->GetDir() == DIR_NONE) {
1107 Port *p = portbus->ElementAtIndex(i);
1108 bit_input = p->GetDir() == DIR_INOUT || p->GetDir() == DIR_IN;
1109 if (bit_input)
1110 wire->port_input = true;
1111 if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_OUT)
1112 wire->port_output = true;
1113 }
1114 net = portbus->ElementAtIndex(i)->GetNet();
1115 RTLIL::SigBit bit(wire, i - wire->start_offset);
1116 if (net_map.count(net) == 0)
1117 net_map[net] = bit;
1118 else if (bit_input)
1119 module->connect(net_map_at(net), bit);
1120 else
1121 module->connect(bit, net_map_at(net));
1122 }
1123 if (i == portbus->RightIndex())
1124 break;
1125 }
1126 }
1127
1128 module->fixup_ports();
1129
1130 dict<Net*, char, hash_ptr_ops> init_nets;
1131 pool<Net*, hash_ptr_ops> anyconst_nets, anyseq_nets;
1132 pool<Net*, hash_ptr_ops> allconst_nets, allseq_nets;
1133 any_all_nets.clear();
1134
1135 FOREACH_NET_OF_NETLIST(nl, mi, net)
1136 {
1137 if (net->IsRamNet())
1138 {
1139 RTLIL::Memory *memory = new RTLIL::Memory;
1140 memory->name = RTLIL::escape_id(net->Name());
1141 log_assert(module->count_id(memory->name) == 0);
1142 module->memories[memory->name] = memory;
1143
1144 int number_of_bits = net->Size();
1145 int bits_in_word = number_of_bits;
1146 FOREACH_PORTREF_OF_NET(net, si, pr) {
1147 if (pr->GetInst()->Type() == OPER_READ_PORT) {
1148 bits_in_word = min<int>(bits_in_word, pr->GetInst()->OutputSize());
1149 continue;
1150 }
1151 if (pr->GetInst()->Type() == OPER_WRITE_PORT || pr->GetInst()->Type() == OPER_CLOCKED_WRITE_PORT) {
1152 bits_in_word = min<int>(bits_in_word, pr->GetInst()->Input2Size());
1153 continue;
1154 }
1155 log_error("Verific RamNet %s is connected to unsupported instance type %s (%s).\n",
1156 net->Name(), pr->GetInst()->View()->Owner()->Name(), pr->GetInst()->Name());
1157 }
1158
1159 memory->width = bits_in_word;
1160 memory->size = number_of_bits / bits_in_word;
1161
1162 const char *ascii_initdata = net->GetWideInitialValue();
1163 if (ascii_initdata) {
1164 while (*ascii_initdata != 0 && *ascii_initdata != '\'')
1165 ascii_initdata++;
1166 if (*ascii_initdata == '\'')
1167 ascii_initdata++;
1168 if (*ascii_initdata != 0) {
1169 log_assert(*ascii_initdata == 'b');
1170 ascii_initdata++;
1171 }
1172 for (int word_idx = 0; word_idx < memory->size; word_idx++) {
1173 Const initval = Const(State::Sx, memory->width);
1174 bool initval_valid = false;
1175 for (int bit_idx = memory->width-1; bit_idx >= 0; bit_idx--) {
1176 if (*ascii_initdata == 0)
1177 break;
1178 if (*ascii_initdata == '0' || *ascii_initdata == '1') {
1179 initval[bit_idx] = (*ascii_initdata == '0') ? State::S0 : State::S1;
1180 initval_valid = true;
1181 }
1182 ascii_initdata++;
1183 }
1184 if (initval_valid) {
1185 RTLIL::Cell *cell = module->addCell(new_verific_id(net), ID($meminit));
1186 cell->parameters[ID::WORDS] = 1;
1187 if (net->GetOrigTypeRange()->LeftRangeBound() < net->GetOrigTypeRange()->RightRangeBound())
1188 cell->setPort(ID::ADDR, word_idx);
1189 else
1190 cell->setPort(ID::ADDR, memory->size - word_idx - 1);
1191 cell->setPort(ID::DATA, initval);
1192 cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str());
1193 cell->parameters[ID::ABITS] = 32;
1194 cell->parameters[ID::WIDTH] = memory->width;
1195 cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
1196 }
1197 }
1198 }
1199 continue;
1200 }
1201
1202 if (net->GetInitialValue())
1203 init_nets[net] = net->GetInitialValue();
1204
1205 const char *rand_const_attr = net->GetAttValue(" rand_const");
1206 const char *rand_attr = net->GetAttValue(" rand");
1207
1208 const char *anyconst_attr = net->GetAttValue("anyconst");
1209 const char *anyseq_attr = net->GetAttValue("anyseq");
1210
1211 const char *allconst_attr = net->GetAttValue("allconst");
1212 const char *allseq_attr = net->GetAttValue("allseq");
1213
1214 if (rand_const_attr != nullptr && (!strcmp(rand_const_attr, "1") || !strcmp(rand_const_attr, "'1'"))) {
1215 anyconst_nets.insert(net);
1216 any_all_nets.insert(net);
1217 }
1218 else if (rand_attr != nullptr && (!strcmp(rand_attr, "1") || !strcmp(rand_attr, "'1'"))) {
1219 anyseq_nets.insert(net);
1220 any_all_nets.insert(net);
1221 }
1222 else if (anyconst_attr != nullptr && (!strcmp(anyconst_attr, "1") || !strcmp(anyconst_attr, "'1'"))) {
1223 anyconst_nets.insert(net);
1224 any_all_nets.insert(net);
1225 }
1226 else if (anyseq_attr != nullptr && (!strcmp(anyseq_attr, "1") || !strcmp(anyseq_attr, "'1'"))) {
1227 anyseq_nets.insert(net);
1228 any_all_nets.insert(net);
1229 }
1230 else if (allconst_attr != nullptr && (!strcmp(allconst_attr, "1") || !strcmp(allconst_attr, "'1'"))) {
1231 allconst_nets.insert(net);
1232 any_all_nets.insert(net);
1233 }
1234 else if (allseq_attr != nullptr && (!strcmp(allseq_attr, "1") || !strcmp(allseq_attr, "'1'"))) {
1235 allseq_nets.insert(net);
1236 any_all_nets.insert(net);
1237 }
1238
1239 if (net_map.count(net)) {
1240 if (verific_verbose)
1241 log(" skipping net %s.\n", net->Name());
1242 continue;
1243 }
1244
1245 if (net->Bus())
1246 continue;
1247
1248 RTLIL::IdString wire_name = module->uniquify(mode_names || net->IsUserDeclared() ? RTLIL::escape_id(net->Name()) : new_verific_id(net));
1249
1250 if (verific_verbose)
1251 log(" importing net %s as %s.\n", net->Name(), log_id(wire_name));
1252
1253 RTLIL::Wire *wire = module->addWire(wire_name);
1254 import_attributes(wire->attributes, net, nl);
1255
1256 net_map[net] = wire;
1257 }
1258
1259 FOREACH_NETBUS_OF_NETLIST(nl, mi, netbus)
1260 {
1261 bool found_new_net = false;
1262 for (int i = netbus->LeftIndex();; i += netbus->IsUp() ? +1 : -1) {
1263 net = netbus->ElementAtIndex(i);
1264 if (net_map.count(net) == 0)
1265 found_new_net = true;
1266 if (i == netbus->RightIndex())
1267 break;
1268 }
1269
1270 if (found_new_net)
1271 {
1272 RTLIL::IdString wire_name = module->uniquify(mode_names || netbus->IsUserDeclared() ? RTLIL::escape_id(netbus->Name()) : new_verific_id(netbus));
1273
1274 if (verific_verbose)
1275 log(" importing netbus %s as %s.\n", netbus->Name(), log_id(wire_name));
1276
1277 RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
1278 wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
1279 MapIter mibus;
1280 FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
1281 if (net)
1282 import_attributes(wire->attributes, net, nl);
1283 break;
1284 }
1285
1286 RTLIL::Const initval = Const(State::Sx, GetSize(wire));
1287 bool initval_valid = false;
1288
1289 for (int i = netbus->LeftIndex();; i += netbus->IsUp() ? +1 : -1)
1290 {
1291 if (netbus->ElementAtIndex(i))
1292 {
1293 int bitidx = i - wire->start_offset;
1294 net = netbus->ElementAtIndex(i);
1295 RTLIL::SigBit bit(wire, bitidx);
1296
1297 if (init_nets.count(net)) {
1298 if (init_nets.at(net) == '0')
1299 initval.bits.at(bitidx) = State::S0;
1300 if (init_nets.at(net) == '1')
1301 initval.bits.at(bitidx) = State::S1;
1302 initval_valid = true;
1303 init_nets.erase(net);
1304 }
1305
1306 if (net_map.count(net) == 0)
1307 net_map[net] = bit;
1308 else
1309 module->connect(bit, net_map_at(net));
1310 }
1311
1312 if (i == netbus->RightIndex())
1313 break;
1314 }
1315
1316 if (initval_valid)
1317 wire->attributes[ID::init] = initval;
1318 }
1319 else
1320 {
1321 if (verific_verbose)
1322 log(" skipping netbus %s.\n", netbus->Name());
1323 }
1324
1325 SigSpec anyconst_sig;
1326 SigSpec anyseq_sig;
1327 SigSpec allconst_sig;
1328 SigSpec allseq_sig;
1329
1330 for (int i = netbus->RightIndex();; i += netbus->IsUp() ? -1 : +1) {
1331 net = netbus->ElementAtIndex(i);
1332 if (net != nullptr && anyconst_nets.count(net)) {
1333 anyconst_sig.append(net_map_at(net));
1334 anyconst_nets.erase(net);
1335 }
1336 if (net != nullptr && anyseq_nets.count(net)) {
1337 anyseq_sig.append(net_map_at(net));
1338 anyseq_nets.erase(net);
1339 }
1340 if (net != nullptr && allconst_nets.count(net)) {
1341 allconst_sig.append(net_map_at(net));
1342 allconst_nets.erase(net);
1343 }
1344 if (net != nullptr && allseq_nets.count(net)) {
1345 allseq_sig.append(net_map_at(net));
1346 allseq_nets.erase(net);
1347 }
1348 if (i == netbus->LeftIndex())
1349 break;
1350 }
1351
1352 if (GetSize(anyconst_sig))
1353 module->connect(anyconst_sig, module->Anyconst(new_verific_id(netbus), GetSize(anyconst_sig)));
1354
1355 if (GetSize(anyseq_sig))
1356 module->connect(anyseq_sig, module->Anyseq(new_verific_id(netbus), GetSize(anyseq_sig)));
1357
1358 if (GetSize(allconst_sig))
1359 module->connect(allconst_sig, module->Allconst(new_verific_id(netbus), GetSize(allconst_sig)));
1360
1361 if (GetSize(allseq_sig))
1362 module->connect(allseq_sig, module->Allseq(new_verific_id(netbus), GetSize(allseq_sig)));
1363 }
1364
1365 for (auto it : init_nets)
1366 {
1367 Const initval;
1368 SigBit bit = net_map_at(it.first);
1369 log_assert(bit.wire);
1370
1371 if (bit.wire->attributes.count(ID::init))
1372 initval = bit.wire->attributes.at(ID::init);
1373
1374 while (GetSize(initval) < GetSize(bit.wire))
1375 initval.bits.push_back(State::Sx);
1376
1377 if (it.second == '0')
1378 initval.bits.at(bit.offset) = State::S0;
1379 if (it.second == '1')
1380 initval.bits.at(bit.offset) = State::S1;
1381
1382 bit.wire->attributes[ID::init] = initval;
1383 }
1384
1385 for (auto net : anyconst_nets)
1386 module->connect(net_map_at(net), module->Anyconst(new_verific_id(net)));
1387
1388 for (auto net : anyseq_nets)
1389 module->connect(net_map_at(net), module->Anyseq(new_verific_id(net)));
1390
1391 pool<Instance*, hash_ptr_ops> sva_asserts;
1392 pool<Instance*, hash_ptr_ops> sva_assumes;
1393 pool<Instance*, hash_ptr_ops> sva_covers;
1394 pool<Instance*, hash_ptr_ops> sva_triggers;
1395
1396 pool<RTLIL::Cell*> past_ffs;
1397
1398 FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
1399 {
1400 RTLIL::IdString inst_name = module->uniquify(mode_names || inst->IsUserDeclared() ? RTLIL::escape_id(inst->Name()) : new_verific_id(inst));
1401
1402 if (verific_verbose)
1403 log(" importing cell %s (%s) as %s.\n", inst->Name(), inst->View()->Owner()->Name(), log_id(inst_name));
1404
1405 if (mode_verific)
1406 goto import_verific_cells;
1407
1408 if (inst->Type() == PRIM_PWR) {
1409 module->connect(net_map_at(inst->GetOutput()), RTLIL::State::S1);
1410 continue;
1411 }
1412
1413 if (inst->Type() == PRIM_GND) {
1414 module->connect(net_map_at(inst->GetOutput()), RTLIL::State::S0);
1415 continue;
1416 }
1417
1418 if (inst->Type() == PRIM_BUF) {
1419 auto outnet = inst->GetOutput();
1420 if (!any_all_nets.count(outnet))
1421 module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet));
1422 continue;
1423 }
1424
1425 if (inst->Type() == PRIM_X) {
1426 module->connect(net_map_at(inst->GetOutput()), RTLIL::State::Sx);
1427 continue;
1428 }
1429
1430 if (inst->Type() == PRIM_Z) {
1431 module->connect(net_map_at(inst->GetOutput()), RTLIL::State::Sz);
1432 continue;
1433 }
1434
1435 if (inst->Type() == OPER_READ_PORT)
1436 {
1437 RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name()), nullptr);
1438 if (!memory)
1439 log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name());
1440
1441 int numchunks = int(inst->OutputSize()) / memory->width;
1442 int chunksbits = ceil_log2(numchunks);
1443
1444 for (int i = 0; i < numchunks; i++)
1445 {
1446 RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
1447 RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
1448
1449 RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
1450 RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd));
1451 cell->parameters[ID::MEMID] = memory->name.str();
1452 cell->parameters[ID::CLK_ENABLE] = false;
1453 cell->parameters[ID::CLK_POLARITY] = true;
1454 cell->parameters[ID::TRANSPARENT] = false;
1455 cell->parameters[ID::ABITS] = GetSize(addr);
1456 cell->parameters[ID::WIDTH] = GetSize(data);
1457 cell->setPort(ID::CLK, RTLIL::State::Sx);
1458 cell->setPort(ID::EN, RTLIL::State::Sx);
1459 cell->setPort(ID::ADDR, addr);
1460 cell->setPort(ID::DATA, data);
1461 }
1462 continue;
1463 }
1464
1465 if (inst->Type() == OPER_WRITE_PORT || inst->Type() == OPER_CLOCKED_WRITE_PORT)
1466 {
1467 RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()), nullptr);
1468 if (!memory)
1469 log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name());
1470 int numchunks = int(inst->Input2Size()) / memory->width;
1471 int chunksbits = ceil_log2(numchunks);
1472
1473 for (int i = 0; i < numchunks; i++)
1474 {
1475 RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
1476 RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
1477
1478 RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
1479 RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr));
1480 cell->parameters[ID::MEMID] = memory->name.str();
1481 cell->parameters[ID::CLK_ENABLE] = false;
1482 cell->parameters[ID::CLK_POLARITY] = true;
1483 cell->parameters[ID::PRIORITY] = 0;
1484 cell->parameters[ID::ABITS] = GetSize(addr);
1485 cell->parameters[ID::WIDTH] = GetSize(data);
1486 cell->setPort(ID::EN, RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data)));
1487 cell->setPort(ID::CLK, RTLIL::State::S0);
1488 cell->setPort(ID::ADDR, addr);
1489 cell->setPort(ID::DATA, data);
1490
1491 if (inst->Type() == OPER_CLOCKED_WRITE_PORT) {
1492 cell->parameters[ID::CLK_ENABLE] = true;
1493 cell->setPort(ID::CLK, net_map_at(inst->GetClock()));
1494 }
1495 }
1496 continue;
1497 }
1498
1499 if (!mode_gates) {
1500 if (import_netlist_instance_cells(inst, inst_name))
1501 continue;
1502 if (inst->IsOperator() && !verific_sva_prims.count(inst->Type()))
1503 log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst->View()->Owner()->Name());
1504 } else {
1505 if (import_netlist_instance_gates(inst, inst_name))
1506 continue;
1507 }
1508
1509 if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT)
1510 sva_asserts.insert(inst);
1511
1512 if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME || inst->Type() == PRIM_SVA_RESTRICT)
1513 sva_assumes.insert(inst);
1514
1515 if (inst->Type() == PRIM_SVA_COVER || inst->Type() == PRIM_SVA_IMMEDIATE_COVER)
1516 sva_covers.insert(inst);
1517
1518 if (inst->Type() == PRIM_SVA_TRIGGERED)
1519 sva_triggers.insert(inst);
1520
1521 if (inst->Type() == OPER_SVA_STABLE)
1522 {
1523 VerificClocking clocking(this, inst->GetInput2Bit(0));
1524 log_assert(clocking.disable_sig == State::S0);
1525 log_assert(clocking.body_net == nullptr);
1526
1527 log_assert(inst->Input1Size() == inst->OutputSize());
1528
1529 SigSpec sig_d, sig_q, sig_o;
1530 sig_q = module->addWire(new_verific_id(inst), inst->Input1Size());
1531
1532 for (int i = int(inst->Input1Size())-1; i >= 0; i--){
1533 sig_d.append(net_map_at(inst->GetInput1Bit(i)));
1534 sig_o.append(net_map_at(inst->GetOutputBit(i)));
1535 }
1536
1537 if (verific_verbose) {
1538 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
1539 log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
1540 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1541 log_signal(sig_d), log_signal(sig_q), log_signal(sig_o));
1542 }
1543
1544 clocking.addDff(new_verific_id(inst), sig_d, sig_q);
1545 module->addXnor(new_verific_id(inst), sig_d, sig_q, sig_o);
1546
1547 if (!mode_keep)
1548 continue;
1549 }
1550
1551 if (inst->Type() == PRIM_SVA_STABLE)
1552 {
1553 VerificClocking clocking(this, inst->GetInput2());
1554 log_assert(clocking.disable_sig == State::S0);
1555 log_assert(clocking.body_net == nullptr);
1556
1557 SigSpec sig_d = net_map_at(inst->GetInput1());
1558 SigSpec sig_o = net_map_at(inst->GetOutput());
1559 SigSpec sig_q = module->addWire(new_verific_id(inst));
1560
1561 if (verific_verbose) {
1562 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
1563 log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
1564 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1565 log_signal(sig_d), log_signal(sig_q), log_signal(sig_o));
1566 }
1567
1568 clocking.addDff(new_verific_id(inst), sig_d, sig_q);
1569 module->addXnor(new_verific_id(inst), sig_d, sig_q, sig_o);
1570
1571 if (!mode_keep)
1572 continue;
1573 }
1574
1575 if (inst->Type() == PRIM_SVA_PAST)
1576 {
1577 VerificClocking clocking(this, inst->GetInput2());
1578 log_assert(clocking.disable_sig == State::S0);
1579 log_assert(clocking.body_net == nullptr);
1580
1581 SigBit sig_d = net_map_at(inst->GetInput1());
1582 SigBit sig_q = net_map_at(inst->GetOutput());
1583
1584 if (verific_verbose)
1585 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
1586 log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
1587
1588 past_ffs.insert(clocking.addDff(new_verific_id(inst), sig_d, sig_q));
1589
1590 if (!mode_keep)
1591 continue;
1592 }
1593
1594 if ((inst->Type() == PRIM_SVA_ROSE || inst->Type() == PRIM_SVA_FELL))
1595 {
1596 VerificClocking clocking(this, inst->GetInput2());
1597 log_assert(clocking.disable_sig == State::S0);
1598 log_assert(clocking.body_net == nullptr);
1599
1600 SigBit sig_d = net_map_at(inst->GetInput1());
1601 SigBit sig_o = net_map_at(inst->GetOutput());
1602 SigBit sig_q = module->addWire(new_verific_id(inst));
1603
1604 if (verific_verbose)
1605 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
1606 log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
1607
1608 clocking.addDff(new_verific_id(inst), sig_d, sig_q);
1609 module->addEq(new_verific_id(inst), {sig_q, sig_d}, Const(inst->Type() == PRIM_SVA_ROSE ? 1 : 2, 2), sig_o);
1610
1611 if (!mode_keep)
1612 continue;
1613 }
1614
1615 if (inst->Type() == PRIM_YOSYSHQ_INITSTATE)
1616 {
1617 if (verific_verbose)
1618 log(" adding YosysHQ init state\n");
1619 SigBit initstate = module->Initstate(new_verific_id(inst));
1620 SigBit sig_o = net_map_at(inst->GetOutput());
1621 module->connect(sig_o, initstate);
1622
1623 if (!mode_keep)
1624 continue;
1625 }
1626
1627 if (!mode_keep && verific_sva_prims.count(inst->Type())) {
1628 if (verific_verbose)
1629 log(" skipping SVA cell in non k-mode\n");
1630 continue;
1631 }
1632
1633 if (inst->Type() == PRIM_HDL_ASSERTION)
1634 {
1635 SigBit cond = net_map_at(inst->GetInput());
1636
1637 if (verific_verbose)
1638 log(" assert condition %s.\n", log_signal(cond));
1639
1640 const char *assume_attr = nullptr; // inst->GetAttValue("assume");
1641
1642 Cell *cell = nullptr;
1643 if (assume_attr != nullptr && !strcmp(assume_attr, "1"))
1644 cell = module->addAssume(new_verific_id(inst), cond, State::S1);
1645 else
1646 cell = module->addAssert(new_verific_id(inst), cond, State::S1);
1647
1648 import_attributes(cell->attributes, inst);
1649 continue;
1650 }
1651
1652 if (inst->IsPrimitive())
1653 {
1654 if (!mode_keep)
1655 log_error("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name());
1656
1657 if (!verific_sva_prims.count(inst->Type()))
1658 log_warning("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name());
1659 }
1660
1661 import_verific_cells:
1662 std::string inst_type = inst->View()->Owner()->Name();
1663
1664 nl_todo[inst_type] = inst->View();
1665
1666 if (inst->View()->IsOperator() || inst->View()->IsPrimitive()) {
1667 inst_type = "$verific$" + inst_type;
1668 } else {
1669 if (*inst->View()->Name()) {
1670 inst_type += "(";
1671 inst_type += inst->View()->Name();
1672 inst_type += ")";
1673 }
1674 inst_type = "\\" + sha1_if_contain_spaces(inst_type);
1675 }
1676
1677 RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
1678
1679 if (inst->IsPrimitive() && mode_keep)
1680 cell->attributes[ID::keep] = 1;
1681
1682 dict<IdString, vector<SigBit>> cell_port_conns;
1683
1684 if (verific_verbose)
1685 log(" ports in verific db:\n");
1686
1687 FOREACH_PORTREF_OF_INST(inst, mi2, pr) {
1688 if (verific_verbose)
1689 log(" .%s(%s)\n", pr->GetPort()->Name(), pr->GetNet()->Name());
1690 const char *port_name = pr->GetPort()->Name();
1691 int port_offset = 0;
1692 if (pr->GetPort()->Bus()) {
1693 port_name = pr->GetPort()->Bus()->Name();
1694 port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) -
1695 min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
1696 }
1697 IdString port_name_id = RTLIL::escape_id(port_name);
1698 auto &sigvec = cell_port_conns[port_name_id];
1699 if (GetSize(sigvec) <= port_offset) {
1700 SigSpec zwires = module->addWire(new_verific_id(inst), port_offset+1-GetSize(sigvec));
1701 for (auto bit : zwires)
1702 sigvec.push_back(bit);
1703 }
1704 sigvec[port_offset] = net_map_at(pr->GetNet());
1705 }
1706
1707 if (verific_verbose)
1708 log(" ports in yosys db:\n");
1709
1710 for (auto &it : cell_port_conns) {
1711 if (verific_verbose)
1712 log(" .%s(%s)\n", log_id(it.first), log_signal(it.second));
1713 cell->setPort(it.first, it.second);
1714 }
1715 }
1716
1717 if (!mode_nosva)
1718 {
1719 for (auto inst : sva_asserts) {
1720 if (mode_autocover)
1721 verific_import_sva_cover(this, inst);
1722 verific_import_sva_assert(this, inst);
1723 }
1724
1725 for (auto inst : sva_assumes)
1726 verific_import_sva_assume(this, inst);
1727
1728 for (auto inst : sva_covers)
1729 verific_import_sva_cover(this, inst);
1730
1731 for (auto inst : sva_triggers)
1732 verific_import_sva_trigger(this, inst);
1733
1734 merge_past_ffs(past_ffs);
1735 }
1736
1737 if (!mode_fullinit)
1738 {
1739 pool<SigBit> non_ff_bits;
1740 CellTypes ff_types;
1741
1742 ff_types.setup_internals_ff();
1743 ff_types.setup_stdcells_mem();
1744
1745 for (auto cell : module->cells())
1746 {
1747 if (ff_types.cell_known(cell->type))
1748 continue;
1749
1750 for (auto conn : cell->connections())
1751 {
1752 if (!cell->output(conn.first))
1753 continue;
1754
1755 for (auto bit : conn.second)
1756 if (bit.wire != nullptr)
1757 non_ff_bits.insert(bit);
1758 }
1759 }
1760
1761 for (auto wire : module->wires())
1762 {
1763 if (!wire->attributes.count(ID::init))
1764 continue;
1765
1766 Const &initval = wire->attributes.at(ID::init);
1767 for (int i = 0; i < GetSize(initval); i++)
1768 {
1769 if (initval[i] != State::S0 && initval[i] != State::S1)
1770 continue;
1771
1772 if (non_ff_bits.count(SigBit(wire, i)))
1773 initval[i] = State::Sx;
1774 }
1775
1776 if (initval.is_fully_undef())
1777 wire->attributes.erase(ID::init);
1778 }
1779 }
1780 }
1781
1782 // ==================================================================
1783
1784 VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_at_only)
1785 {
1786 module = importer->module;
1787
1788 log_assert(importer != nullptr);
1789 log_assert(net != nullptr);
1790
1791 Instance *inst = net->Driver();
1792
1793 if (inst != nullptr && inst->Type() == PRIM_SVA_AT)
1794 {
1795 net = inst->GetInput1();
1796 body_net = inst->GetInput2();
1797
1798 inst = net->Driver();
1799
1800 Instance *body_inst = body_net->Driver();
1801 if (body_inst != nullptr && body_inst->Type() == PRIM_SVA_DISABLE_IFF) {
1802 disable_net = body_inst->GetInput1();
1803 disable_sig = importer->net_map_at(disable_net);
1804 body_net = body_inst->GetInput2();
1805 }
1806 }
1807 else
1808 {
1809 if (sva_at_only)
1810 return;
1811 }
1812
1813 // Use while() instead of if() to work around VIPER #13453
1814 while (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE)
1815 {
1816 net = inst->GetInput();
1817 inst = net->Driver();;
1818 }
1819
1820 if (inst != nullptr && inst->Type() == PRIM_INV)
1821 {
1822 net = inst->GetInput();
1823 inst = net->Driver();;
1824 posedge = false;
1825 }
1826
1827 // Detect clock-enable circuit
1828 do {
1829 if (inst == nullptr || inst->Type() != PRIM_AND)
1830 break;
1831
1832 Net *net_dlatch = inst->GetInput1();
1833 Instance *inst_dlatch = net_dlatch->Driver();
1834
1835 if (inst_dlatch == nullptr || inst_dlatch->Type() != PRIM_DLATCHRS)
1836 break;
1837
1838 if (!inst_dlatch->GetSet()->IsGnd() || !inst_dlatch->GetReset()->IsGnd())
1839 break;
1840
1841 Net *net_enable = inst_dlatch->GetInput();
1842 Net *net_not_clock = inst_dlatch->GetControl();
1843
1844 if (net_enable == nullptr || net_not_clock == nullptr)
1845 break;
1846
1847 Instance *inst_not_clock = net_not_clock->Driver();
1848
1849 if (inst_not_clock == nullptr || inst_not_clock->Type() != PRIM_INV)
1850 break;
1851
1852 Net *net_clock1 = inst_not_clock->GetInput();
1853 Net *net_clock2 = inst->GetInput2();
1854
1855 if (net_clock1 == nullptr || net_clock1 != net_clock2)
1856 break;
1857
1858 enable_net = net_enable;
1859 enable_sig = importer->net_map_at(enable_net);
1860
1861 net = net_clock1;
1862 inst = net->Driver();;
1863 } while (0);
1864
1865 // Detect condition expression
1866 do {
1867 if (body_net == nullptr)
1868 break;
1869
1870 Instance *inst_mux = body_net->Driver();
1871
1872 if (inst_mux == nullptr || inst_mux->Type() != PRIM_MUX)
1873 break;
1874
1875 if (!inst_mux->GetInput1()->IsPwr())
1876 break;
1877
1878 Net *sva_net = inst_mux->GetInput2();
1879 if (!verific_is_sva_net(importer, sva_net))
1880 break;
1881
1882 body_net = sva_net;
1883 cond_net = inst_mux->GetControl();
1884 } while (0);
1885
1886 clock_net = net;
1887 clock_sig = importer->net_map_at(clock_net);
1888
1889 const char *gclk_attr = clock_net->GetAttValue("gclk");
1890 if (gclk_attr != nullptr && (!strcmp(gclk_attr, "1") || !strcmp(gclk_attr, "'1'")))
1891 gclk = true;
1892 }
1893
1894 Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value)
1895 {
1896 log_assert(GetSize(sig_d) == GetSize(sig_q));
1897
1898 auto set_init_attribute = [&](SigSpec &s) {
1899 if (GetSize(init_value) == 0)
1900 return;
1901 log_assert(GetSize(s) == GetSize(init_value));
1902 if (s.is_wire()) {
1903 s.as_wire()->attributes[ID::init] = init_value;
1904 } else {
1905 Wire *w = module->addWire(NEW_ID, GetSize(s));
1906 w->attributes[ID::init] = init_value;
1907 module->connect(s, w);
1908 s = w;
1909 }
1910 };
1911
1912 if (enable_sig != State::S1)
1913 sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
1914
1915 if (disable_sig != State::S0) {
1916 log_assert(GetSize(sig_q) == GetSize(init_value));
1917
1918 if (gclk) {
1919 Wire *pre_d = module->addWire(NEW_ID, GetSize(sig_d));
1920 Wire *post_q_w = module->addWire(NEW_ID, GetSize(sig_q));
1921
1922 Const initval(State::Sx, GetSize(sig_q));
1923 int offset = 0;
1924 for (auto c : sig_q.chunks()) {
1925 if (c.wire && c.wire->attributes.count(ID::init)) {
1926 Const val = c.wire->attributes.at(ID::init);
1927 for (int i = 0; i < GetSize(c); i++)
1928 initval[offset+i] = val[c.offset+i];
1929 }
1930 offset += GetSize(c);
1931 }
1932
1933 if (!initval.is_fully_undef())
1934 post_q_w->attributes[ID::init] = initval;
1935
1936 module->addMux(NEW_ID, sig_d, init_value, disable_sig, pre_d);
1937 module->addMux(NEW_ID, post_q_w, init_value, disable_sig, sig_q);
1938
1939 SigSpec post_q(post_q_w);
1940 set_init_attribute(post_q);
1941 return module->addFf(name, pre_d, post_q);
1942 }
1943
1944 set_init_attribute(sig_q);
1945 return module->addAdff(name, clock_sig, disable_sig, sig_d, sig_q, init_value, posedge);
1946 }
1947
1948 if (gclk) {
1949 set_init_attribute(sig_q);
1950 return module->addFf(name, sig_d, sig_q);
1951 }
1952
1953 set_init_attribute(sig_q);
1954 return module->addDff(name, clock_sig, sig_d, sig_q, posedge);
1955 }
1956
1957 Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value)
1958 {
1959 log_assert(gclk == false);
1960 log_assert(disable_sig == State::S0);
1961
1962 // FIXME: Adffe
1963 if (enable_sig != State::S1)
1964 sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
1965
1966 return module->addAdff(name, clock_sig, sig_arst, sig_d, sig_q, arst_value, posedge);
1967 }
1968
1969 Cell *VerificClocking::addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q)
1970 {
1971 log_assert(gclk == false);
1972 log_assert(disable_sig == State::S0);
1973
1974 // FIXME: Dffsre
1975 if (enable_sig != State::S1)
1976 sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
1977
1978 return module->addDffsr(name, clock_sig, sig_set, sig_clr, sig_d, sig_q, posedge);
1979 }
1980
1981 Cell *VerificClocking::addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::SigSpec sig_adata, SigSpec sig_d, SigSpec sig_q)
1982 {
1983 log_assert(disable_sig == State::S0);
1984
1985 // FIXME: Aldffe
1986 if (enable_sig != State::S1)
1987 sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
1988
1989 if (gclk) {
1990 Wire *pre_d = module->addWire(NEW_ID, GetSize(sig_d));
1991 Wire *post_q = module->addWire(NEW_ID, GetSize(sig_q));
1992
1993 Const initval(State::Sx, GetSize(sig_q));
1994 int offset = 0;
1995 for (auto c : sig_q.chunks()) {
1996 if (c.wire && c.wire->attributes.count(ID::init)) {
1997 Const val = c.wire->attributes.at(ID::init);
1998 for (int i = 0; i < GetSize(c); i++)
1999 initval[offset+i] = val[c.offset+i];
2000 }
2001 offset += GetSize(c);
2002 }
2003
2004 if (!initval.is_fully_undef())
2005 post_q->attributes[ID::init] = initval;
2006
2007 module->addMux(NEW_ID, sig_d, sig_adata, sig_aload, pre_d);
2008 module->addMux(NEW_ID, post_q, sig_adata, sig_aload, sig_q);
2009
2010 return module->addFf(name, pre_d, post_q);
2011 }
2012
2013 return module->addAldff(name, clock_sig, sig_aload, sig_d, sig_q, sig_adata, posedge);
2014 }
2015
2016 // ==================================================================
2017
2018 struct VerificExtNets
2019 {
2020 int portname_cnt = 0;
2021
2022 // a map from Net to the same Net one level up in the design hierarchy
2023 std::map<Net*, Net*> net_level_up_drive_up;
2024 std::map<Net*, Net*> net_level_up_drive_down;
2025
2026 Net *route_up(Net *net, bool drive_up, Net *final_net = nullptr)
2027 {
2028 auto &net_level_up = drive_up ? net_level_up_drive_up : net_level_up_drive_down;
2029
2030 if (net_level_up.count(net) == 0)
2031 {
2032 Netlist *nl = net->Owner();
2033
2034 // Simply return if Netlist is not unique
2035 log_assert(nl->NumOfRefs() == 1);
2036
2037 Instance *up_inst = (Instance*)nl->GetReferences()->GetLast();
2038 Netlist *up_nl = up_inst->Owner();
2039
2040 // create new Port
2041 string name = stringf("___extnets_%d", portname_cnt++);
2042 Port *new_port = new Port(name.c_str(), drive_up ? DIR_OUT : DIR_IN);
2043 nl->Add(new_port);
2044 nl->Buf(net)->Connect(new_port);
2045
2046 // create new Net in up Netlist
2047 Net *new_net = final_net;
2048 if (new_net == nullptr || new_net->Owner() != up_nl) {
2049 new_net = new Net(name.c_str());
2050 up_nl->Add(new_net);
2051 }
2052 up_inst->Connect(new_port, new_net);
2053
2054 net_level_up[net] = new_net;
2055 }
2056
2057 return net_level_up.at(net);
2058 }
2059
2060 Net *route_up(Net *net, bool drive_up, Netlist *dest, Net *final_net = nullptr)
2061 {
2062 while (net->Owner() != dest)
2063 net = route_up(net, drive_up, final_net);
2064 if (final_net != nullptr)
2065 log_assert(net == final_net);
2066 return net;
2067 }
2068
2069 Netlist *find_common_ancestor(Netlist *A, Netlist *B)
2070 {
2071 std::set<Netlist*> ancestors_of_A;
2072
2073 Netlist *cursor = A;
2074 while (1) {
2075 ancestors_of_A.insert(cursor);
2076 if (cursor->NumOfRefs() != 1)
2077 break;
2078 cursor = ((Instance*)cursor->GetReferences()->GetLast())->Owner();
2079 }
2080
2081 cursor = B;
2082 while (1) {
2083 if (ancestors_of_A.count(cursor))
2084 return cursor;
2085 if (cursor->NumOfRefs() != 1)
2086 break;
2087 cursor = ((Instance*)cursor->GetReferences()->GetLast())->Owner();
2088 }
2089
2090 log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A).c_str(), get_full_netlist_name(B).c_str());
2091 }
2092
2093 void run(Netlist *nl)
2094 {
2095 MapIter mi, mi2;
2096 Instance *inst;
2097 PortRef *pr;
2098
2099 vector<tuple<Instance*, Port*, Net*>> todo_connect;
2100
2101 FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
2102 run(inst->View());
2103
2104 FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
2105 FOREACH_PORTREF_OF_INST(inst, mi2, pr)
2106 {
2107 Port *port = pr->GetPort();
2108 Net *net = pr->GetNet();
2109
2110 if (!net->IsExternalTo(nl))
2111 continue;
2112
2113 if (verific_verbose)
2114 log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl).c_str(), inst->Name(), port->Name());
2115
2116 Netlist *ext_nl = net->Owner();
2117
2118 if (verific_verbose)
2119 log(" external net owner: %s\n", get_full_netlist_name(ext_nl).c_str());
2120
2121 Netlist *ca_nl = find_common_ancestor(nl, ext_nl);
2122
2123 if (verific_verbose)
2124 log(" common ancestor: %s\n", get_full_netlist_name(ca_nl).c_str());
2125
2126 Net *ca_net = route_up(net, !port->IsOutput(), ca_nl);
2127 Net *new_net = ca_net;
2128
2129 if (ca_nl != nl)
2130 {
2131 if (verific_verbose)
2132 log(" net in common ancestor: %s\n", ca_net->Name());
2133
2134 string name = stringf("___extnets_%d", portname_cnt++);
2135 new_net = new Net(name.c_str());
2136 nl->Add(new_net);
2137
2138 Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
2139 log_assert(n == ca_net);
2140 }
2141
2142 if (verific_verbose)
2143 log(" new local net: %s\n", new_net->Name());
2144
2145 log_assert(!new_net->IsExternalTo(nl));
2146 todo_connect.push_back(tuple<Instance*, Port*, Net*>(inst, port, new_net));
2147 }
2148
2149 for (auto it : todo_connect) {
2150 get<0>(it)->Disconnect(get<1>(it));
2151 get<0>(it)->Connect(get<1>(it), get<2>(it));
2152 }
2153 }
2154 };
2155
2156 void verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
2157 {
2158 verific_sva_fsm_limit = 16;
2159
2160 std::map<std::string,Netlist*> nl_todo, nl_done;
2161
2162 VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
2163 Array *netlists = NULL;
2164 Array veri_libs, vhdl_libs;
2165 #ifdef VERIFIC_VHDL_SUPPORT
2166 VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
2167 if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
2168 #endif
2169 if (veri_lib) veri_libs.InsertLast(veri_lib);
2170
2171 Map verific_params(STRING_HASH);
2172 for (const auto &i : parameters)
2173 verific_params.Insert(i.first.c_str(), i.second.c_str());
2174
2175 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
2176 InitialAssertions::Rewrite("work", &verific_params);
2177 #endif
2178
2179 if (top.empty()) {
2180 netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
2181 }
2182 else {
2183 Array veri_modules, vhdl_units;
2184
2185 if (veri_lib) {
2186 VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
2187 if (veri_module) {
2188 veri_modules.InsertLast(veri_module);
2189 }
2190
2191 // Also elaborate all root modules since they may contain bind statements
2192 MapIter mi;
2193 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
2194 if (!veri_module->IsRootModule()) continue;
2195 veri_modules.InsertLast(veri_module);
2196 }
2197 }
2198
2199 #ifdef VERIFIC_VHDL_SUPPORT
2200 if (vhdl_lib) {
2201 VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str());
2202 if (vhdl_unit)
2203 vhdl_units.InsertLast(vhdl_unit);
2204 }
2205 #endif
2206 netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
2207 }
2208
2209 Netlist *nl;
2210 int i;
2211
2212 FOREACH_ARRAY_ITEM(netlists, i, nl) {
2213 if (!top.empty() && nl->CellBaseName() != top)
2214 continue;
2215 nl->AddAtt(new Att(" \\top", NULL));
2216 nl_todo.emplace(nl->CellBaseName(), nl);
2217 }
2218
2219 delete netlists;
2220
2221 if (!verific_error_msg.empty())
2222 log_error("%s\n", verific_error_msg.c_str());
2223
2224 for (auto nl : nl_todo)
2225 nl.second->ChangePortBusStructures(1 /* hierarchical */);
2226
2227 VerificExtNets worker;
2228 for (auto nl : nl_todo)
2229 worker.run(nl.second);
2230
2231 while (!nl_todo.empty()) {
2232 auto it = nl_todo.begin();
2233 Netlist *nl = it->second;
2234 if (nl_done.count(it->first) == 0) {
2235 VerificImporter importer(false, false, false, false, false, false, false);
2236 nl_done[it->first] = it->second;
2237 importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == top);
2238 }
2239 nl_todo.erase(it);
2240 }
2241
2242 hier_tree::DeleteHierarchicalTree();
2243 veri_file::Reset();
2244 #ifdef VERIFIC_VHDL_SUPPORT
2245 vhdl_file::Reset();
2246 #endif
2247 Libset::Reset();
2248 Message::Reset();
2249 RuntimeFlags::DeleteAllFlags();
2250 LineFile::DeleteAllLineFiles();
2251 verific_incdirs.clear();
2252 verific_libdirs.clear();
2253 verific_import_pending = false;
2254
2255 if (!verific_error_msg.empty())
2256 log_error("%s\n", verific_error_msg.c_str());
2257 }
2258
2259 YOSYS_NAMESPACE_END
2260 #endif /* YOSYS_ENABLE_VERIFIC */
2261
2262 PRIVATE_NAMESPACE_BEGIN
2263
2264 #ifdef YOSYS_ENABLE_VERIFIC
2265 bool check_noverific_env()
2266 {
2267 const char *e = getenv("YOSYS_NOVERIFIC");
2268 if (e == nullptr)
2269 return false;
2270 if (atoi(e) == 0)
2271 return false;
2272 return true;
2273 }
2274 #endif
2275
2276 struct VerificPass : public Pass {
2277 VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
2278 void help() override
2279 {
2280 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2281 log("\n");
2282 log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
2283 log("\n");
2284 log("Load the specified Verilog/SystemVerilog files into Verific.\n");
2285 log("\n");
2286 log("All files specified in one call to this command are one compilation unit.\n");
2287 log("Files passed to different calls to this command are treated as belonging to\n");
2288 log("different compilation units.\n");
2289 log("\n");
2290 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
2291 log("the language version (and before file names) to set additional verilog defines.\n");
2292 log("The macros YOSYS, SYNTHESIS, and VERIFIC are defined implicitly.\n");
2293 log("\n");
2294 log("\n");
2295 log(" verific -formal <verilog-file>..\n");
2296 log("\n");
2297 log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
2298 log("\n");
2299 log("\n");
2300 #ifdef VERIFIC_VHDL_SUPPORT
2301 log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
2302 log("\n");
2303 log("Load the specified VHDL files into Verific.\n");
2304 log("\n");
2305 log("\n");
2306 #endif
2307 log(" verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal] <command-file>\n");
2308 log("\n");
2309 log("Load and execute the specified command file.\n");
2310 log("Override verilog parsing mode can be set.\n");
2311 log("The macros YOSYS, SYNTHESIS/FORMAL, and VERIFIC are defined implicitly.\n");
2312 log("\n");
2313 log("Command file parser supports following commands:\n");
2314 log(" +define - defines macro\n");
2315 log(" -u - upper case all identifier (makes Verilog parser case insensitive)\n");
2316 log(" -v - register library name (file)\n");
2317 log(" -y - register library name (directory)\n");
2318 log(" +incdir - specify include dir\n");
2319 log(" +libext - specify library extension\n");
2320 log(" +liborder - add library in ordered list\n");
2321 log(" +librescan - unresolved modules will be always searched starting with the first\n");
2322 log(" library specified by -y/-v options.\n");
2323 log(" -f/-file - nested -f option\n");
2324 log(" -F - nested -F option\n");
2325 log("\n");
2326 log(" parse mode:\n");
2327 log(" -ams\n");
2328 log(" +systemverilogext\n");
2329 log(" +v2k\n");
2330 log(" +verilog1995ext\n");
2331 log(" +verilog2001ext\n");
2332 log(" -sverilog\n");
2333 log("\n");
2334 log("\n");
2335 log(" verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
2336 log("\n");
2337 log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
2338 log("(default library when -work is not present: \"work\")\n");
2339 log("\n");
2340 log("\n");
2341 log(" verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>\n");
2342 log("\n");
2343 log("Look up external definitions in the specified library.\n");
2344 log("(-L may be used more than once)\n");
2345 log("\n");
2346 log("\n");
2347 log(" verific -vlog-incdir <directory>..\n");
2348 log("\n");
2349 log("Add Verilog include directories.\n");
2350 log("\n");
2351 log("\n");
2352 log(" verific -vlog-libdir <directory>..\n");
2353 log("\n");
2354 log("Add Verilog library directories. Verific will search in this directories to\n");
2355 log("find undefined modules.\n");
2356 log("\n");
2357 log("\n");
2358 log(" verific -vlog-define <macro>[=<value>]..\n");
2359 log("\n");
2360 log("Add Verilog defines.\n");
2361 log("\n");
2362 log("\n");
2363 log(" verific -vlog-undef <macro>..\n");
2364 log("\n");
2365 log("Remove Verilog defines previously set with -vlog-define.\n");
2366 log("\n");
2367 log("\n");
2368 log(" verific -set-error <msg_id>..\n");
2369 log(" verific -set-warning <msg_id>..\n");
2370 log(" verific -set-info <msg_id>..\n");
2371 log(" verific -set-ignore <msg_id>..\n");
2372 log("\n");
2373 log("Set message severity. <msg_id> is the string in square brackets when a message\n");
2374 log("is printed, such as VERI-1209.\n");
2375 log("\n");
2376 log("\n");
2377 log(" verific -import [options] <top-module>..\n");
2378 log("\n");
2379 log("Elaborate the design for the specified top modules, import to Yosys and\n");
2380 log("reset the internal state of Verific.\n");
2381 log("\n");
2382 log("Import options:\n");
2383 log("\n");
2384 log(" -all\n");
2385 log(" Elaborate all modules, not just the hierarchy below the given top\n");
2386 log(" modules. With this option the list of modules to import is optional.\n");
2387 log("\n");
2388 log(" -gates\n");
2389 log(" Create a gate-level netlist.\n");
2390 log("\n");
2391 log(" -flatten\n");
2392 log(" Flatten the design in Verific before importing.\n");
2393 log("\n");
2394 log(" -extnets\n");
2395 log(" Resolve references to external nets by adding module ports as needed.\n");
2396 log("\n");
2397 log(" -autocover\n");
2398 log(" Generate automatic cover statements for all asserts\n");
2399 log("\n");
2400 log(" -fullinit\n");
2401 log(" Keep all register initializations, even those for non-FF registers.\n");
2402 log("\n");
2403 log(" -chparam name value \n");
2404 log(" Elaborate the specified top modules (all modules when -all given) using\n");
2405 log(" this parameter value. Modules on which this parameter does not exist will\n");
2406 log(" cause Verific to produce a VERI-1928 or VHDL-1676 message. This option\n");
2407 log(" can be specified multiple times to override multiple parameters.\n");
2408 log(" String values must be passed in double quotes (\").\n");
2409 log("\n");
2410 log(" -v, -vv\n");
2411 log(" Verbose log messages. (-vv is even more verbose than -v.)\n");
2412 log("\n");
2413 log("The following additional import options are useful for debugging the Verific\n");
2414 log("bindings (for Yosys and/or Verific developers):\n");
2415 log("\n");
2416 log(" -k\n");
2417 log(" Keep going after an unsupported verific primitive is found. The\n");
2418 log(" unsupported primitive is added as blockbox module to the design.\n");
2419 log(" This will also add all SVA related cells to the design parallel to\n");
2420 log(" the checker logic inferred by it.\n");
2421 log("\n");
2422 log(" -V\n");
2423 log(" Import Verific netlist as-is without translating to Yosys cell types. \n");
2424 log("\n");
2425 log(" -nosva\n");
2426 log(" Ignore SVA properties, do not infer checker logic.\n");
2427 log("\n");
2428 log(" -L <int>\n");
2429 log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
2430 log("\n");
2431 log(" -n\n");
2432 log(" Keep all Verific names on instances and nets. By default only\n");
2433 log(" user-declared names are preserved.\n");
2434 log("\n");
2435 log(" -d <dump_file>\n");
2436 log(" Dump the Verific netlist as a verilog file.\n");
2437 log("\n");
2438 log("\n");
2439 log(" verific [-work <libname>] -pp [options] <filename> [<module>]..\n");
2440 log("\n");
2441 log("Pretty print design (or just module) to the specified file from the\n");
2442 log("specified library. (default library when -work is not present: \"work\")\n");
2443 log("\n");
2444 log("Pretty print options:\n");
2445 log("\n");
2446 log(" -verilog\n");
2447 log(" Save output for Verilog/SystemVerilog design modules (default).\n");
2448 log("\n");
2449 log(" -vhdl\n");
2450 log(" Save output for VHDL design units.\n");
2451 log("\n");
2452 log("\n");
2453 log(" verific -app <application>..\n");
2454 log("\n");
2455 log("Execute YosysHQ formal application on loaded Verilog files.\n");
2456 log("\n");
2457 log("Application options:\n");
2458 log("\n");
2459 log(" -module <module>\n");
2460 log(" Run formal application only on specified module.\n");
2461 log("\n");
2462 log(" -blacklist <filename[:lineno]>\n");
2463 log(" Do not run application on modules from files that match the filename\n");
2464 log(" or filename and line number if provided in such format.\n");
2465 log(" Parameter can also contain comma separated list of file locations.\n");
2466 log("\n");
2467 log(" -blfile <file>\n");
2468 log(" Do not run application on locations specified in file, they can represent filename\n");
2469 log(" or filename and location in file.\n");
2470 log("\n");
2471 log("Applications:\n");
2472 log("\n");
2473 #if defined(YOSYS_ENABLE_VERIFIC) && defined(YOSYSHQ_VERIFIC_FORMALAPPS)
2474 VerificFormalApplications vfa;
2475 log("%s\n",vfa.GetHelp().c_str());
2476 #else
2477 log(" WARNING: Applications only available in commercial build.\n");
2478
2479 #endif
2480 log("\n");
2481 log("\n");
2482 log(" verific -template <name> <top_module>..\n");
2483 log("\n");
2484 log("Generate template for specified top module of loaded design.\n");
2485 log("\n");
2486 log("Template options:\n");
2487 log("\n");
2488 log(" -out\n");
2489 log(" Specifies output file for generated template, by default output is stdout\n");
2490 log("\n");
2491 log(" -chparam name value \n");
2492 log(" Generate template using this parameter value. Otherwise default parameter\n");
2493 log(" values will be used for templat generate functionality. This option\n");
2494 log(" can be specified multiple times to override multiple parameters.\n");
2495 log(" String values must be passed in double quotes (\").\n");
2496 log("\n");
2497 log("Templates:\n");
2498 log("\n");
2499 #if defined(YOSYS_ENABLE_VERIFIC) && defined(YOSYSHQ_VERIFIC_TEMPLATES)
2500 VerificTemplateGenerator vfg;
2501 log("%s\n",vfg.GetHelp().c_str());
2502 #else
2503 log(" WARNING: Templates only available in commercial build.\n");
2504 log("\n");
2505 #endif
2506 log("\n");
2507 log("\n");
2508 log(" verific -cfg [<name> [<value>]]\n");
2509 log("\n");
2510 log("Get/set Verific runtime flags.\n");
2511 log("\n");
2512 log("\n");
2513 log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n");
2514 log("https://www.yosyshq.com/\n");
2515 log("\n");
2516 log("Contact office@yosyshq.com for free evaluation\n");
2517 log("binaries of YosysHQ Tabby CAD Suite.\n");
2518 log("\n");
2519 }
2520 #ifdef YOSYS_ENABLE_VERIFIC
2521 void execute(std::vector<std::string> args, RTLIL::Design *design) override
2522 {
2523 static bool set_verific_global_flags = true;
2524
2525 if (check_noverific_env())
2526 log_cmd_error("This version of Yosys is built without Verific support.\n"
2527 "\n"
2528 "Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"
2529 "https://www.yosyshq.com/\n"
2530 "\n"
2531 "Contact office@yosyshq.com for free evaluation\n"
2532 "binaries of YosysHQ Tabby CAD Suite.\n");
2533
2534 log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
2535
2536 if (set_verific_global_flags)
2537 {
2538 Message::SetConsoleOutput(0);
2539 Message::RegisterCallBackMsg(msg_func);
2540
2541 RuntimeFlags::SetVar("db_preserve_user_instances", 1);
2542 RuntimeFlags::SetVar("db_preserve_user_nets", 1);
2543 RuntimeFlags::SetVar("db_preserve_x", 1);
2544
2545 RuntimeFlags::SetVar("db_allow_external_nets", 1);
2546 RuntimeFlags::SetVar("db_infer_wide_operators", 1);
2547 RuntimeFlags::SetVar("db_infer_set_reset_registers", 0);
2548
2549 RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
2550 RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
2551 RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
2552
2553 #ifdef VERIFIC_VHDL_SUPPORT
2554 RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
2555 RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
2556
2557 RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
2558 RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
2559
2560 RuntimeFlags::SetVar("vhdl_preserve_assignments", 1);
2561 //RuntimeFlags::SetVar("vhdl_preserve_comments", 1);
2562 RuntimeFlags::SetVar("vhdl_preserve_drivers", 1);
2563 #endif
2564 RuntimeFlags::SetVar("veri_preserve_assignments", 1);
2565 RuntimeFlags::SetVar("veri_preserve_comments", 1);
2566 RuntimeFlags::SetVar("veri_preserve_drivers", 1);
2567
2568 // Workaround for VIPER #13851
2569 RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
2570
2571 // WARNING: instantiating unknown module 'XYZ' (VERI-1063)
2572 Message::SetMessageType("VERI-1063", VERIFIC_ERROR);
2573
2574 // https://github.com/YosysHQ/yosys/issues/1055
2575 RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
2576
2577 RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1);
2578
2579 #ifndef DB_PRESERVE_INITIAL_VALUE
2580 # warning Verific was built without DB_PRESERVE_INITIAL_VALUE.
2581 #endif
2582
2583 set_verific_global_flags = false;
2584 }
2585
2586 verific_verbose = 0;
2587 verific_sva_fsm_limit = 16;
2588
2589 const char *release_str = Message::ReleaseString();
2590 time_t release_time = Message::ReleaseDate();
2591 char *release_tmstr = ctime(&release_time);
2592
2593 if (release_str == nullptr)
2594 release_str = "(no release string)";
2595
2596 for (char *p = release_tmstr; *p; p++)
2597 if (*p == '\n') *p = 0;
2598
2599 log("Built with Verific %s, released at %s.\n", release_str, release_tmstr);
2600
2601 int argidx = 1;
2602 std::string work = "work";
2603
2604 if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" ||
2605 args[argidx] == "-set-info" || args[argidx] == "-set-ignore"))
2606 {
2607 msg_type_t new_type;
2608
2609 if (args[argidx] == "-set-error")
2610 new_type = VERIFIC_ERROR;
2611 else if (args[argidx] == "-set-warning")
2612 new_type = VERIFIC_WARNING;
2613 else if (args[argidx] == "-set-info")
2614 new_type = VERIFIC_INFO;
2615 else if (args[argidx] == "-set-ignore")
2616 new_type = VERIFIC_IGNORE;
2617 else
2618 log_abort();
2619
2620 for (argidx++; argidx < GetSize(args); argidx++)
2621 Message::SetMessageType(args[argidx].c_str(), new_type);
2622
2623 goto check_error;
2624 }
2625
2626 if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") {
2627 for (argidx++; argidx < GetSize(args); argidx++)
2628 verific_incdirs.push_back(args[argidx]);
2629 goto check_error;
2630 }
2631
2632 if (GetSize(args) > argidx && args[argidx] == "-vlog-libdir") {
2633 for (argidx++; argidx < GetSize(args); argidx++)
2634 verific_libdirs.push_back(args[argidx]);
2635 goto check_error;
2636 }
2637
2638 if (GetSize(args) > argidx && args[argidx] == "-vlog-define") {
2639 for (argidx++; argidx < GetSize(args); argidx++) {
2640 string name = args[argidx];
2641 size_t equal = name.find('=');
2642 if (equal != std::string::npos) {
2643 string value = name.substr(equal+1);
2644 name = name.substr(0, equal);
2645 veri_file::DefineCmdLineMacro(name.c_str(), value.c_str());
2646 } else {
2647 veri_file::DefineCmdLineMacro(name.c_str());
2648 }
2649 }
2650 goto check_error;
2651 }
2652
2653 if (GetSize(args) > argidx && args[argidx] == "-vlog-undef") {
2654 for (argidx++; argidx < GetSize(args); argidx++) {
2655 string name = args[argidx];
2656 veri_file::UndefineMacro(name.c_str());
2657 }
2658 goto check_error;
2659 }
2660
2661 veri_file::RemoveAllLOptions();
2662 for (; argidx < GetSize(args); argidx++)
2663 {
2664 if (args[argidx] == "-work" && argidx+1 < GetSize(args)) {
2665 work = args[++argidx];
2666 continue;
2667 }
2668 if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
2669 veri_file::AddLOption(args[++argidx].c_str());
2670 continue;
2671 }
2672 break;
2673 }
2674
2675 if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
2676 {
2677 unsigned verilog_mode = veri_file::VERILOG_95; // default recommended by Verific
2678 bool is_formal = false;
2679 const char* filename = nullptr;
2680
2681 Verific::veri_file::f_file_flags flags = (args[argidx] == "-f") ? veri_file::F_FILE_NONE : veri_file::F_FILE_CAPITAL;
2682
2683 for (argidx++; argidx < GetSize(args); argidx++) {
2684 if (args[argidx] == "-vlog95") {
2685 verilog_mode = veri_file::VERILOG_95;
2686 continue;
2687 } else if (args[argidx] == "-vlog2k") {
2688 verilog_mode = veri_file::VERILOG_2K;
2689 continue;
2690 } else if (args[argidx] == "-sv2005") {
2691 verilog_mode = veri_file::SYSTEM_VERILOG_2005;
2692 continue;
2693 } else if (args[argidx] == "-sv2009") {
2694 verilog_mode = veri_file::SYSTEM_VERILOG_2009;
2695 continue;
2696 } else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") {
2697 verilog_mode = veri_file::SYSTEM_VERILOG;
2698 if (args[argidx] == "-formal") is_formal = true;
2699 continue;
2700 } else if (args[argidx].compare(0, 1, "-") == 0) {
2701 cmd_error(args, argidx, "unknown option");
2702 goto check_error;
2703 }
2704
2705 if (!filename) {
2706 filename = args[argidx].c_str();
2707 continue;
2708 } else {
2709 log_cmd_error("Only one filename can be specified.\n");
2710 }
2711 }
2712 if (!filename)
2713 log_cmd_error("Filname must be specified.\n");
2714
2715 unsigned analysis_mode = verilog_mode; // keep default as provided by user if not defined in file
2716 Array *file_names = veri_file::ProcessFFile(filename, flags, analysis_mode);
2717 if (analysis_mode != verilog_mode)
2718 log_warning("Provided verilog mode differs from one specified in file.\n");
2719
2720 veri_file::DefineMacro("YOSYS");
2721 veri_file::DefineMacro("VERIFIC");
2722 veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS");
2723
2724 if (!veri_file::AnalyzeMultipleFiles(file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
2725 verific_error_msg.clear();
2726 log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
2727 }
2728
2729 delete file_names;
2730 verific_import_pending = true;
2731 goto check_error;
2732 }
2733
2734 if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
2735 args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))
2736 {
2737 Array file_names;
2738 unsigned verilog_mode;
2739
2740 if (args[argidx] == "-vlog95")
2741 verilog_mode = veri_file::VERILOG_95;
2742 else if (args[argidx] == "-vlog2k")
2743 verilog_mode = veri_file::VERILOG_2K;
2744 else if (args[argidx] == "-sv2005")
2745 verilog_mode = veri_file::SYSTEM_VERILOG_2005;
2746 else if (args[argidx] == "-sv2009")
2747 verilog_mode = veri_file::SYSTEM_VERILOG_2009;
2748 else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal")
2749 verilog_mode = veri_file::SYSTEM_VERILOG;
2750 else
2751 log_abort();
2752
2753 veri_file::DefineMacro("YOSYS");
2754 veri_file::DefineMacro("VERIFIC");
2755 veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS");
2756
2757 for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].compare(0, 2, "-D") == 0; argidx++) {
2758 std::string name = args[argidx].substr(2);
2759 if (args[argidx] == "-D") {
2760 if (++argidx >= GetSize(args))
2761 break;
2762 name = args[argidx];
2763 }
2764 size_t equal = name.find('=');
2765 if (equal != std::string::npos) {
2766 string value = name.substr(equal+1);
2767 name = name.substr(0, equal);
2768 veri_file::DefineMacro(name.c_str(), value.c_str());
2769 } else {
2770 veri_file::DefineMacro(name.c_str());
2771 }
2772 }
2773
2774 for (auto &dir : verific_incdirs)
2775 veri_file::AddIncludeDir(dir.c_str());
2776 for (auto &dir : verific_libdirs)
2777 veri_file::AddYDir(dir.c_str());
2778
2779 while (argidx < GetSize(args))
2780 file_names.Insert(args[argidx++].c_str());
2781
2782 if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
2783 verific_error_msg.clear();
2784 log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
2785 }
2786
2787 verific_import_pending = true;
2788 goto check_error;
2789 }
2790
2791 #ifdef VERIFIC_VHDL_SUPPORT
2792 if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
2793 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
2794 for (argidx++; argidx < GetSize(args); argidx++)
2795 if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_87))
2796 log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
2797 verific_import_pending = true;
2798 goto check_error;
2799 }
2800
2801 if (GetSize(args) > argidx && args[argidx] == "-vhdl93") {
2802 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2803 for (argidx++; argidx < GetSize(args); argidx++)
2804 if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_93))
2805 log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
2806 verific_import_pending = true;
2807 goto check_error;
2808 }
2809
2810 if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") {
2811 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2812 for (argidx++; argidx < GetSize(args); argidx++)
2813 if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2K))
2814 log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
2815 verific_import_pending = true;
2816 goto check_error;
2817 }
2818
2819 if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
2820 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
2821 for (argidx++; argidx < GetSize(args); argidx++)
2822 if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2008))
2823 log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
2824 verific_import_pending = true;
2825 goto check_error;
2826 }
2827 #endif
2828
2829 #ifdef YOSYSHQ_VERIFIC_FORMALAPPS
2830 if (argidx < GetSize(args) && args[argidx] == "-app")
2831 {
2832 if (!(argidx+1 < GetSize(args)))
2833 cmd_error(args, argidx, "No formal application specified.\n");
2834
2835 VerificFormalApplications vfa;
2836 auto apps = vfa.GetApps();
2837 std::string app = args[++argidx];
2838 std::vector<std::string> blacklists;
2839 if (apps.find(app) == apps.end())
2840 log_cmd_error("Application '%s' does not exist.\n", app.c_str());
2841
2842 FormalApplication *application = apps[app];
2843 application->setLogger([](std::string msg) { log("%s",msg.c_str()); } );
2844 VeriModule *selected_module = nullptr;
2845
2846 for (argidx++; argidx < GetSize(args); argidx++) {
2847 std::string error;
2848 if (application->checkParams(args, argidx, error)) {
2849 if (!error.empty())
2850 cmd_error(args, argidx, error);
2851 continue;
2852 }
2853
2854 if (args[argidx] == "-module" && argidx < GetSize(args)) {
2855 if (!(argidx+1 < GetSize(args)))
2856 cmd_error(args, argidx+1, "No module name specified.\n");
2857 std::string module = args[++argidx];
2858 VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
2859 selected_module = veri_lib ? veri_lib->GetModule(module.c_str(), 1) : nullptr;
2860 if (!selected_module) {
2861 log_error("Can't find module '%s'.\n", module.c_str());
2862 }
2863 continue;
2864 }
2865 if (args[argidx] == "-blacklist" && argidx < GetSize(args)) {
2866 if (!(argidx+1 < GetSize(args)))
2867 cmd_error(args, argidx+1, "No blacklist specified.\n");
2868
2869 std::string line = args[++argidx];
2870 std::string p;
2871 while (!(p = next_token(line, ",\t\r\n ")).empty())
2872 blacklists.push_back(p);
2873 continue;
2874 }
2875 if (args[argidx] == "-blfile" && argidx < GetSize(args)) {
2876 if (!(argidx+1 < GetSize(args)))
2877 cmd_error(args, argidx+1, "No blacklist file specified.\n");
2878 std::string fn = args[++argidx];
2879 std::ifstream f(fn);
2880 if (f.fail())
2881 log_cmd_error("Can't open blacklist file '%s'!\n", fn.c_str());
2882
2883 std::string line,p;
2884 while (std::getline(f, line)) {
2885 while (!(p = next_token(line, ",\t\r\n ")).empty())
2886 blacklists.push_back(p);
2887 }
2888 continue;
2889 }
2890 break;
2891 }
2892 if (argidx < GetSize(args))
2893 cmd_error(args, argidx, "unknown option/parameter");
2894
2895 application->setBlacklists(&blacklists);
2896 application->setSingleModuleMode(selected_module!=nullptr);
2897
2898 const char *err = application->validate();
2899 if (err)
2900 cmd_error(args, argidx, err);
2901
2902 MapIter mi;
2903 VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
2904 log("Running formal application '%s'.\n", app.c_str());
2905
2906 if (selected_module) {
2907 std::string out;
2908 if (!application->execute(selected_module, out))
2909 log_error("%s", out.c_str());
2910 }
2911 else {
2912 VeriModule *module ;
2913 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, module) {
2914 std::string out;
2915 if (!application->execute(module, out)) {
2916 log_error("%s", out.c_str());
2917 break;
2918 }
2919 }
2920 }
2921 goto check_error;
2922 }
2923 #endif
2924 if (argidx < GetSize(args) && args[argidx] == "-pp")
2925 {
2926 const char* filename = nullptr;
2927 const char* module = nullptr;
2928 bool mode_vhdl = false;
2929 for (argidx++; argidx < GetSize(args); argidx++) {
2930 #ifdef VERIFIC_VHDL_SUPPORT
2931 if (args[argidx] == "-vhdl") {
2932 mode_vhdl = true;
2933 continue;
2934 }
2935 #endif
2936 if (args[argidx] == "-verilog") {
2937 mode_vhdl = false;
2938 continue;
2939 }
2940
2941 if (args[argidx].compare(0, 1, "-") == 0) {
2942 cmd_error(args, argidx, "unknown option");
2943 goto check_error;
2944 }
2945
2946 if (!filename) {
2947 filename = args[argidx].c_str();
2948 continue;
2949 }
2950 if (module)
2951 log_cmd_error("Only one module can be specified.\n");
2952 module = args[argidx].c_str();
2953 }
2954
2955 if (argidx < GetSize(args))
2956 cmd_error(args, argidx, "unknown option/parameter");
2957
2958 if (!filename)
2959 log_cmd_error("Filname must be specified.\n");
2960
2961 if (mode_vhdl)
2962 #ifdef VERIFIC_VHDL_SUPPORT
2963 vhdl_file::PrettyPrint(filename, module, work.c_str());
2964 #else
2965 goto check_error;
2966 #endif
2967 else
2968 veri_file::PrettyPrint(filename, module, work.c_str());
2969 goto check_error;
2970 }
2971
2972 #ifdef YOSYSHQ_VERIFIC_TEMPLATES
2973 if (argidx < GetSize(args) && args[argidx] == "-template")
2974 {
2975 if (!(argidx+1 < GetSize(args)))
2976 cmd_error(args, argidx+1, "No template type specified.\n");
2977
2978 VerificTemplateGenerator vfg;
2979 auto gens = vfg.GetGenerators();
2980 std::string app = args[++argidx];
2981 if (gens.find(app) == gens.end())
2982 log_cmd_error("Template generator '%s' does not exist.\n", app.c_str());
2983 TemplateGenerator *generator = gens[app];
2984 if (!(argidx+1 < GetSize(args)))
2985 cmd_error(args, argidx+1, "No top module specified.\n");
2986 generator->setLogger([](std::string msg) { log("%s",msg.c_str()); } );
2987
2988 std::string module = args[++argidx];
2989 VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
2990 VeriModule *veri_module = veri_lib ? veri_lib->GetModule(module.c_str(), 1) : nullptr;
2991 if (!veri_module) {
2992 log_error("Can't find module/unit '%s'.\n", module.c_str());
2993 }
2994
2995 log("Template '%s' is running for module '%s'.\n", app.c_str(),module.c_str());
2996
2997 Map parameters(STRING_HASH);
2998 const char *out_filename = nullptr;
2999
3000 for (argidx++; argidx < GetSize(args); argidx++) {
3001 std::string error;
3002 if (generator->checkParams(args, argidx, error)) {
3003 if (!error.empty())
3004 cmd_error(args, argidx, error);
3005 continue;
3006 }
3007
3008 if (args[argidx] == "-chparam" && argidx < GetSize(args)) {
3009 if (!(argidx+1 < GetSize(args)))
3010 cmd_error(args, argidx+1, "No param name specified.\n");
3011 if (!(argidx+2 < GetSize(args)))
3012 cmd_error(args, argidx+2, "No param value specified.\n");
3013
3014 const std::string &key = args[++argidx];
3015 const std::string &value = args[++argidx];
3016 unsigned new_insertion = parameters.Insert(key.c_str(), value.c_str(),
3017 1 /* force_overwrite */);
3018 if (!new_insertion)
3019 log_warning_noprefix("-chparam %s already specified: overwriting.\n", key.c_str());
3020 continue;
3021 }
3022
3023 if (args[argidx] == "-out" && argidx < GetSize(args)) {
3024 if (!(argidx+1 < GetSize(args)))
3025 cmd_error(args, argidx+1, "No output file specified.\n");
3026 out_filename = args[++argidx].c_str();
3027 continue;
3028 }
3029
3030 break;
3031 }
3032 if (argidx < GetSize(args))
3033 cmd_error(args, argidx, "unknown option/parameter");
3034
3035 const char *err = generator->validate();
3036 if (err)
3037 cmd_error(args, argidx, err);
3038
3039 std::string val;
3040 if (!generator->generate(veri_module, val, &parameters))
3041 log_error("%s", val.c_str());
3042
3043 FILE *of = stdout;
3044 if (out_filename) {
3045 of = fopen(out_filename, "w");
3046 if (of == nullptr)
3047 log_error("Can't open '%s' for writing: %s\n", out_filename, strerror(errno));
3048 log("Writing output to '%s'\n",out_filename);
3049 }
3050 fprintf(of, "%s\n",val.c_str());
3051 fflush(of);
3052 if (of!=stdout)
3053 fclose(of);
3054 goto check_error;
3055 }
3056 #endif
3057 if (GetSize(args) > argidx && args[argidx] == "-import")
3058 {
3059 std::map<std::string,Netlist*> nl_todo, nl_done;
3060 bool mode_all = false, mode_gates = false, mode_keep = false;
3061 bool mode_nosva = false, mode_names = false, mode_verific = false;
3062 bool mode_autocover = false, mode_fullinit = false;
3063 bool flatten = false, extnets = false;
3064 string dumpfile;
3065 Map parameters(STRING_HASH);
3066
3067 for (argidx++; argidx < GetSize(args); argidx++) {
3068 if (args[argidx] == "-all") {
3069 mode_all = true;
3070 continue;
3071 }
3072 if (args[argidx] == "-gates") {
3073 mode_gates = true;
3074 continue;
3075 }
3076 if (args[argidx] == "-flatten") {
3077 flatten = true;
3078 continue;
3079 }
3080 if (args[argidx] == "-extnets") {
3081 extnets = true;
3082 continue;
3083 }
3084 if (args[argidx] == "-k") {
3085 mode_keep = true;
3086 continue;
3087 }
3088 if (args[argidx] == "-nosva") {
3089 mode_nosva = true;
3090 continue;
3091 }
3092 if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
3093 verific_sva_fsm_limit = atoi(args[++argidx].c_str());
3094 continue;
3095 }
3096 if (args[argidx] == "-n") {
3097 mode_names = true;
3098 continue;
3099 }
3100 if (args[argidx] == "-autocover") {
3101 mode_autocover = true;
3102 continue;
3103 }
3104 if (args[argidx] == "-fullinit") {
3105 mode_fullinit = true;
3106 continue;
3107 }
3108 if (args[argidx] == "-chparam" && argidx+2 < GetSize(args)) {
3109 const std::string &key = args[++argidx];
3110 const std::string &value = args[++argidx];
3111 unsigned new_insertion = parameters.Insert(key.c_str(), value.c_str(),
3112 1 /* force_overwrite */);
3113 if (!new_insertion)
3114 log_warning_noprefix("-chparam %s already specified: overwriting.\n", key.c_str());
3115 continue;
3116 }
3117 if (args[argidx] == "-V") {
3118 mode_verific = true;
3119 continue;
3120 }
3121 if (args[argidx] == "-v") {
3122 verific_verbose = 1;
3123 continue;
3124 }
3125 if (args[argidx] == "-vv") {
3126 verific_verbose = 2;
3127 continue;
3128 }
3129 if (args[argidx] == "-d" && argidx+1 < GetSize(args)) {
3130 dumpfile = args[++argidx];
3131 continue;
3132 }
3133 break;
3134 }
3135
3136 if (argidx > GetSize(args) && args[argidx].compare(0, 1, "-") == 0)
3137 cmd_error(args, argidx, "unknown option");
3138
3139 std::set<std::string> top_mod_names;
3140
3141 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
3142 InitialAssertions::Rewrite(work, &parameters);
3143 #endif
3144 if (mode_all)
3145 {
3146 log("Running hier_tree::ElaborateAll().\n");
3147
3148 VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
3149
3150 Array veri_libs, vhdl_libs;
3151 #ifdef VERIFIC_VHDL_SUPPORT
3152 VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
3153 if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
3154 #endif
3155 if (veri_lib) veri_libs.InsertLast(veri_lib);
3156
3157 Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &parameters);
3158 Netlist *nl;
3159 int i;
3160
3161 FOREACH_ARRAY_ITEM(netlists, i, nl)
3162 nl_todo.emplace(nl->CellBaseName(), nl);
3163 delete netlists;
3164 }
3165 else
3166 {
3167 if (argidx == GetSize(args))
3168 cmd_error(args, argidx, "No top module specified.\n");
3169
3170 VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
3171 #ifdef VERIFIC_VHDL_SUPPORT
3172 VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
3173 #endif
3174
3175 Array veri_modules, vhdl_units;
3176 for (; argidx < GetSize(args); argidx++)
3177 {
3178 const char *name = args[argidx].c_str();
3179 top_mod_names.insert(name);
3180
3181 VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
3182 if (veri_module) {
3183 log("Adding Verilog module '%s' to elaboration queue.\n", name);
3184 veri_modules.InsertLast(veri_module);
3185 continue;
3186 }
3187 #ifdef VERIFIC_VHDL_SUPPORT
3188 VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr;
3189 if (vhdl_unit) {
3190 log("Adding VHDL unit '%s' to elaboration queue.\n", name);
3191 vhdl_units.InsertLast(vhdl_unit);
3192 continue;
3193 }
3194 #endif
3195 log_error("Can't find module/unit '%s'.\n", name);
3196 }
3197
3198 if (veri_lib) {
3199 // Also elaborate all root modules since they may contain bind statements
3200 MapIter mi;
3201 VeriModule *veri_module;
3202 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
3203 if (!veri_module->IsRootModule()) continue;
3204 veri_modules.InsertLast(veri_module);
3205 }
3206 }
3207
3208 log("Running hier_tree::Elaborate().\n");
3209 Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
3210 Netlist *nl;
3211 int i;
3212
3213 FOREACH_ARRAY_ITEM(netlists, i, nl) {
3214 if (!top_mod_names.count(nl->CellBaseName()))
3215 continue;
3216 nl->AddAtt(new Att(" \\top", NULL));
3217 nl_todo.emplace(nl->CellBaseName(), nl);
3218 }
3219 delete netlists;
3220 }
3221
3222 if (!verific_error_msg.empty())
3223 goto check_error;
3224
3225 if (flatten) {
3226 for (auto nl : nl_todo)
3227 nl.second->Flatten();
3228 }
3229
3230 if (extnets) {
3231 VerificExtNets worker;
3232 for (auto nl : nl_todo)
3233 worker.run(nl.second);
3234 }
3235
3236 for (auto nl : nl_todo)
3237 nl.second->ChangePortBusStructures(1 /* hierarchical */);
3238
3239 if (!dumpfile.empty()) {
3240 VeriWrite veri_writer;
3241 veri_writer.WriteFile(dumpfile.c_str(), Netlist::PresentDesign());
3242 }
3243
3244 while (!nl_todo.empty()) {
3245 auto it = nl_todo.begin();
3246 Netlist *nl = it->second;
3247 if (nl_done.count(it->first) == 0) {
3248 VerificImporter importer(mode_gates, mode_keep, mode_nosva,
3249 mode_names, mode_verific, mode_autocover, mode_fullinit);
3250 nl_done[it->first] = it->second;
3251 importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->Owner()->Name()));
3252 }
3253 nl_todo.erase(it);
3254 }
3255
3256 hier_tree::DeleteHierarchicalTree();
3257 veri_file::Reset();
3258 #ifdef VERIFIC_VHDL_SUPPORT
3259 vhdl_file::Reset();
3260 #endif
3261 Libset::Reset();
3262 Message::Reset();
3263 RuntimeFlags::DeleteAllFlags();
3264 LineFile::DeleteAllLineFiles();
3265 verific_incdirs.clear();
3266 verific_libdirs.clear();
3267 verific_import_pending = false;
3268 goto check_error;
3269 }
3270
3271 if (argidx < GetSize(args) && args[argidx] == "-cfg")
3272 {
3273 if (argidx+1 == GetSize(args)) {
3274 MapIter mi;
3275 const char *k, *s;
3276 unsigned long v;
3277 pool<std::string> lines;
3278 FOREACH_MAP_ITEM(RuntimeFlags::GetVarMap(), mi, &k, &v) {
3279 lines.insert(stringf("%s %lu", k, v));
3280 }
3281 FOREACH_MAP_ITEM(RuntimeFlags::GetStringVarMap(), mi, &k, &s) {
3282 if (s == nullptr)
3283 lines.insert(stringf("%s NULL", k));
3284 else
3285 lines.insert(stringf("%s \"%s\"", k, s));
3286 }
3287 lines.sort();
3288 for (auto &line : lines)
3289 log("verific -cfg %s\n", line.c_str());
3290 goto check_error;
3291 }
3292
3293 if (argidx+2 == GetSize(args)) {
3294 const char *k = args[argidx+1].c_str();
3295 if (RuntimeFlags::HasUnsignedVar(k)) {
3296 log("verific -cfg %s %lu\n", k, RuntimeFlags::GetVar(k));
3297 goto check_error;
3298 }
3299 if (RuntimeFlags::HasStringVar(k)) {
3300 const char *s = RuntimeFlags::GetStringVar(k);
3301 if (s == nullptr)
3302 log("verific -cfg %s NULL\n", k);
3303 else
3304 log("verific -cfg %s \"%s\"\n", k, s);
3305 goto check_error;
3306 }
3307 log_cmd_error("Can't find Verific Runtime flag '%s'.\n", k);
3308 }
3309
3310 if (argidx+3 == GetSize(args)) {
3311 const auto &k = args[argidx+1], &v = args[argidx+2];
3312 if (v == "NULL") {
3313 RuntimeFlags::SetStringVar(k.c_str(), nullptr);
3314 goto check_error;
3315 }
3316 if (v[0] == '"') {
3317 std::string s = v.substr(1, GetSize(v)-2);
3318 RuntimeFlags::SetStringVar(k.c_str(), v.c_str());
3319 goto check_error;
3320 }
3321 char *endptr;
3322 unsigned long n = strtol(v.c_str(), &endptr, 0);
3323 if (*endptr == 0) {
3324 RuntimeFlags::SetVar(k.c_str(), n);
3325 goto check_error;
3326 }
3327 }
3328 }
3329
3330 cmd_error(args, argidx, "Missing or unsupported mode parameter.\n");
3331
3332 check_error:
3333 if (!verific_error_msg.empty())
3334 log_error("%s\n", verific_error_msg.c_str());
3335
3336 }
3337 #else /* YOSYS_ENABLE_VERIFIC */
3338 void execute(std::vector<std::string>, RTLIL::Design *) override {
3339 log_cmd_error("This version of Yosys is built without Verific support.\n"
3340 "\n"
3341 "Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"
3342 "https://www.yosyshq.com/\n"
3343 "\n"
3344 "Contact office@yosyshq.com for free evaluation\n"
3345 "binaries of YosysHQ Tabby CAD Suite.\n");
3346 }
3347 #endif
3348 } VerificPass;
3349
3350 struct ReadPass : public Pass {
3351 ReadPass() : Pass("read", "load HDL designs") { }
3352 void help() override
3353 {
3354 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
3355 log("\n");
3356 log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..\n");
3357 log("\n");
3358 log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n");
3359 log("is only available via Verific.)\n");
3360 log("\n");
3361 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
3362 log("the language version (and before file names) to set additional verilog defines.\n");
3363 log("\n");
3364 log("\n");
3365 #ifdef VERIFIC_VHDL_SUPPORT
3366 log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
3367 log("\n");
3368 log("Load the specified VHDL files. (Requires Verific.)\n");
3369 log("\n");
3370 log("\n");
3371 #endif
3372 log(" read {-f|-F} <command-file>\n");
3373 log("\n");
3374 log("Load and execute the specified command file. (Requires Verific.)\n");
3375 log("Check verific command for more information about supported commands in file.\n");
3376 log("\n");
3377 log("\n");
3378 log(" read -define <macro>[=<value>]..\n");
3379 log("\n");
3380 log("Set global Verilog/SystemVerilog defines.\n");
3381 log("\n");
3382 log("\n");
3383 log(" read -undef <macro>..\n");
3384 log("\n");
3385 log("Unset global Verilog/SystemVerilog defines.\n");
3386 log("\n");
3387 log("\n");
3388 log(" read -incdir <directory>\n");
3389 log("\n");
3390 log("Add directory to global Verilog/SystemVerilog include directories.\n");
3391 log("\n");
3392 log("\n");
3393 log(" read -verific\n");
3394 log(" read -noverific\n");
3395 log("\n");
3396 log("Subsequent calls to 'read' will either use or not use Verific. Calling 'read'\n");
3397 log("with -verific will result in an error on Yosys binaries that are built without\n");
3398 log("Verific support. The default is to use Verific if it is available.\n");
3399 log("\n");
3400 }
3401 void execute(std::vector<std::string> args, RTLIL::Design *design) override
3402 {
3403 #ifdef YOSYS_ENABLE_VERIFIC
3404 static bool verific_available = !check_noverific_env();
3405 #else
3406 static bool verific_available = false;
3407 #endif
3408 static bool use_verific = verific_available;
3409
3410 if (args.size() < 2 || args[1][0] != '-')
3411 cmd_error(args, 1, "Missing mode parameter.\n");
3412
3413 if (args[1] == "-verific" || args[1] == "-noverific") {
3414 if (args.size() != 2)
3415 cmd_error(args, 1, "Additional arguments to -verific/-noverific.\n");
3416 if (args[1] == "-verific") {
3417 if (!verific_available)
3418 cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
3419 use_verific = true;
3420 } else {
3421 use_verific = false;
3422 }
3423 return;
3424 }
3425
3426 if (args.size() < 3)
3427 cmd_error(args, 3, "Missing file name parameter.\n");
3428
3429 if (args[1] == "-vlog95" || args[1] == "-vlog2k") {
3430 if (use_verific) {
3431 args[0] = "verific";
3432 } else {
3433 args[0] = "read_verilog";
3434 args[1] = "-defer";
3435 }
3436 Pass::call(design, args);
3437 return;
3438 }
3439
3440 if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" || args[1] == "-sv" || args[1] == "-formal") {
3441 if (use_verific) {
3442 args[0] = "verific";
3443 } else {
3444 args[0] = "read_verilog";
3445 if (args[1] == "-formal")
3446 args.insert(args.begin()+1, std::string());
3447 args[1] = "-sv";
3448 args.insert(args.begin()+1, "-defer");
3449 }
3450 Pass::call(design, args);
3451 return;
3452 }
3453
3454 #ifdef VERIFIC_VHDL_SUPPORT
3455 if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl") {
3456 if (use_verific) {
3457 args[0] = "verific";
3458 Pass::call(design, args);
3459 } else {
3460 cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
3461 }
3462 return;
3463 }
3464 #endif
3465 if (args[1] == "-f" || args[1] == "-F") {
3466 if (use_verific) {
3467 args[0] = "verific";
3468 Pass::call(design, args);
3469 } else {
3470 cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
3471 }
3472 return;
3473 }
3474
3475 if (args[1] == "-define") {
3476 if (use_verific) {
3477 args[0] = "verific";
3478 args[1] = "-vlog-define";
3479 Pass::call(design, args);
3480 }
3481 args[0] = "verilog_defines";
3482 args.erase(args.begin()+1, args.begin()+2);
3483 for (int i = 1; i < GetSize(args); i++)
3484 args[i] = "-D" + args[i];
3485 Pass::call(design, args);
3486 return;
3487 }
3488
3489 if (args[1] == "-undef") {
3490 if (use_verific) {
3491 args[0] = "verific";
3492 args[1] = "-vlog-undef";
3493 Pass::call(design, args);
3494 }
3495 args[0] = "verilog_defines";
3496 args.erase(args.begin()+1, args.begin()+2);
3497 for (int i = 1; i < GetSize(args); i++)
3498 args[i] = "-U" + args[i];
3499 Pass::call(design, args);
3500 return;
3501 }
3502
3503 if (args[1] == "-incdir") {
3504 if (use_verific) {
3505 args[0] = "verific";
3506 args[1] = "-vlog-incdir";
3507 Pass::call(design, args);
3508 }
3509 args[0] = "verilog_defaults";
3510 args[1] = "-add";
3511 for (int i = 2; i < GetSize(args); i++)
3512 args[i] = "-I" + args[i];
3513 Pass::call(design, args);
3514 return;
3515 }
3516
3517 cmd_error(args, 1, "Missing or unsupported mode parameter.\n");
3518 }
3519 } ReadPass;
3520
3521 PRIVATE_NAMESPACE_END